X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Fi387-tdep.c;h=574914cab78f6b62a720a08e6a70de5b171d92ef;hb=6a2c1b8790e58ce0688507b5b1f8369aa621a665;hp=5842c004f62309737f8d8d063b4449aa7ccfc2b8;hpb=9a82579f3d1ba4b133844af18ec0a7fb0074dad9;p=deliverable%2Fbinutils-gdb.git
diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c
index 5842c004f6..574914cab7 100644
--- a/gdb/i387-tdep.c
+++ b/gdb/i387-tdep.c
@@ -1,12 +1,12 @@
/* Intel 387 floating point stuff.
- Copyright 1988, 1989, 1991, 1992, 1993, 1994, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
+
+ Copyright (C) 1988-2017 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -15,190 +15,52 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ along with this program. If not, see . */
#include "defs.h"
+#include "doublest.h"
+#include "floatformat.h"
#include "frame.h"
+#include "gdbcore.h"
#include "inferior.h"
#include "language.h"
-#include "value.h"
-#include "gdbcore.h"
-#include "floatformat.h"
#include "regcache.h"
-#include "gdb_assert.h"
-#include "doublest.h"
+#include "value.h"
-#if GDB_MULTI_ARCH >0
#include "i386-tdep.h"
-#endif
-
-/* FIXME: Eliminate the next two functions when we have the time to
- change all the callers. */
-
-void i387_to_double (char *from, char *to);
-void double_to_i387 (char *from, char *to);
-
-void
-i387_to_double (char *from, char *to)
-{
- floatformat_to_double (&floatformat_i387_ext, from, (double *) to);
-}
-
-void
-double_to_i387 (char *from, char *to)
-{
- floatformat_from_double (&floatformat_i387_ext, (double *) from, to);
-}
-
-
-/* FIXME: The functions on this page are used by the old `info float'
- implementations that a few of the i386 targets provide. These
- functions should be removed if all of these have been converted to
- use the generic implementation based on the new register file
- layout. */
-
-static void print_387_control_bits (unsigned int control);
-static void print_387_status_bits (unsigned int status);
-
-static void
-print_387_control_bits (unsigned int control)
-{
- switch ((control >> 8) & 3)
- {
- case 0:
- puts_unfiltered (" 24 bit; ");
- break;
- case 1:
- puts_unfiltered (" (bad); ");
- break;
- case 2:
- puts_unfiltered (" 53 bit; ");
- break;
- case 3:
- puts_unfiltered (" 64 bit; ");
- break;
- }
- switch ((control >> 10) & 3)
- {
- case 0:
- puts_unfiltered ("NEAR; ");
- break;
- case 1:
- puts_unfiltered ("DOWN; ");
- break;
- case 2:
- puts_unfiltered ("UP; ");
- break;
- case 3:
- puts_unfiltered ("CHOP; ");
- break;
- }
- if (control & 0x3f)
- {
- puts_unfiltered ("mask");
- if (control & 0x0001)
- puts_unfiltered (" INVAL");
- if (control & 0x0002)
- puts_unfiltered (" DENOR");
- if (control & 0x0004)
- puts_unfiltered (" DIVZ");
- if (control & 0x0008)
- puts_unfiltered (" OVERF");
- if (control & 0x0010)
- puts_unfiltered (" UNDER");
- if (control & 0x0020)
- puts_unfiltered (" LOS");
- puts_unfiltered (";");
- }
-
- if (control & 0xe080)
- warning ("\nreserved bits on: %s",
- local_hex_string (control & 0xe080));
-}
-
-void
-print_387_control_word (unsigned int control)
-{
- printf_filtered ("control %s:", local_hex_string(control & 0xffff));
- print_387_control_bits (control);
- puts_unfiltered ("\n");
-}
-
-static void
-print_387_status_bits (unsigned int status)
-{
- printf_unfiltered (" flags %d%d%d%d; ",
- (status & 0x4000) != 0,
- (status & 0x0400) != 0,
- (status & 0x0200) != 0,
- (status & 0x0100) != 0);
- printf_unfiltered ("top %d; ", (status >> 11) & 7);
- if (status & 0xff)
- {
- puts_unfiltered ("excep");
- if (status & 0x0001) puts_unfiltered (" INVAL");
- if (status & 0x0002) puts_unfiltered (" DENOR");
- if (status & 0x0004) puts_unfiltered (" DIVZ");
- if (status & 0x0008) puts_unfiltered (" OVERF");
- if (status & 0x0010) puts_unfiltered (" UNDER");
- if (status & 0x0020) puts_unfiltered (" LOS");
- if (status & 0x0040) puts_unfiltered (" STACK");
- }
-}
-
-void
-print_387_status_word (unsigned int status)
-{
- printf_filtered ("status %s:", local_hex_string (status & 0xffff));
- print_387_status_bits (status);
- puts_unfiltered ("\n");
-}
-
-
-/* Implement the `info float' layout based on the register definitions
- in `tm-i386.h'. */
+#include "i387-tdep.h"
+#include "x86-xstate.h"
/* Print the floating point number specified by RAW. */
+
static void
-print_i387_value (char *raw)
+print_i387_value (struct gdbarch *gdbarch,
+ const gdb_byte *raw, struct ui_file *file)
{
DOUBLEST value;
- int len = TARGET_LONG_DOUBLE_BIT / TARGET_CHAR_BIT;
- char *tmp = alloca (len);
-
- /* This code only works on targets where ... */
- gdb_assert (TARGET_LONG_DOUBLE_FORMAT == &floatformat_i387_ext);
-
- /* Take care of the padding. FP reg is 80 bits. The same value in
- memory is 96 bits. */
- gdb_assert (FPU_REG_RAW_SIZE < len);
- memcpy (tmp, raw, FPU_REG_RAW_SIZE);
- memset (tmp + FPU_REG_RAW_SIZE, 0, len - FPU_REG_RAW_SIZE);
-
- /* Extract the value as a DOUBLEST. */
- /* Use extract_floating() rather than floatformat_to_doublest().
- The latter is lossy in nature. Once GDB gets a host/target
- independent and non-lossy FP it will become possible to bypass
- extract_floating() and call floatformat*() directly. Note also
- the assumptions about TARGET_LONG_DOUBLE above. */
- value = extract_floating (tmp, len);
+
+ /* Using extract_typed_floating here might affect the representation
+ of certain numbers such as NaNs, even if GDB is running natively.
+ This is fine since our caller already detects such special
+ numbers and we print the hexadecimal representation anyway. */
+ value = extract_typed_floating (raw, i387_ext_type (gdbarch));
/* We try to print 19 digits. The last digit may or may not contain
garbage, but we'd better print one too many. We need enough room
to print the value, 1 position for the sign, 1 for the decimal
point, 19 for the digits and 6 for the exponent adds up to 27. */
#ifdef PRINTF_HAS_LONG_DOUBLE
- printf_filtered (" %-+27.19Lg", (long double) value);
+ fprintf_filtered (file, " %-+27.19Lg", (long double) value);
#else
- printf_filtered (" %-+27.19g", (double) value);
+ fprintf_filtered (file, " %-+27.19g", (double) value);
#endif
}
/* Print the classification for the register contents RAW. */
+
static void
-print_i387_ext (unsigned char *raw)
+print_i387_ext (struct gdbarch *gdbarch,
+ const gdb_byte *raw, struct ui_file *file)
{
int sign;
int integer;
@@ -216,190 +78,1804 @@ print_i387_ext (unsigned char *raw)
{
if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
/* Infinity. */
- printf_filtered (" %cInf", (sign ? '-' : '+'));
+ fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
/* Real Indefinite (QNaN). */
- puts_unfiltered (" Real Indefinite (QNaN)");
+ fputs_unfiltered (" Real Indefinite (QNaN)", file);
else if (fraction[1] & 0x40000000)
/* QNaN. */
- puts_filtered (" QNaN");
+ fputs_filtered (" QNaN", file);
else
/* SNaN. */
- puts_filtered (" SNaN");
+ fputs_filtered (" SNaN", file);
}
else if (exponent < 0x7fff && exponent > 0x0000 && integer)
/* Normal. */
- print_i387_value (raw);
+ print_i387_value (gdbarch, raw, file);
else if (exponent == 0x0000)
{
/* Denormal or zero. */
- print_i387_value (raw);
+ print_i387_value (gdbarch, raw, file);
if (integer)
/* Pseudo-denormal. */
- puts_filtered (" Pseudo-denormal");
+ fputs_filtered (" Pseudo-denormal", file);
else if (fraction[0] || fraction[1])
/* Denormal. */
- puts_filtered (" Denormal");
+ fputs_filtered (" Denormal", file);
}
else
/* Unsupported. */
- puts_filtered (" Unsupported");
+ fputs_filtered (" Unsupported", file);
}
-/* Print the status word STATUS. */
+/* Print the status word STATUS. If STATUS_P is false, then STATUS
+ was unavailable. */
+
static void
-print_i387_status_word (unsigned int status)
+print_i387_status_word (int status_p,
+ unsigned int status, struct ui_file *file)
{
- printf_filtered ("Status Word: %s",
- local_hex_string_custom (status, "04"));
- puts_filtered (" ");
- printf_filtered (" %s", (status & 0x0001) ? "IE" : " ");
- printf_filtered (" %s", (status & 0x0002) ? "DE" : " ");
- printf_filtered (" %s", (status & 0x0004) ? "ZE" : " ");
- printf_filtered (" %s", (status & 0x0008) ? "OE" : " ");
- printf_filtered (" %s", (status & 0x0010) ? "UE" : " ");
- printf_filtered (" %s", (status & 0x0020) ? "PE" : " ");
- puts_filtered (" ");
- printf_filtered (" %s", (status & 0x0080) ? "ES" : " ");
- puts_filtered (" ");
- printf_filtered (" %s", (status & 0x0040) ? "SF" : " ");
- puts_filtered (" ");
- printf_filtered (" %s", (status & 0x0100) ? "C0" : " ");
- printf_filtered (" %s", (status & 0x0200) ? "C1" : " ");
- printf_filtered (" %s", (status & 0x0400) ? "C2" : " ");
- printf_filtered (" %s", (status & 0x4000) ? "C3" : " ");
-
- puts_filtered ("\n");
-
- printf_filtered (" TOP: %d\n", ((status >> 11) & 7));
+ fprintf_filtered (file, "Status Word: ");
+ if (!status_p)
+ {
+ fprintf_filtered (file, "%s\n", _(""));
+ return;
+ }
+
+ fprintf_filtered (file, "%s", hex_string_custom (status, 4));
+ fputs_filtered (" ", file);
+ fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
+ fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
+ fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
+ fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
+ fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
+ fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
+ fputs_filtered (" ", file);
+ fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
+ fputs_filtered (" ", file);
+ fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
+ fputs_filtered (" ", file);
+ fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
+ fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
+ fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
+ fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
+
+ fputs_filtered ("\n", file);
+
+ fprintf_filtered (file,
+ " TOP: %d\n", ((status >> 11) & 7));
}
-/* Print the control word CONTROL. */
+/* Print the control word CONTROL. If CONTROL_P is false, then
+ CONTROL was unavailable. */
+
static void
-print_i387_control_word (unsigned int control)
+print_i387_control_word (int control_p,
+ unsigned int control, struct ui_file *file)
{
- printf_filtered ("Control Word: %s",
- local_hex_string_custom (control, "04"));
- puts_filtered (" ");
- printf_filtered (" %s", (control & 0x0001) ? "IM" : " ");
- printf_filtered (" %s", (control & 0x0002) ? "DM" : " ");
- printf_filtered (" %s", (control & 0x0004) ? "ZM" : " ");
- printf_filtered (" %s", (control & 0x0008) ? "OM" : " ");
- printf_filtered (" %s", (control & 0x0010) ? "UM" : " ");
- printf_filtered (" %s", (control & 0x0020) ? "PM" : " ");
-
- puts_filtered ("\n");
-
- puts_filtered (" PC: ");
+ fprintf_filtered (file, "Control Word: ");
+ if (!control_p)
+ {
+ fprintf_filtered (file, "%s\n", _(""));
+ return;
+ }
+
+ fprintf_filtered (file, "%s", hex_string_custom (control, 4));
+ fputs_filtered (" ", file);
+ fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
+ fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
+ fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
+ fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
+ fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
+ fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
+
+ fputs_filtered ("\n", file);
+
+ fputs_filtered (" PC: ", file);
switch ((control >> 8) & 3)
{
case 0:
- puts_filtered ("Single Precision (24-bits)\n");
+ fputs_filtered ("Single Precision (24-bits)\n", file);
break;
case 1:
- puts_filtered ("Reserved\n");
+ fputs_filtered ("Reserved\n", file);
break;
case 2:
- puts_filtered ("Double Precision (53-bits)\n");
+ fputs_filtered ("Double Precision (53-bits)\n", file);
break;
case 3:
- puts_filtered ("Extended Precision (64-bits)\n");
+ fputs_filtered ("Extended Precision (64-bits)\n", file);
break;
}
- puts_filtered (" RC: ");
+ fputs_filtered (" RC: ", file);
switch ((control >> 10) & 3)
{
case 0:
- puts_filtered ("Round to nearest\n");
+ fputs_filtered ("Round to nearest\n", file);
break;
case 1:
- puts_filtered ("Round down\n");
+ fputs_filtered ("Round down\n", file);
break;
case 2:
- puts_filtered ("Round up\n");
+ fputs_filtered ("Round up\n", file);
break;
case 3:
- puts_filtered ("Round toward zero\n");
+ fputs_filtered ("Round toward zero\n", file);
break;
}
}
-/* Print out the i387 floating poin state. */
+/* Print out the i387 floating point state. Note that we ignore FRAME
+ in the code below. That's OK since floating-point registers are
+ never saved on the stack. */
+
void
-i387_float_info (void)
+i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
+ struct frame_info *frame, const char *args)
{
- unsigned int fctrl;
- unsigned int fstat;
- unsigned int ftag;
- unsigned int fiseg;
- unsigned int fioff;
- unsigned int foseg;
- unsigned int fooff;
- unsigned int fop;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
+ ULONGEST fctrl;
+ int fctrl_p;
+ ULONGEST fstat;
+ int fstat_p;
+ ULONGEST ftag;
+ int ftag_p;
+ ULONGEST fiseg;
+ int fiseg_p;
+ ULONGEST fioff;
+ int fioff_p;
+ ULONGEST foseg;
+ int foseg_p;
+ ULONGEST fooff;
+ int fooff_p;
+ ULONGEST fop;
+ int fop_p;
int fpreg;
int top;
- fctrl = read_register (FCTRL_REGNUM);
- fstat = read_register (FSTAT_REGNUM);
- ftag = read_register (FTAG_REGNUM);
- fiseg = read_register (FCS_REGNUM);
- fioff = read_register (FCOFF_REGNUM);
- foseg = read_register (FDS_REGNUM);
- fooff = read_register (FDOFF_REGNUM);
- fop = read_register (FOP_REGNUM);
-
- top = ((fstat >> 11) & 7);
-
- for (fpreg = 7; fpreg >= 0; fpreg--)
+ gdb_assert (gdbarch == get_frame_arch (frame));
+
+ fctrl_p = read_frame_register_unsigned (frame,
+ I387_FCTRL_REGNUM (tdep), &fctrl);
+ fstat_p = read_frame_register_unsigned (frame,
+ I387_FSTAT_REGNUM (tdep), &fstat);
+ ftag_p = read_frame_register_unsigned (frame,
+ I387_FTAG_REGNUM (tdep), &ftag);
+ fiseg_p = read_frame_register_unsigned (frame,
+ I387_FISEG_REGNUM (tdep), &fiseg);
+ fioff_p = read_frame_register_unsigned (frame,
+ I387_FIOFF_REGNUM (tdep), &fioff);
+ foseg_p = read_frame_register_unsigned (frame,
+ I387_FOSEG_REGNUM (tdep), &foseg);
+ fooff_p = read_frame_register_unsigned (frame,
+ I387_FOOFF_REGNUM (tdep), &fooff);
+ fop_p = read_frame_register_unsigned (frame,
+ I387_FOP_REGNUM (tdep), &fop);
+
+ if (fstat_p)
+ {
+ top = ((fstat >> 11) & 7);
+
+ for (fpreg = 7; fpreg >= 0; fpreg--)
+ {
+ struct value *regval;
+ int regnum;
+ int i;
+ int tag = -1;
+
+ fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
+
+ if (ftag_p)
+ {
+ tag = (ftag >> (fpreg * 2)) & 3;
+
+ switch (tag)
+ {
+ case 0:
+ fputs_filtered ("Valid ", file);
+ break;
+ case 1:
+ fputs_filtered ("Zero ", file);
+ break;
+ case 2:
+ fputs_filtered ("Special ", file);
+ break;
+ case 3:
+ fputs_filtered ("Empty ", file);
+ break;
+ }
+ }
+ else
+ fputs_filtered ("Unknown ", file);
+
+ regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
+ regval = get_frame_register_value (frame, regnum);
+
+ if (value_entirely_available (regval))
+ {
+ const gdb_byte *raw = value_contents (regval);
+
+ fputs_filtered ("0x", file);
+ for (i = 9; i >= 0; i--)
+ fprintf_filtered (file, "%02x", raw[i]);
+
+ if (tag != -1 && tag != 3)
+ print_i387_ext (gdbarch, raw, file);
+ }
+ else
+ fprintf_filtered (file, "%s", _(""));
+
+ fputs_filtered ("\n", file);
+ }
+ }
+
+ fputs_filtered ("\n", file);
+ print_i387_status_word (fstat_p, fstat, file);
+ print_i387_control_word (fctrl_p, fctrl, file);
+ fprintf_filtered (file, "Tag Word: %s\n",
+ ftag_p ? hex_string_custom (ftag, 4) : _(""));
+ fprintf_filtered (file, "Instruction Pointer: %s:",
+ fiseg_p ? hex_string_custom (fiseg, 2) : _(""));
+ fprintf_filtered (file, "%s\n",
+ fioff_p ? hex_string_custom (fioff, 8) : _(""));
+ fprintf_filtered (file, "Operand Pointer: %s:",
+ foseg_p ? hex_string_custom (foseg, 2) : _(""));
+ fprintf_filtered (file, "%s\n",
+ fooff_p ? hex_string_custom (fooff, 8) : _(""));
+ fprintf_filtered (file, "Opcode: %s\n",
+ fop_p
+ ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
+ : _(""));
+}
+
+
+/* Return nonzero if a value of type TYPE stored in register REGNUM
+ needs any special handling. */
+
+int
+i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
+ struct type *type)
+{
+ if (i386_fp_regnum_p (gdbarch, regnum))
+ {
+ /* Floating point registers must be converted unless we are
+ accessing them in their hardware type or TYPE is not float. */
+ if (type == i387_ext_type (gdbarch)
+ || TYPE_CODE (type) != TYPE_CODE_FLT)
+ return 0;
+ else
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Read a value of type TYPE from register REGNUM in frame FRAME, and
+ return its contents in TO. */
+
+int
+i387_register_to_value (struct frame_info *frame, int regnum,
+ struct type *type, gdb_byte *to,
+ int *optimizedp, int *unavailablep)
+{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ gdb_byte from[I386_MAX_REGISTER_SIZE];
+
+ gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
+
+ /* We only support floating-point values. */
+ if (TYPE_CODE (type) != TYPE_CODE_FLT)
+ {
+ warning (_("Cannot convert floating-point register value "
+ "to non-floating-point type."));
+ *optimizedp = *unavailablep = 0;
+ return 0;
+ }
+
+ /* Convert to TYPE. */
+ if (!get_frame_register_bytes (frame, regnum, 0,
+ register_size (gdbarch, regnum),
+ from, optimizedp, unavailablep))
+ return 0;
+
+ convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
+ *optimizedp = *unavailablep = 0;
+ return 1;
+}
+
+/* Write the contents FROM of a value of type TYPE into register
+ REGNUM in frame FRAME. */
+
+void
+i387_value_to_register (struct frame_info *frame, int regnum,
+ struct type *type, const gdb_byte *from)
+{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ gdb_byte to[I386_MAX_REGISTER_SIZE];
+
+ gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
+
+ /* We only support floating-point values. */
+ if (TYPE_CODE (type) != TYPE_CODE_FLT)
+ {
+ warning (_("Cannot convert non-floating-point type "
+ "to floating-point register value."));
+ return;
+ }
+
+ /* Convert from TYPE. */
+ convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
+ put_frame_register (frame, regnum, to);
+}
+
+
+/* Handle FSAVE and FXSAVE formats. */
+
+/* At fsave_offset[REGNUM] you'll find the offset to the location in
+ the data structure used by the "fsave" instruction where GDB
+ register REGNUM is stored. */
+
+static int fsave_offset[] =
+{
+ 28 + 0 * 10, /* %st(0) ... */
+ 28 + 1 * 10,
+ 28 + 2 * 10,
+ 28 + 3 * 10,
+ 28 + 4 * 10,
+ 28 + 5 * 10,
+ 28 + 6 * 10,
+ 28 + 7 * 10, /* ... %st(7). */
+ 0, /* `fctrl' (16 bits). */
+ 4, /* `fstat' (16 bits). */
+ 8, /* `ftag' (16 bits). */
+ 16, /* `fiseg' (16 bits). */
+ 12, /* `fioff'. */
+ 24, /* `foseg' (16 bits). */
+ 20, /* `fooff'. */
+ 18 /* `fop' (bottom 11 bits). */
+};
+
+#define FSAVE_ADDR(tdep, fsave, regnum) \
+ (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
+
+
+/* Fill register REGNUM in REGCACHE with the appropriate value from
+ *FSAVE. This function masks off any of the reserved bits in
+ *FSAVE. */
+
+void
+i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ const gdb_byte *regs = (const gdb_byte *) fsave;
+ int i;
+
+ gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
+
+ for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
+ if (regnum == -1 || regnum == i)
+ {
+ if (fsave == NULL)
+ {
+ regcache_raw_supply (regcache, i, NULL);
+ continue;
+ }
+
+ /* Most of the FPU control registers occupy only 16 bits in the
+ fsave area. Give those a special treatment. */
+ if (i >= I387_FCTRL_REGNUM (tdep)
+ && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
+ {
+ gdb_byte val[4];
+
+ memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
+ val[2] = val[3] = 0;
+ if (i == I387_FOP_REGNUM (tdep))
+ val[1] &= ((1 << 3) - 1);
+ regcache_raw_supply (regcache, i, val);
+ }
+ else
+ regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
+ }
+
+ /* Provide dummy values for the SSE registers. */
+ for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
+ if (regnum == -1 || regnum == i)
+ regcache_raw_supply (regcache, i, NULL);
+ if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
+ {
+ gdb_byte buf[4];
+
+ store_unsigned_integer (buf, 4, byte_order, 0x1f80);
+ regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
+ }
+}
+
+/* Fill register REGNUM (if it is a floating-point register) in *FSAVE
+ with the value from REGCACHE. If REGNUM is -1, do this for all
+ registers. This function doesn't touch any of the reserved bits in
+ *FSAVE. */
+
+void
+i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
+ gdb_byte *regs = (gdb_byte *) fsave;
+ int i;
+
+ gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
+
+ for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
+ if (regnum == -1 || regnum == i)
+ {
+ /* Most of the FPU control registers occupy only 16 bits in
+ the fsave area. Give those a special treatment. */
+ if (i >= I387_FCTRL_REGNUM (tdep)
+ && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
+ {
+ gdb_byte buf[4];
+
+ regcache_raw_collect (regcache, i, buf);
+
+ if (i == I387_FOP_REGNUM (tdep))
+ {
+ /* The opcode occupies only 11 bits. Make sure we
+ don't touch the other bits. */
+ buf[1] &= ((1 << 3) - 1);
+ buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
+ }
+ memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
+ }
+ else
+ regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
+ }
+}
+
+
+/* At fxsave_offset[REGNUM] you'll find the offset to the location in
+ the data structure used by the "fxsave" instruction where GDB
+ register REGNUM is stored. */
+
+static int fxsave_offset[] =
+{
+ 32, /* %st(0) through ... */
+ 48,
+ 64,
+ 80,
+ 96,
+ 112,
+ 128,
+ 144, /* ... %st(7) (80 bits each). */
+ 0, /* `fctrl' (16 bits). */
+ 2, /* `fstat' (16 bits). */
+ 4, /* `ftag' (16 bits). */
+ 12, /* `fiseg' (16 bits). */
+ 8, /* `fioff'. */
+ 20, /* `foseg' (16 bits). */
+ 16, /* `fooff'. */
+ 6, /* `fop' (bottom 11 bits). */
+ 160 + 0 * 16, /* %xmm0 through ... */
+ 160 + 1 * 16,
+ 160 + 2 * 16,
+ 160 + 3 * 16,
+ 160 + 4 * 16,
+ 160 + 5 * 16,
+ 160 + 6 * 16,
+ 160 + 7 * 16,
+ 160 + 8 * 16,
+ 160 + 9 * 16,
+ 160 + 10 * 16,
+ 160 + 11 * 16,
+ 160 + 12 * 16,
+ 160 + 13 * 16,
+ 160 + 14 * 16,
+ 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
+};
+
+#define FXSAVE_ADDR(tdep, fxsave, regnum) \
+ (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
+
+/* We made an unfortunate choice in putting %mxcsr after the SSE
+ registers %xmm0-%xmm7 instead of before, since it makes supporting
+ the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
+ don't include the offset for %mxcsr here above. */
+
+#define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
+
+static int i387_tag (const gdb_byte *raw);
+
+
+/* Fill register REGNUM in REGCACHE with the appropriate
+ floating-point or SSE register value from *FXSAVE. This function
+ masks off any of the reserved bits in *FXSAVE. */
+
+void
+i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
+ const gdb_byte *regs = (const gdb_byte *) fxsave;
+ int i;
+
+ gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
+ gdb_assert (tdep->num_xmm_regs > 0);
+
+ for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
+ if (regnum == -1 || regnum == i)
+ {
+ if (regs == NULL)
+ {
+ regcache_raw_supply (regcache, i, NULL);
+ continue;
+ }
+
+ /* Most of the FPU control registers occupy only 16 bits in
+ the fxsave area. Give those a special treatment. */
+ if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
+ && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
+ {
+ gdb_byte val[4];
+
+ memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
+ val[2] = val[3] = 0;
+ if (i == I387_FOP_REGNUM (tdep))
+ val[1] &= ((1 << 3) - 1);
+ else if (i== I387_FTAG_REGNUM (tdep))
+ {
+ /* The fxsave area contains a simplified version of
+ the tag word. We have to look at the actual 80-bit
+ FP data to recreate the traditional i387 tag word. */
+
+ unsigned long ftag = 0;
+ int fpreg;
+ int top;
+
+ top = ((FXSAVE_ADDR (tdep, regs,
+ I387_FSTAT_REGNUM (tdep)))[1] >> 3);
+ top &= 0x7;
+
+ for (fpreg = 7; fpreg >= 0; fpreg--)
+ {
+ int tag;
+
+ if (val[0] & (1 << fpreg))
+ {
+ int thisreg = (fpreg + 8 - top) % 8
+ + I387_ST0_REGNUM (tdep);
+ tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
+ }
+ else
+ tag = 3; /* Empty */
+
+ ftag |= tag << (2 * fpreg);
+ }
+ val[0] = ftag & 0xff;
+ val[1] = (ftag >> 8) & 0xff;
+ }
+ regcache_raw_supply (regcache, i, val);
+ }
+ else
+ regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
+ }
+
+ if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
+ {
+ if (regs == NULL)
+ regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
+ else
+ regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
+ FXSAVE_MXCSR_ADDR (regs));
+ }
+}
+
+/* Fill register REGNUM (if it is a floating-point or SSE register) in
+ *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
+ all registers. This function doesn't touch any of the reserved
+ bits in *FXSAVE. */
+
+void
+i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
+ gdb_byte *regs = (gdb_byte *) fxsave;
+ int i;
+
+ gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
+ gdb_assert (tdep->num_xmm_regs > 0);
+
+ for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
+ if (regnum == -1 || regnum == i)
+ {
+ /* Most of the FPU control registers occupy only 16 bits in
+ the fxsave area. Give those a special treatment. */
+ if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
+ && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
+ {
+ gdb_byte buf[4];
+
+ regcache_raw_collect (regcache, i, buf);
+
+ if (i == I387_FOP_REGNUM (tdep))
+ {
+ /* The opcode occupies only 11 bits. Make sure we
+ don't touch the other bits. */
+ buf[1] &= ((1 << 3) - 1);
+ buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
+ }
+ else if (i == I387_FTAG_REGNUM (tdep))
+ {
+ /* Converting back is much easier. */
+
+ unsigned short ftag;
+ int fpreg;
+
+ ftag = (buf[1] << 8) | buf[0];
+ buf[0] = 0;
+ buf[1] = 0;
+
+ for (fpreg = 7; fpreg >= 0; fpreg--)
+ {
+ int tag = (ftag >> (fpreg * 2)) & 3;
+
+ if (tag != 3)
+ buf[0] |= (1 << fpreg);
+ }
+ }
+ memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
+ }
+ else
+ regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
+ }
+
+ if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
+ regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
+ FXSAVE_MXCSR_ADDR (regs));
+}
+
+/* `xstate_bv' is at byte offset 512. */
+#define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
+
+/* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
+ the upper 128bit of AVX register data structure used by the "xsave"
+ instruction where GDB register REGNUM is stored. */
+
+static int xsave_avxh_offset[] =
+{
+ 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
+ 576 + 1 * 16,
+ 576 + 2 * 16,
+ 576 + 3 * 16,
+ 576 + 4 * 16,
+ 576 + 5 * 16,
+ 576 + 6 * 16,
+ 576 + 7 * 16,
+ 576 + 8 * 16,
+ 576 + 9 * 16,
+ 576 + 10 * 16,
+ 576 + 11 * 16,
+ 576 + 12 * 16,
+ 576 + 13 * 16,
+ 576 + 14 * 16,
+ 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
+};
+
+#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
+ (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
+
+/* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
+ the upper 128bit of ZMM register data structure used by the "xsave"
+ instruction where GDB register REGNUM is stored. */
+
+static int xsave_ymm_avx512_offset[] =
+{
+ /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
+ 1664 + 16 + 0 * 64, /* %ymm16 through... */
+ 1664 + 16 + 1 * 64,
+ 1664 + 16 + 2 * 64,
+ 1664 + 16 + 3 * 64,
+ 1664 + 16 + 4 * 64,
+ 1664 + 16 + 5 * 64,
+ 1664 + 16 + 6 * 64,
+ 1664 + 16 + 7 * 64,
+ 1664 + 16 + 8 * 64,
+ 1664 + 16 + 9 * 64,
+ 1664 + 16 + 10 * 64,
+ 1664 + 16 + 11 * 64,
+ 1664 + 16 + 12 * 64,
+ 1664 + 16 + 13 * 64,
+ 1664 + 16 + 14 * 64,
+ 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
+};
+
+#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
+ (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
+
+static int xsave_xmm_avx512_offset[] =
+{
+ 1664 + 0 * 64, /* %ymm16 through... */
+ 1664 + 1 * 64,
+ 1664 + 2 * 64,
+ 1664 + 3 * 64,
+ 1664 + 4 * 64,
+ 1664 + 5 * 64,
+ 1664 + 6 * 64,
+ 1664 + 7 * 64,
+ 1664 + 8 * 64,
+ 1664 + 9 * 64,
+ 1664 + 10 * 64,
+ 1664 + 11 * 64,
+ 1664 + 12 * 64,
+ 1664 + 13 * 64,
+ 1664 + 14 * 64,
+ 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
+};
+
+#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
+ (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
+
+static int xsave_mpx_offset[] = {
+ 960 + 0 * 16, /* bnd0r...bnd3r registers. */
+ 960 + 1 * 16,
+ 960 + 2 * 16,
+ 960 + 3 * 16,
+ 1024 + 0 * 8, /* bndcfg ... bndstatus. */
+ 1024 + 1 * 8,
+};
+
+#define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
+ (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
+
+ /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
+ of the AVX512 opmask register data structure used by the "xsave"
+ instruction where GDB register REGNUM is stored. */
+
+static int xsave_avx512_k_offset[] =
+{
+ 1088 + 0 * 8, /* %k0 through... */
+ 1088 + 1 * 8,
+ 1088 + 2 * 8,
+ 1088 + 3 * 8,
+ 1088 + 4 * 8,
+ 1088 + 5 * 8,
+ 1088 + 6 * 8,
+ 1088 + 7 * 8 /* %k7 (64 bits each). */
+};
+
+#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
+ (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
+
+/* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
+ the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
+ instruction where GDB register REGNUM is stored. */
+
+static int xsave_avx512_zmm_h_offset[] =
+{
+ 1152 + 0 * 32,
+ 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
+ 1152 + 2 * 32,
+ 1152 + 3 * 32,
+ 1152 + 4 * 32,
+ 1152 + 5 * 32,
+ 1152 + 6 * 32,
+ 1152 + 7 * 32,
+ 1152 + 8 * 32,
+ 1152 + 9 * 32,
+ 1152 + 10 * 32,
+ 1152 + 11 * 32,
+ 1152 + 12 * 32,
+ 1152 + 13 * 32,
+ 1152 + 14 * 32,
+ 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
+ 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
+ 1664 + 32 + 1 * 64,
+ 1664 + 32 + 2 * 64,
+ 1664 + 32 + 3 * 64,
+ 1664 + 32 + 4 * 64,
+ 1664 + 32 + 5 * 64,
+ 1664 + 32 + 6 * 64,
+ 1664 + 32 + 7 * 64,
+ 1664 + 32 + 8 * 64,
+ 1664 + 32 + 9 * 64,
+ 1664 + 32 + 10 * 64,
+ 1664 + 32 + 11 * 64,
+ 1664 + 32 + 12 * 64,
+ 1664 + 32 + 13 * 64,
+ 1664 + 32 + 14 * 64,
+ 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
+};
+
+#define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
+ (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
+
+/* At xsave_pkeys_offset[REGNUM] you find the offset to the location
+ of the PKRU register data structure used by the "xsave"
+ instruction where GDB register REGNUM is stored. */
+
+static int xsave_pkeys_offset[] =
+{
+2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
+ instructions and applications). */
+};
+
+#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
+ (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
+
+/* Similar to i387_supply_fxsave, but use XSAVE extended state. */
+
+void
+i387_supply_xsave (struct regcache *regcache, int regnum,
+ const void *xsave)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const gdb_byte *regs = (const gdb_byte *) xsave;
+ int i;
+ ULONGEST clear_bv;
+ static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
+ enum
+ {
+ none = 0x0,
+ x87 = 0x1,
+ sse = 0x2,
+ avxh = 0x4,
+ mpx = 0x8,
+ avx512_k = 0x10,
+ avx512_zmm_h = 0x20,
+ avx512_ymmh_avx512 = 0x40,
+ avx512_xmm_avx512 = 0x80,
+ pkeys = 0x100,
+ all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
+ | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
+ } regclass;
+
+ gdb_assert (regs != NULL);
+ gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
+ gdb_assert (tdep->num_xmm_regs > 0);
+
+ if (regnum == -1)
+ regclass = all;
+ else if (regnum >= I387_PKRU_REGNUM (tdep)
+ && regnum < I387_PKEYSEND_REGNUM (tdep))
+ regclass = pkeys;
+ else if (regnum >= I387_ZMM0H_REGNUM (tdep)
+ && regnum < I387_ZMMENDH_REGNUM (tdep))
+ regclass = avx512_zmm_h;
+ else if (regnum >= I387_K0_REGNUM (tdep)
+ && regnum < I387_KEND_REGNUM (tdep))
+ regclass = avx512_k;
+ else if (regnum >= I387_YMM16H_REGNUM (tdep)
+ && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
+ regclass = avx512_ymmh_avx512;
+ else if (regnum >= I387_XMM16_REGNUM (tdep)
+ && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
+ regclass = avx512_xmm_avx512;
+ else if (regnum >= I387_YMM0H_REGNUM (tdep)
+ && regnum < I387_YMMENDH_REGNUM (tdep))
+ regclass = avxh;
+ else if (regnum >= I387_BND0R_REGNUM (tdep)
+ && regnum < I387_MPXEND_REGNUM (tdep))
+ regclass = mpx;
+ else if (regnum >= I387_XMM0_REGNUM (tdep)
+ && regnum < I387_MXCSR_REGNUM (tdep))
+ regclass = sse;
+ else if (regnum >= I387_ST0_REGNUM (tdep)
+ && regnum < I387_FCTRL_REGNUM (tdep))
+ regclass = x87;
+ else
+ regclass = none;
+
+ if (regclass != none)
+ {
+ /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ ULONGEST xstate_bv = 0;
+
+ xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
+ 8, byte_order);
+
+ /* Clear part in vector registers if its bit in xstat_bv is zero. */
+ clear_bv = (~(xstate_bv)) & tdep->xcr0;
+ }
+ else
+ clear_bv = X86_XSTATE_ALL_MASK;
+
+ /* With the delayed xsave mechanism, in between the program
+ starting, and the program accessing the vector registers for the
+ first time, the register's values are invalid. The kernel
+ initializes register states to zero when they are set the first
+ time in a program. This means that from the user-space programs'
+ perspective, it's the same as if the registers have always been
+ zero from the start of the program. Therefore, the debugger
+ should provide the same illusion to the user. */
+
+ switch (regclass)
+ {
+ case none:
+ break;
+
+ case pkeys:
+ if ((clear_bv & X86_XSTATE_PKRU))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ XSAVE_PKEYS_ADDR (tdep, regs, regnum));
+ return;
+
+ case avx512_zmm_h:
+ if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
+ return;
+
+ case avx512_k:
+ if ((clear_bv & X86_XSTATE_K))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
+ return;
+
+ case avx512_ymmh_avx512:
+ if ((clear_bv & X86_XSTATE_ZMM))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
+ return;
+
+ case avx512_xmm_avx512:
+ if ((clear_bv & X86_XSTATE_ZMM))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
+ return;
+
+ case avxh:
+ if ((clear_bv & X86_XSTATE_AVX))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ XSAVE_AVXH_ADDR (tdep, regs, regnum));
+ return;
+
+ case mpx:
+ if ((clear_bv & X86_XSTATE_BNDREGS))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ XSAVE_MPX_ADDR (tdep, regs, regnum));
+ return;
+
+ case sse:
+ if ((clear_bv & X86_XSTATE_SSE))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ FXSAVE_ADDR (tdep, regs, regnum));
+ return;
+
+ case x87:
+ if ((clear_bv & X86_XSTATE_X87))
+ regcache_raw_supply (regcache, regnum, zero);
+ else
+ regcache_raw_supply (regcache, regnum,
+ FXSAVE_ADDR (tdep, regs, regnum));
+ return;
+
+ case all:
+ /* Handle PKEYS registers. */
+ if ((tdep->xcr0 & X86_XSTATE_PKRU))
+ {
+ if ((clear_bv & X86_XSTATE_PKRU))
+ {
+ for (i = I387_PKRU_REGNUM (tdep);
+ i < I387_PKEYSEND_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_PKRU_REGNUM (tdep);
+ i < I387_PKEYSEND_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_PKEYS_ADDR (tdep, regs, i));
+ }
+ }
+
+ /* Handle the upper ZMM registers. */
+ if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
+ {
+ if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
+ {
+ for (i = I387_ZMM0H_REGNUM (tdep);
+ i < I387_ZMMENDH_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_ZMM0H_REGNUM (tdep);
+ i < I387_ZMMENDH_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
+ }
+ }
+
+ /* Handle AVX512 OpMask registers. */
+ if ((tdep->xcr0 & X86_XSTATE_K))
+ {
+ if ((clear_bv & X86_XSTATE_K))
+ {
+ for (i = I387_K0_REGNUM (tdep);
+ i < I387_KEND_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_K0_REGNUM (tdep);
+ i < I387_KEND_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_AVX512_K_ADDR (tdep, regs, i));
+ }
+ }
+
+ /* Handle the YMM_AVX512 registers. */
+ if ((tdep->xcr0 & X86_XSTATE_ZMM))
+ {
+ if ((clear_bv & X86_XSTATE_ZMM))
+ {
+ for (i = I387_YMM16H_REGNUM (tdep);
+ i < I387_YMMH_AVX512_END_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ for (i = I387_XMM16_REGNUM (tdep);
+ i < I387_XMM_AVX512_END_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_YMM16H_REGNUM (tdep);
+ i < I387_YMMH_AVX512_END_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
+ for (i = I387_XMM16_REGNUM (tdep);
+ i < I387_XMM_AVX512_END_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
+ }
+ }
+ /* Handle the upper YMM registers. */
+ if ((tdep->xcr0 & X86_XSTATE_AVX))
+ {
+ if ((clear_bv & X86_XSTATE_AVX))
+ {
+ for (i = I387_YMM0H_REGNUM (tdep);
+ i < I387_YMMENDH_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_YMM0H_REGNUM (tdep);
+ i < I387_YMMENDH_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_AVXH_ADDR (tdep, regs, i));
+ }
+ }
+
+ /* Handle the MPX registers. */
+ if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
+ {
+ if (clear_bv & X86_XSTATE_BNDREGS)
+ {
+ for (i = I387_BND0R_REGNUM (tdep);
+ i < I387_BNDCFGU_REGNUM (tdep); i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_BND0R_REGNUM (tdep);
+ i < I387_BNDCFGU_REGNUM (tdep); i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_MPX_ADDR (tdep, regs, i));
+ }
+ }
+
+ /* Handle the MPX registers. */
+ if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
+ {
+ if (clear_bv & X86_XSTATE_BNDCFG)
+ {
+ for (i = I387_BNDCFGU_REGNUM (tdep);
+ i < I387_MPXEND_REGNUM (tdep); i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_BNDCFGU_REGNUM (tdep);
+ i < I387_MPXEND_REGNUM (tdep); i++)
+ regcache_raw_supply (regcache, i,
+ XSAVE_MPX_ADDR (tdep, regs, i));
+ }
+ }
+
+ /* Handle the XMM registers. */
+ if ((tdep->xcr0 & X86_XSTATE_SSE))
+ {
+ if ((clear_bv & X86_XSTATE_SSE))
+ {
+ for (i = I387_XMM0_REGNUM (tdep);
+ i < I387_MXCSR_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_XMM0_REGNUM (tdep);
+ i < I387_MXCSR_REGNUM (tdep); i++)
+ regcache_raw_supply (regcache, i,
+ FXSAVE_ADDR (tdep, regs, i));
+ }
+ }
+
+ /* Handle the x87 registers. */
+ if ((tdep->xcr0 & X86_XSTATE_X87))
+ {
+ if ((clear_bv & X86_XSTATE_X87))
+ {
+ for (i = I387_ST0_REGNUM (tdep);
+ i < I387_FCTRL_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, zero);
+ }
+ else
+ {
+ for (i = I387_ST0_REGNUM (tdep);
+ i < I387_FCTRL_REGNUM (tdep);
+ i++)
+ regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
+ }
+ }
+ break;
+ }
+
+ /* Only handle x87 control registers. */
+ for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
+ if (regnum == -1 || regnum == i)
+ {
+ /* Most of the FPU control registers occupy only 16 bits in
+ the xsave extended state. Give those a special treatment. */
+ if (i != I387_FIOFF_REGNUM (tdep)
+ && i != I387_FOOFF_REGNUM (tdep))
+ {
+ gdb_byte val[4];
+
+ memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
+ val[2] = val[3] = 0;
+ if (i == I387_FOP_REGNUM (tdep))
+ val[1] &= ((1 << 3) - 1);
+ else if (i== I387_FTAG_REGNUM (tdep))
+ {
+ /* The fxsave area contains a simplified version of
+ the tag word. We have to look at the actual 80-bit
+ FP data to recreate the traditional i387 tag word. */
+
+ unsigned long ftag = 0;
+ int fpreg;
+ int top;
+
+ top = ((FXSAVE_ADDR (tdep, regs,
+ I387_FSTAT_REGNUM (tdep)))[1] >> 3);
+ top &= 0x7;
+
+ for (fpreg = 7; fpreg >= 0; fpreg--)
+ {
+ int tag;
+
+ if (val[0] & (1 << fpreg))
+ {
+ int thisreg = (fpreg + 8 - top) % 8
+ + I387_ST0_REGNUM (tdep);
+ tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
+ }
+ else
+ tag = 3; /* Empty */
+
+ ftag |= tag << (2 * fpreg);
+ }
+ val[0] = ftag & 0xff;
+ val[1] = (ftag >> 8) & 0xff;
+ }
+ regcache_raw_supply (regcache, i, val);
+ }
+ else
+ regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
+ }
+
+ if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
+ regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
+ FXSAVE_MXCSR_ADDR (regs));
+}
+
+/* Similar to i387_collect_fxsave, but use XSAVE extended state. */
+
+void
+i387_collect_xsave (const struct regcache *regcache, int regnum,
+ void *xsave, int gcore)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ gdb_byte *regs = (gdb_byte *) xsave;
+ int i;
+ enum
{
- unsigned char raw[FPU_REG_RAW_SIZE];
- int tag = (ftag >> (fpreg * 2)) & 3;
- int i;
+ none = 0x0,
+ check = 0x1,
+ x87 = 0x2 | check,
+ sse = 0x4 | check,
+ avxh = 0x8 | check,
+ mpx = 0x10 | check,
+ avx512_k = 0x20 | check,
+ avx512_zmm_h = 0x40 | check,
+ avx512_ymmh_avx512 = 0x80 | check,
+ avx512_xmm_avx512 = 0x100 | check,
+ pkeys = 0x200 | check,
+ all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
+ | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
+ } regclass;
- printf_filtered ("%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
+ gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
+ gdb_assert (tdep->num_xmm_regs > 0);
- switch (tag)
+ if (regnum == -1)
+ regclass = all;
+ else if (regnum >= I387_PKRU_REGNUM (tdep)
+ && regnum < I387_PKEYSEND_REGNUM (tdep))
+ regclass = pkeys;
+ else if (regnum >= I387_ZMM0H_REGNUM (tdep)
+ && regnum < I387_ZMMENDH_REGNUM (tdep))
+ regclass = avx512_zmm_h;
+ else if (regnum >= I387_K0_REGNUM (tdep)
+ && regnum < I387_KEND_REGNUM (tdep))
+ regclass = avx512_k;
+ else if (regnum >= I387_YMM16H_REGNUM (tdep)
+ && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
+ regclass = avx512_ymmh_avx512;
+ else if (regnum >= I387_XMM16_REGNUM (tdep)
+ && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
+ regclass = avx512_xmm_avx512;
+ else if (regnum >= I387_YMM0H_REGNUM (tdep)
+ && regnum < I387_YMMENDH_REGNUM (tdep))
+ regclass = avxh;
+ else if (regnum >= I387_BND0R_REGNUM (tdep)
+ && regnum < I387_MPXEND_REGNUM (tdep))
+ regclass = mpx;
+ else if (regnum >= I387_XMM0_REGNUM (tdep)
+ && regnum < I387_MXCSR_REGNUM (tdep))
+ regclass = sse;
+ else if (regnum >= I387_ST0_REGNUM (tdep)
+ && regnum < I387_FCTRL_REGNUM (tdep))
+ regclass = x87;
+ else
+ regclass = none;
+
+ if (gcore)
+ {
+ /* Clear XSAVE extended state. */
+ memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0));
+
+ /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
+ if (tdep->xsave_xcr0_offset != -1)
+ memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
+ memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
+ }
+
+ if ((regclass & check))
+ {
+ gdb_byte raw[I386_MAX_REGISTER_SIZE];
+ ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
+ gdb_byte *p;
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+
+ /* The supported bits in `xstat_bv' are 8 bytes. */
+ initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
+ 8, byte_order);
+ clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
+
+ /* Clear register set if its bit in xstat_bv is zero. */
+ if (clear_bv)
{
- case 0:
- puts_filtered ("Valid ");
- break;
- case 1:
- puts_filtered ("Zero ");
- break;
- case 2:
- puts_filtered ("Special ");
- break;
- case 3:
- puts_filtered ("Empty ");
- break;
+ if ((clear_bv & X86_XSTATE_PKRU))
+ for (i = I387_PKRU_REGNUM (tdep);
+ i < I387_PKEYSEND_REGNUM (tdep); i++)
+ memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
+
+ if ((clear_bv & X86_XSTATE_BNDREGS))
+ for (i = I387_BND0R_REGNUM (tdep);
+ i < I387_BNDCFGU_REGNUM (tdep); i++)
+ memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
+
+ if ((clear_bv & X86_XSTATE_BNDCFG))
+ for (i = I387_BNDCFGU_REGNUM (tdep);
+ i < I387_MPXEND_REGNUM (tdep); i++)
+ memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
+
+ if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
+ for (i = I387_ZMM0H_REGNUM (tdep);
+ i < I387_ZMMENDH_REGNUM (tdep); i++)
+ memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
+
+ if ((clear_bv & X86_XSTATE_K))
+ for (i = I387_K0_REGNUM (tdep);
+ i < I387_KEND_REGNUM (tdep); i++)
+ memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
+
+ if ((clear_bv & X86_XSTATE_ZMM))
+ {
+ for (i = I387_YMM16H_REGNUM (tdep);
+ i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
+ memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
+ for (i = I387_XMM16_REGNUM (tdep);
+ i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
+ memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
+ }
+
+ if ((clear_bv & X86_XSTATE_AVX))
+ for (i = I387_YMM0H_REGNUM (tdep);
+ i < I387_YMMENDH_REGNUM (tdep); i++)
+ memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
+
+ if ((clear_bv & X86_XSTATE_SSE))
+ for (i = I387_XMM0_REGNUM (tdep);
+ i < I387_MXCSR_REGNUM (tdep); i++)
+ memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
+
+ if ((clear_bv & X86_XSTATE_X87))
+ for (i = I387_ST0_REGNUM (tdep);
+ i < I387_FCTRL_REGNUM (tdep); i++)
+ memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
}
- read_register_gen ((fpreg + 8 - top) % 8 + FP0_REGNUM, raw);
+ if (regclass == all)
+ {
+ /* Check if any PKEYS registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_PKRU))
+ for (i = I387_PKRU_REGNUM (tdep);
+ i < I387_PKEYSEND_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_PKEYS_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 4) != 0)
+ {
+ xstate_bv |= X86_XSTATE_PKRU;
+ memcpy (p, raw, 4);
+ }
+ }
+
+ /* Check if any ZMMH registers are changed. */
+ if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
+ for (i = I387_ZMM0H_REGNUM (tdep);
+ i < I387_ZMMENDH_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 32) != 0)
+ {
+ xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
+ memcpy (p, raw, 32);
+ }
+ }
+
+ /* Check if any K registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_K))
+ for (i = I387_K0_REGNUM (tdep);
+ i < I387_KEND_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 8) != 0)
+ {
+ xstate_bv |= X86_XSTATE_K;
+ memcpy (p, raw, 8);
+ }
+ }
- puts_filtered ("0x");
- for (i = 9; i >= 0; i--)
- printf_filtered ("%02x", raw[i]);
+ /* Check if any XMM or upper YMM registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_ZMM))
+ {
+ for (i = I387_YMM16H_REGNUM (tdep);
+ i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 16) != 0)
+ {
+ xstate_bv |= X86_XSTATE_ZMM;
+ memcpy (p, raw, 16);
+ }
+ }
+ for (i = I387_XMM16_REGNUM (tdep);
+ i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 16) != 0)
+ {
+ xstate_bv |= X86_XSTATE_ZMM;
+ memcpy (p, raw, 16);
+ }
+ }
+ }
- if (tag != 3)
- print_i387_ext (raw);
+ /* Check if any upper YMM registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_AVX))
+ for (i = I387_YMM0H_REGNUM (tdep);
+ i < I387_YMMENDH_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_AVXH_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 16))
+ {
+ xstate_bv |= X86_XSTATE_AVX;
+ memcpy (p, raw, 16);
+ }
+ }
+ /* Check if any upper MPX registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
+ for (i = I387_BND0R_REGNUM (tdep);
+ i < I387_BNDCFGU_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_MPX_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 16))
+ {
+ xstate_bv |= X86_XSTATE_BNDREGS;
+ memcpy (p, raw, 16);
+ }
+ }
+
+ /* Check if any upper MPX registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
+ for (i = I387_BNDCFGU_REGNUM (tdep);
+ i < I387_MPXEND_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = XSAVE_MPX_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 8))
+ {
+ xstate_bv |= X86_XSTATE_BNDCFG;
+ memcpy (p, raw, 8);
+ }
+ }
+
+ /* Check if any SSE registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_SSE))
+ for (i = I387_XMM0_REGNUM (tdep);
+ i < I387_MXCSR_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = FXSAVE_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 16))
+ {
+ xstate_bv |= X86_XSTATE_SSE;
+ memcpy (p, raw, 16);
+ }
+ }
+
+ /* Check if any X87 registers are changed. */
+ if ((tdep->xcr0 & X86_XSTATE_X87))
+ for (i = I387_ST0_REGNUM (tdep);
+ i < I387_FCTRL_REGNUM (tdep); i++)
+ {
+ regcache_raw_collect (regcache, i, raw);
+ p = FXSAVE_ADDR (tdep, regs, i);
+ if (memcmp (raw, p, 10))
+ {
+ xstate_bv |= X86_XSTATE_X87;
+ memcpy (p, raw, 10);
+ }
+ }
+ }
+ else
+ {
+ /* Check if REGNUM is changed. */
+ regcache_raw_collect (regcache, regnum, raw);
- puts_filtered ("\n");
+ switch (regclass)
+ {
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("invalid i387 regclass"));
+
+ case pkeys:
+ /* This is a PKEYS register. */
+ p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 4) != 0)
+ {
+ xstate_bv |= X86_XSTATE_PKRU;
+ memcpy (p, raw, 4);
+ }
+ break;
+
+ case avx512_zmm_h:
+ /* This is a ZMM register. */
+ p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 32) != 0)
+ {
+ xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
+ memcpy (p, raw, 32);
+ }
+ break;
+ case avx512_k:
+ /* This is a AVX512 mask register. */
+ p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 8) != 0)
+ {
+ xstate_bv |= X86_XSTATE_K;
+ memcpy (p, raw, 8);
+ }
+ break;
+
+ case avx512_ymmh_avx512:
+ /* This is an upper YMM16-31 register. */
+ p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 16) != 0)
+ {
+ xstate_bv |= X86_XSTATE_ZMM;
+ memcpy (p, raw, 16);
+ }
+ break;
+
+ case avx512_xmm_avx512:
+ /* This is an upper XMM16-31 register. */
+ p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 16) != 0)
+ {
+ xstate_bv |= X86_XSTATE_ZMM;
+ memcpy (p, raw, 16);
+ }
+ break;
+
+ case avxh:
+ /* This is an upper YMM register. */
+ p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 16))
+ {
+ xstate_bv |= X86_XSTATE_AVX;
+ memcpy (p, raw, 16);
+ }
+ break;
+
+ case mpx:
+ if (regnum < I387_BNDCFGU_REGNUM (tdep))
+ {
+ regcache_raw_collect (regcache, regnum, raw);
+ p = XSAVE_MPX_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 16))
+ {
+ xstate_bv |= X86_XSTATE_BNDREGS;
+ memcpy (p, raw, 16);
+ }
+ }
+ else
+ {
+ p = XSAVE_MPX_ADDR (tdep, regs, regnum);
+ xstate_bv |= X86_XSTATE_BNDCFG;
+ memcpy (p, raw, 8);
+ }
+ break;
+
+ case sse:
+ /* This is an SSE register. */
+ p = FXSAVE_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 16))
+ {
+ xstate_bv |= X86_XSTATE_SSE;
+ memcpy (p, raw, 16);
+ }
+ break;
+
+ case x87:
+ /* This is an x87 register. */
+ p = FXSAVE_ADDR (tdep, regs, regnum);
+ if (memcmp (raw, p, 10))
+ {
+ xstate_bv |= X86_XSTATE_X87;
+ memcpy (p, raw, 10);
+ }
+ break;
+ }
+ }
+
+ /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
+ registers are changed. */
+ if (xstate_bv)
+ {
+ /* The supported bits in `xstat_bv' are 8 bytes. */
+ initial_xstate_bv |= xstate_bv;
+ store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
+ 8, byte_order,
+ initial_xstate_bv);
+
+ switch (regclass)
+ {
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("invalid i387 regclass"));
+
+ case all:
+ break;
+
+ case x87:
+ case sse:
+ case avxh:
+ case mpx:
+ case avx512_k:
+ case avx512_zmm_h:
+ case avx512_ymmh_avx512:
+ case avx512_xmm_avx512:
+ case pkeys:
+ /* Register REGNUM has been updated. Return. */
+ return;
+ }
+ }
+ else
+ {
+ /* Return if REGNUM isn't changed. */
+ if (regclass != all)
+ return;
+ }
}
- puts_filtered ("\n");
-
- print_i387_status_word (fstat);
- print_i387_control_word (fctrl);
- printf_filtered ("Tag Word: %s\n",
- local_hex_string_custom (ftag, "04"));
- printf_filtered ("Instruction Pointer: %s:",
- local_hex_string_custom (fiseg, "02"));
- printf_filtered ("%s\n", local_hex_string_custom (fioff, "08"));
- printf_filtered ("Operand Pointer: %s:",
- local_hex_string_custom (foseg, "02"));
- printf_filtered ("%s\n", local_hex_string_custom (fooff, "08"));
- printf_filtered ("Opcode: %s\n",
- local_hex_string_custom (fop ? (fop | 0xd800) : 0, "04"));
+ /* Only handle x87 control registers. */
+ for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
+ if (regnum == -1 || regnum == i)
+ {
+ /* Most of the FPU control registers occupy only 16 bits in
+ the xsave extended state. Give those a special treatment. */
+ if (i != I387_FIOFF_REGNUM (tdep)
+ && i != I387_FOOFF_REGNUM (tdep))
+ {
+ gdb_byte buf[4];
+
+ regcache_raw_collect (regcache, i, buf);
+
+ if (i == I387_FOP_REGNUM (tdep))
+ {
+ /* The opcode occupies only 11 bits. Make sure we
+ don't touch the other bits. */
+ buf[1] &= ((1 << 3) - 1);
+ buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
+ }
+ else if (i == I387_FTAG_REGNUM (tdep))
+ {
+ /* Converting back is much easier. */
+
+ unsigned short ftag;
+ int fpreg;
+
+ ftag = (buf[1] << 8) | buf[0];
+ buf[0] = 0;
+ buf[1] = 0;
+
+ for (fpreg = 7; fpreg >= 0; fpreg--)
+ {
+ int tag = (ftag >> (fpreg * 2)) & 3;
+
+ if (tag != 3)
+ buf[0] |= (1 << fpreg);
+ }
+ }
+ memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
+ }
+ else
+ regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
+ }
+
+ if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
+ regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
+ FXSAVE_MXCSR_ADDR (regs));
+}
+
+/* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
+ *RAW. */
+
+static int
+i387_tag (const gdb_byte *raw)
+{
+ int integer;
+ unsigned int exponent;
+ unsigned long fraction[2];
+
+ integer = raw[7] & 0x80;
+ exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
+ fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
+ fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
+ | (raw[5] << 8) | raw[4]);
+
+ if (exponent == 0x7fff)
+ {
+ /* Special. */
+ return (2);
+ }
+ else if (exponent == 0x0000)
+ {
+ if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
+ {
+ /* Zero. */
+ return (1);
+ }
+ else
+ {
+ /* Special. */
+ return (2);
+ }
+ }
+ else
+ {
+ if (integer)
+ {
+ /* Valid. */
+ return (0);
+ }
+ else
+ {
+ /* Special. */
+ return (2);
+ }
+ }
+}
+
+/* Prepare the FPU stack in REGCACHE for a function return. */
+
+void
+i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ ULONGEST fstat;
+
+ /* Set the top of the floating-point register stack to 7. The
+ actual value doesn't really matter, but 7 is what a normal
+ function return would end up with if the program started out with
+ a freshly initialized FPU. */
+ regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
+ fstat |= (7 << 11);
+ regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
+
+ /* Mark %st(1) through %st(7) as empty. Since we set the top of the
+ floating-point register stack to 7, the appropriate value for the
+ tag word is 0x3fff. */
+ regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
+
+}
+
+/* See i387-tdep.h. */
+
+void
+i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (I387_BND0R_REGNUM (tdep) > 0)
+ {
+ gdb_byte bnd_buf[16];
+
+ memset (bnd_buf, 0, 16);
+ for (int i = 0; i < I387_NUM_BND_REGS; i++)
+ regcache_raw_write (regcache, I387_BND0R_REGNUM (tdep) + i, bnd_buf);
+ }
}