X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Fm88k-tdep.c;h=3c96d37a8dee494b127825e208c315904e37e026;hb=0d62e5e8077eecf77e9b7b5dc0d2689d051a3ab3;hp=afe1ca2d7e188673f8ea598fba89ae6d4dcd1fab;hpb=afd64b4e2d76f981f6828f9f55fcc03784d6915b;p=deliverable%2Fbinutils-gdb.git

diff --git a/gdb/m88k-tdep.c b/gdb/m88k-tdep.c
index afe1ca2d7e..3c96d37a8d 100644
--- a/gdb/m88k-tdep.c
+++ b/gdb/m88k-tdep.c
@@ -1,5 +1,7 @@
 /* Target-machine dependent code for Motorola 88000 series, for GDB.
-   Copyright 1988, 1990, 1991, 1994, 1995 Free Software Foundation, Inc.
+
+   Copyright 1988, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998,
+   2000, 2001, 2002 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -26,6 +28,7 @@
 #include "symtab.h"
 #include "setjmp.h"
 #include "value.h"
+#include "regcache.h"
 
 /* Size of an instruction */
 #define	BYTES_PER_88K_INSN	4
@@ -37,6 +40,45 @@ void frame_find_saved_regs ();
 
 int target_is_m88110 = 0;
 
+void
+m88k_target_write_pc (CORE_ADDR pc, ptid_t ptid)
+{
+  /* According to the MC88100 RISC Microprocessor User's Manual,
+     section 6.4.3.1.2:
+
+     ... can be made to return to a particular instruction by placing
+     a valid instruction address in the SNIP and the next sequential
+     instruction address in the SFIP (with V bits set and E bits
+     clear).  The rte resumes execution at the instruction pointed to
+     by the SNIP, then the SFIP.
+
+     The E bit is the least significant bit (bit 0).  The V (valid)
+     bit is bit 1.  This is why we logical or 2 into the values we are
+     writing below.  It turns out that SXIP plays no role when
+     returning from an exception so nothing special has to be done
+     with it.  We could even (presumably) give it a totally bogus
+     value.
+
+     -- Kevin Buettner */
+
+  write_register_pid (SXIP_REGNUM, pc, ptid);
+  write_register_pid (SNIP_REGNUM, (pc | 2), ptid);
+  write_register_pid (SFIP_REGNUM, (pc | 2) + 4, ptid);
+}
+
+/* The type of a register.  */
+struct type *
+m88k_register_type (int regnum)
+{
+  if (regnum >= XFP_REGNUM)
+    return builtin_type_m88110_ext;
+  else if (regnum == PC_REGNUM || regnum == FP_REGNUM || regnum == SP_REGNUM)
+    return builtin_type_void_func_ptr;
+  else
+    return builtin_type_int32;
+}
+
+
 /* The m88k kernel aligns all instructions on 4-byte boundaries.  The
    kernel also uses the least significant two bits for its own hocus
    pocus.  When gdb receives an address from the kernel, it needs to
@@ -244,7 +286,7 @@ examine_prologue (register CORE_ADDR ip, register CORE_ADDR limit,
 {
   register CORE_ADDR next_ip;
   register int src;
-  unsigned int insn;
+  unsigned long insn;
   int size, offset;
   char must_adjust[32];		/* If set, must adjust offsets in fsr */
   int sp_offset = -1;		/* -1 means not set (valid must be mult of 8) */
@@ -387,7 +429,7 @@ end_of_prologue_found:
   /* (we hope...) */
   if (fsr->regs[SP_REGNUM] != 0
       && fsr->regs[SP_REGNUM] != frame_sp - sp_offset)
-    fprintf_unfiltered (gdb_stderr, "Bad saved SP value %x != %x, offset %x!\n",
+    fprintf_unfiltered (gdb_stderr, "Bad saved SP value %lx != %lx, offset %x!\n",
 			fsr->regs[SP_REGNUM],
 			frame_sp - sp_offset, sp_offset);
 
@@ -566,14 +608,12 @@ void
 pop_frame (void)
 {
   register struct frame_info *frame = get_current_frame ();
-  register CORE_ADDR fp;
   register int regnum;
   struct frame_saved_regs fsr;
 
-  fp = FRAME_FP (frame);
   get_frame_saved_regs (frame, &fsr);
 
-  if (PC_IN_CALL_DUMMY (read_pc (), read_register (SP_REGNUM), FRAME_FP (fi)))
+  if (PC_IN_CALL_DUMMY (read_pc (), read_register (SP_REGNUM), frame->frame))
     {
       /* FIXME: I think get_frame_saved_regs should be handling this so
          that we can deal with the saved registers properly (e.g. frame