X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Fppc-linux-nat.c;h=0b7052d0f6dee1e3686dc64dcc3f51f02620ec7f;hb=e98ee8c458f3a8405eb93e71b00f801b4bbe3635;hp=e49a482c095d1bd54ae29cbbd34d71d3c6614121;hpb=bd64614eb737096f40b976fb505ddd42e7f1614c;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index e49a482c09..0b7052d0f6 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -24,6 +24,7 @@ #include "gdbthread.h" #include "gdbcore.h" #include "regcache.h" +#include "regset.h" #include "target.h" #include "linux-nat.h" #include @@ -160,23 +161,22 @@ struct ppc_hw_breakpoint Even though this vrsave register is not included in the regset typedef, it is handled by the ptrace requests. - Note that GNU/Linux doesn't support little endian PPC hardware, - therefore the offset at which the real value of the VSCR register - is located will be always 12 bytes. - The layout is like this (where x is the actual value of the vscr reg): */ /* *INDENT-OFF* */ /* +Big-Endian: |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| <-------> <-------><-------><-> VR0 VR31 VSCR VRSAVE +Little-Endian: + |.|.|.|.|.....|.|.|.|.||X|.|.|.||.| + <-------> <-------><-------><-> + VR0 VR31 VSCR VRSAVE */ /* *INDENT-ON* */ -#define SIZEOF_VRREGS 33*16+4 - -typedef char gdb_vrregset_t[SIZEOF_VRREGS]; +typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET]; /* This is the layout of the POWER7 VSX registers and the way they overlap with the existing FPR and VMX registers. @@ -210,9 +210,7 @@ typedef char gdb_vrregset_t[SIZEOF_VRREGS]; the FP registers (doubleword 0) and hence extend them with additional 64 bits (doubleword 1). The other 32 regs overlap with the VMX registers. */ -#define SIZEOF_VSXREGS 32*8 - -typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; +typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET]; /* On PPC processors that support the Signal Processing Extension (SPE) APU, the general-purpose registers are 64 bits long. @@ -411,13 +409,11 @@ ppc_register_u_addr (struct gdbarch *gdbarch, int regno) registers set mechanism, as opposed to the interface for all the other registers, that stores/fetches each register individually. */ static void -fetch_vsx_register (struct regcache *regcache, int tid, int regno) +fetch_vsx_registers (struct regcache *regcache, int tid, int regno) { int ret; gdb_vsxregset_t regs; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + const struct regset *vsxregset = ppc_linux_vsxregset (); ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); if (ret < 0) @@ -427,26 +423,24 @@ fetch_vsx_register (struct regcache *regcache, int tid, int regno) have_ptrace_getsetvsxregs = 0; return; } - perror_with_name (_("Unable to fetch VSX register")); + perror_with_name (_("Unable to fetch VSX registers")); } - regcache_raw_supply (regcache, regno, - regs + (regno - tdep->ppc_vsr0_upper_regnum) - * vsxregsize); + vsxregset->supply_regset (vsxregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VSXREGSET); } /* The Linux kernel ptrace interface for AltiVec registers uses the registers set mechanism, as opposed to the interface for all the other registers, that stores/fetches each register individually. */ static void -fetch_altivec_register (struct regcache *regcache, int tid, int regno) +fetch_altivec_registers (struct regcache *regcache, int tid, + int regno) { int ret; - int offset = 0; gdb_vrregset_t regs; struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + const struct regset *vrregset = ppc_linux_vrregset (gdbarch); ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); if (ret < 0) @@ -456,19 +450,11 @@ fetch_altivec_register (struct regcache *regcache, int tid, int regno) have_ptrace_getvrregs = 0; return; } - perror_with_name (_("Unable to fetch AltiVec register")); + perror_with_name (_("Unable to fetch AltiVec registers")); } - - /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes - long on the hardware. We deal only with the lower 4 bytes of the - vector. VRSAVE is at the end of the array in a 4 bytes slot, so - there is no need to define an offset for it. */ - if (regno == (tdep->ppc_vrsave_regnum - 1)) - offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - regcache_raw_supply (regcache, regno, - regs + (regno - - tdep->ppc_vr0_regnum) * vrregsize + offset); + + vrregset->supply_regset (vrregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VRREGSET); } /* Fetch the top 32 bits of TID's general-purpose registers and the @@ -526,33 +512,29 @@ fetch_spe_register (struct regcache *regcache, int tid, int regno) int i; for (i = 0; i < ppc_num_gprs; i++) - regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, - &evrregs.evr[i]); + regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]); } else if (tdep->ppc_ev0_upper_regnum <= regno && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) - regcache_raw_supply (regcache, regno, - &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); + regcache->raw_supply (regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); if (regno == -1 || regno == tdep->ppc_acc_regnum) - regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); + regcache->raw_supply (tdep->ppc_acc_regnum, &evrregs.acc); if (regno == -1 || regno == tdep->ppc_spefscr_regnum) - regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, - &evrregs.spefscr); + regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr); } static void fetch_register (struct regcache *regcache, int tid, int regno) { struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); /* This isn't really an address. But ptrace thinks of it as one. */ CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); int bytes_transferred; - unsigned int offset; /* Offset of registers within the u area. */ gdb_byte buf[PPC_MAX_REGISTER_SIZE]; if (altivec_register_p (gdbarch, regno)) @@ -563,7 +545,7 @@ fetch_register (struct regcache *regcache, int tid, int regno) register. */ if (have_ptrace_getvrregs) { - fetch_altivec_register (regcache, tid, regno); + fetch_altivec_registers (regcache, tid, regno); return; } /* If we have discovered that there is no ptrace support for @@ -574,7 +556,7 @@ fetch_register (struct regcache *regcache, int tid, int regno) { if (have_ptrace_getsetvsxregs) { - fetch_vsx_register (regcache, tid, regno); + fetch_vsx_registers (regcache, tid, regno); return; } } @@ -587,7 +569,7 @@ fetch_register (struct regcache *regcache, int tid, int regno) if (regaddr == -1) { memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ - regcache_raw_supply (regcache, regno, buf); + regcache->raw_supply (regno, buf); return; } @@ -620,14 +602,14 @@ fetch_register (struct regcache *regcache, int tid, int regno) { /* Little-endian values are always found at the left end of the bytes transferred. */ - regcache_raw_supply (regcache, regno, buf); + regcache->raw_supply (regno, buf); } else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) { /* Big-endian values are found at the right end of the bytes transferred. */ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); - regcache_raw_supply (regcache, regno, buf + padding); + regcache->raw_supply (regno, buf + padding); } else internal_error (__FILE__, __LINE__, @@ -635,84 +617,6 @@ fetch_register (struct regcache *regcache, int tid, int regno) gdbarch_byte_order (gdbarch)); } -static void -supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); - - for (i = 0; i < ppc_num_vshrs; i++) - { - regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, - *vsxregsetp + i * vsxregsize); - } -} - -static void -supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); - int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - for (i = 0; i < num_of_vrregs; i++) - { - /* The last 2 registers of this set are only 32 bit long, not - 128. However an offset is necessary only for VSCR because it - occupies a whole vector, while VRSAVE occupies a full 4 bytes - slot. */ - if (i == (num_of_vrregs - 2)) - regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize + offset); - else - regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize); - } -} - -static void -fetch_vsx_registers (struct regcache *regcache, int tid) -{ - int ret; - gdb_vsxregset_t regs; - - ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getsetvsxregs = 0; - return; - } - perror_with_name (_("Unable to fetch VSX registers")); - } - supply_vsxregset (regcache, ®s); -} - -static void -fetch_altivec_registers (struct regcache *regcache, int tid) -{ - int ret; - gdb_vrregset_t regs; - - ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getvrregs = 0; - return; - } - perror_with_name (_("Unable to fetch AltiVec registers")); - } - supply_vrregset (regcache, ®s); -} - /* This function actually issues the request to ptrace, telling it to get all general-purpose registers and put them into the specified regset. @@ -724,8 +628,6 @@ fetch_altivec_registers (struct regcache *regcache, int tid) static int fetch_all_gp_regs (struct regcache *regcache, int tid) { - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); gdb_gregset_t gregset; if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) @@ -822,7 +724,6 @@ fetch_fp_regs (struct regcache *regcache, int tid) static void fetch_ppc_registers (struct regcache *regcache, int tid) { - int i; struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -851,10 +752,10 @@ fetch_ppc_registers (struct regcache *regcache, int tid) fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) - fetch_altivec_registers (regcache, tid); + fetch_altivec_registers (regcache, tid, -1); if (have_ptrace_getsetvsxregs) if (tdep->ppc_vsr0_upper_regnum != -1) - fetch_vsx_registers (regcache, tid); + fetch_vsx_registers (regcache, tid, -1); if (tdep->ppc_ev0_upper_regnum >= 0) fetch_spe_register (regcache, tid, -1); } @@ -865,7 +766,7 @@ fetch_ppc_registers (struct regcache *regcache, int tid) void ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) { - pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache)); + pid_t tid = get_ptrace_pid (regcache->ptid ()); if (regno == -1) fetch_ppc_registers (regcache, tid); @@ -873,15 +774,12 @@ ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) fetch_register (regcache, tid, regno); } -/* Store one VSX register. */ static void -store_vsx_register (const struct regcache *regcache, int tid, int regno) +store_vsx_registers (const struct regcache *regcache, int tid, int regno) { int ret; gdb_vsxregset_t regs; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + const struct regset *vsxregset = ppc_linux_vsxregset (); ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); if (ret < 0) @@ -891,27 +789,25 @@ store_vsx_register (const struct regcache *regcache, int tid, int regno) have_ptrace_getsetvsxregs = 0; return; } - perror_with_name (_("Unable to fetch VSX register")); + perror_with_name (_("Unable to fetch VSX registers")); } - regcache_raw_collect (regcache, regno, regs + - (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); + vsxregset->collect_regset (vsxregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VSXREGSET); ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); if (ret < 0) - perror_with_name (_("Unable to store VSX register")); + perror_with_name (_("Unable to store VSX registers")); } -/* Store one register. */ static void -store_altivec_register (const struct regcache *regcache, int tid, int regno) +store_altivec_registers (const struct regcache *regcache, int tid, + int regno) { int ret; - int offset = 0; gdb_vrregset_t regs; struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + const struct regset *vrregset = ppc_linux_vrregset (gdbarch); ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); if (ret < 0) @@ -921,21 +817,15 @@ store_altivec_register (const struct regcache *regcache, int tid, int regno) have_ptrace_getvrregs = 0; return; } - perror_with_name (_("Unable to fetch AltiVec register")); + perror_with_name (_("Unable to fetch AltiVec registers")); } - /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes - long on the hardware. */ - if (regno == (tdep->ppc_vrsave_regnum - 1)) - offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - regcache_raw_collect (regcache, regno, - regs + (regno - - tdep->ppc_vr0_regnum) * vrregsize + offset); + vrregset->collect_regset (vrregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VRREGSET); ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); if (ret < 0) - perror_with_name (_("Unable to store AltiVec register")); + perror_with_name (_("Unable to store AltiVec registers")); } /* Assuming TID referrs to an SPE process, set the top halves of TID's @@ -1000,26 +890,23 @@ store_spe_register (const struct regcache *regcache, int tid, int regno) int i; for (i = 0; i < ppc_num_gprs; i++) - regcache_raw_collect (regcache, - tdep->ppc_ev0_upper_regnum + i, - &evrregs.evr[i]); + regcache->raw_collect (tdep->ppc_ev0_upper_regnum + i, + &evrregs.evr[i]); } else if (tdep->ppc_ev0_upper_regnum <= regno && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) - regcache_raw_collect (regcache, regno, - &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); + regcache->raw_collect (regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); if (regno == -1 || regno == tdep->ppc_acc_regnum) - regcache_raw_collect (regcache, - tdep->ppc_acc_regnum, - &evrregs.acc); + regcache->raw_collect (tdep->ppc_acc_regnum, + &evrregs.acc); if (regno == -1 || regno == tdep->ppc_spefscr_regnum) - regcache_raw_collect (regcache, - tdep->ppc_spefscr_regnum, - &evrregs.spefscr); + regcache->raw_collect (tdep->ppc_spefscr_regnum, + &evrregs.spefscr); /* Write back the modified register set. */ set_spe_registers (tid, &evrregs); @@ -1038,12 +925,12 @@ store_register (const struct regcache *regcache, int tid, int regno) if (altivec_register_p (gdbarch, regno)) { - store_altivec_register (regcache, tid, regno); + store_altivec_registers (regcache, tid, regno); return; } if (vsx_register_p (gdbarch, regno)) { - store_vsx_register (regcache, tid, regno); + store_vsx_registers (regcache, tid, regno); return; } else if (spe_register_p (gdbarch, regno)) @@ -1063,13 +950,13 @@ store_register (const struct regcache *regcache, int tid, int regno) if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) { /* Little-endian values always sit at the left end of the buffer. */ - regcache_raw_collect (regcache, regno, buf); + regcache->raw_collect (regno, buf); } else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) { /* Big-endian values sit at the right end of the buffer. */ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); - regcache_raw_collect (regcache, regno, buf + padding); + regcache->raw_collect (regno, buf + padding); } for (i = 0; i < bytes_to_transfer; i += sizeof (long)) @@ -1101,88 +988,6 @@ store_register (const struct regcache *regcache, int tid, int regno) } } -static void -fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); - - for (i = 0; i < ppc_num_vshrs; i++) - regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, - *vsxregsetp + i * vsxregsize); -} - -static void -fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); - int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - for (i = 0; i < num_of_vrregs; i++) - { - /* The last 2 registers of this set are only 32 bit long, not - 128, but only VSCR is fetched as a 16 bytes quantity. */ - if (i == (num_of_vrregs - 2)) - regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize + offset); - else - regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize); - } -} - -static void -store_vsx_registers (const struct regcache *regcache, int tid) -{ - int ret; - gdb_vsxregset_t regs; - - ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getsetvsxregs = 0; - return; - } - perror_with_name (_("Couldn't get VSX registers")); - } - - fill_vsxregset (regcache, ®s); - - if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) - perror_with_name (_("Couldn't write VSX registers")); -} - -static void -store_altivec_registers (const struct regcache *regcache, int tid) -{ - int ret; - gdb_vrregset_t regs; - - ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getvrregs = 0; - return; - } - perror_with_name (_("Couldn't get AltiVec registers")); - } - - fill_vrregset (regcache, ®s); - - if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) - perror_with_name (_("Couldn't write AltiVec registers")); -} - /* This function actually issues the request to ptrace, telling it to store all general-purpose registers present in the specified regset. @@ -1194,8 +999,6 @@ store_altivec_registers (const struct regcache *regcache, int tid) static int store_all_gp_regs (const struct regcache *regcache, int tid, int regno) { - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); gdb_gregset_t gregset; if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) @@ -1312,7 +1115,6 @@ store_fp_regs (const struct regcache *regcache, int tid, int regno) static void store_ppc_registers (const struct regcache *regcache, int tid) { - int i; struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -1341,24 +1143,24 @@ store_ppc_registers (const struct regcache *regcache, int tid) } if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) - store_altivec_registers (regcache, tid); + store_altivec_registers (regcache, tid, -1); if (have_ptrace_getsetvsxregs) if (tdep->ppc_vsr0_upper_regnum != -1) - store_vsx_registers (regcache, tid); + store_vsx_registers (regcache, tid, -1); if (tdep->ppc_ev0_upper_regnum >= 0) store_spe_register (regcache, tid, -1); } /* Fetch the AT_HWCAP entry from the aux vector. */ -static unsigned long +static CORE_ADDR ppc_linux_get_hwcap (void) { CORE_ADDR field; - if (target_auxv_search (target_stack, AT_HWCAP, &field)) - return (unsigned long) field; + if (target_auxv_search (current_top_target (), AT_HWCAP, &field) != 1) + return 0; - return 0; + return field; } /* The cached DABR value, to install in new threads. @@ -1414,9 +1216,9 @@ have_ptrace_hwdebug_interface (void) { int tid; - tid = ptid_get_lwp (inferior_ptid); + tid = inferior_ptid.lwp (); if (tid == 0) - tid = ptid_get_pid (inferior_ptid); + tid = inferior_ptid.pid (); /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) @@ -1486,9 +1288,9 @@ ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot) /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether the target has DABR. If either answer is no, the ptrace call will return -1. Fail in that case. */ - tid = ptid_get_lwp (ptid); + tid = ptid.lwp (); if (tid == 0) - tid = ptid_get_pid (ptid); + tid = ptid.pid (); if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) return 0; @@ -1597,7 +1399,6 @@ hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) gdb::unique_xmalloc_ptr p (XDUP (ppc_hw_breakpoint, b)); struct hw_break_tuple *hw_breaks; struct thread_points *t; - struct hw_break_tuple *tuple; errno = 0; slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ()); @@ -1698,7 +1499,7 @@ ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, } ALL_LWPS (lp) - hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_insert_point (&p, lp->ptid.lwp ()); return 0; } @@ -1734,7 +1535,7 @@ ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, } ALL_LWPS (lp) - hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_remove_point (&p, lp->ptid.lwp ()); return 0; } @@ -1777,7 +1578,7 @@ ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, p.condition_value = 0; ALL_LWPS (lp) - hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_insert_point (&p, lp->ptid.lwp ()); return 0; } @@ -1805,7 +1606,7 @@ ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, p.condition_value = 0; ALL_LWPS (lp) - hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_remove_point (&p, lp->ptid.lwp ()); return 0; } @@ -1815,9 +1616,8 @@ static int can_use_watchpoint_cond_accel (void) { struct thread_points *p; - int tid = ptid_get_lwp (inferior_ptid); + int tid = inferior_ptid.lwp (); int cnt = hwdebug_info.num_condition_regs, i; - CORE_ADDR tmp_value; if (!have_ptrace_hwdebug_interface () || cnt == 0) return 0; @@ -2069,7 +1869,7 @@ ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, create_watchpoint_request (&p, addr, len, type, cond, 1); ALL_LWPS (lp) - hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_insert_point (&p, lp->ptid.lwp ()); ret = 0; } @@ -2113,7 +1913,7 @@ ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, saved_dabr_value = dabr_value; ALL_LWPS (lp) - if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, + if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, saved_dabr_value) < 0) return -1; @@ -2138,7 +1938,7 @@ ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, create_watchpoint_request (&p, addr, len, type, cond, 0); ALL_LWPS (lp) - hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_remove_point (&p, lp->ptid.lwp ()); ret = 0; } @@ -2146,7 +1946,7 @@ ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, { saved_dabr_value = 0; ALL_LWPS (lp) - if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, + if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, saved_dabr_value) < 0) return -1; @@ -2159,7 +1959,7 @@ ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, void ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) { - int tid = ptid_get_lwp (lp->ptid); + int tid = lp->ptid.lwp (); if (have_ptrace_hwdebug_interface ()) { @@ -2198,7 +1998,7 @@ static void ppc_linux_thread_exit (struct thread_info *tp, int silent) { int i; - int tid = ptid_get_lwp (tp->ptid); + int tid = tp->ptid.lwp (); struct hw_break_tuple *hw_breaks; struct thread_points *t = NULL, *p; @@ -2247,7 +2047,7 @@ ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) /* The index (or slot) of the *point is passed in the si_errno field. */ int slot = siginfo.si_errno; - t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0); + t = hwdebug_find_thread_points_by_tid (inferior_ptid.lwp (), 0); /* Find out if this *point is a hardware breakpoint. If so, we should return 0. */ @@ -2316,7 +2116,7 @@ ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask void ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) { - pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache)); + pid_t tid = get_ptrace_pid (regcache->ptid ()); if (regno >= 0) store_register (regcache, tid, regno); @@ -2368,35 +2168,17 @@ fill_fpregset (const struct regcache *regcache, fpregsetp, sizeof (*fpregsetp)); } -static int -ppc_linux_target_wordsize (void) -{ - int wordsize = 4; - - /* Check for 64-bit inferior process. This is the case when the host is - 64-bit, and in addition the top bit of the MSR register is set. */ -#ifdef __powerpc64__ - long msr; - - int tid = ptid_get_lwp (inferior_ptid); - if (tid == 0) - tid = ptid_get_pid (inferior_ptid); - - errno = 0; - msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); - if (errno == 0 && ppc64_64bit_inferior_p (msr)) - wordsize = 8; -#endif - - return wordsize; -} - int ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) { - int sizeof_auxv_field = ppc_linux_target_wordsize (); + int tid = inferior_ptid.lwp (); + if (tid == 0) + tid = inferior_ptid.pid (); + + int sizeof_auxv_field = ppc_linux_target_wordsize (tid); + enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); gdb_byte *ptr = *readptr; @@ -2418,9 +2200,9 @@ ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, const struct target_desc * ppc_linux_nat_target::read_description () { - int tid = ptid_get_lwp (inferior_ptid); + int tid = inferior_ptid.lwp (); if (tid == 0) - tid = ptid_get_pid (inferior_ptid); + tid = inferior_ptid.pid (); if (have_ptrace_getsetevrregs) { @@ -2437,9 +2219,9 @@ ppc_linux_nat_target::read_description () struct ppc_linux_features features = ppc_linux_no_features; - features.wordsize = ppc_linux_target_wordsize (); + features.wordsize = ppc_linux_target_wordsize (tid); - unsigned long hwcap = ppc_linux_get_hwcap (); + CORE_ADDR hwcap = ppc_linux_get_hwcap (); if (have_ptrace_getsetvsxregs && (hwcap & PPC_FEATURE_HAS_VSX))