X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Fppc-linux-nat.c;h=10ff73dc7631ed1744d3c74a4ff93f5731e1d48e;hb=4fcd97eb159fbfdf2b6576762821900345f510b3;hp=66e6e831a77001783cbed6f31318723f4716297f;hpb=4e052eda914ce3a3c48b31a0d13bce89c364495e;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index 66e6e831a7..10ff73dc76 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -1,12 +1,13 @@ -/* PPC linux native support. - Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2001 Free Software - Foundation, Inc. +/* PPC GNU/Linux native support. + + Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003, + 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. This file is part of GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or + the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, @@ -15,114 +16,1646 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + along with this program. If not, see . */ #include "defs.h" +#include "gdb_string.h" #include "frame.h" #include "inferior.h" #include "gdbcore.h" #include "regcache.h" +#include "gdb_assert.h" +#include "target.h" +#include "linux-nat.h" +#include #include #include #include #include #include -#include +#include "gdb_wait.h" #include #include +#include /* Prototypes for supply_gregset etc. */ #include "gregset.h" +#include "ppc-tdep.h" +#include "ppc-linux-tdep.h" + +/* Required when using the AUXV. */ +#include "elf/common.h" +#include "auxv.h" + +/* This sometimes isn't defined. */ +#ifndef PT_ORIG_R3 +#define PT_ORIG_R3 34 +#endif +#ifndef PT_TRAP +#define PT_TRAP 40 +#endif + +/* The PPC_FEATURE_* defines should be provided by . + If they aren't, we can provide them ourselves (their values are fixed + because they are part of the kernel ABI). They are used in the AT_HWCAP + entry of the AUXV. */ +#ifndef PPC_FEATURE_CELL +#define PPC_FEATURE_CELL 0x00010000 +#endif +#ifndef PPC_FEATURE_BOOKE +#define PPC_FEATURE_BOOKE 0x00008000 +#endif +#ifndef PPC_FEATURE_HAS_DFP +#define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */ +#endif + +/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a + configure time check. Some older glibc's (for instance 2.2.1) + don't have a specific powerpc version of ptrace.h, and fall back on + a generic one. In such cases, sys/ptrace.h defines + PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that + ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and + PTRACE_SETVRREGS to be. This also makes a configury check pretty + much useless. */ + +/* These definitions should really come from the glibc header files, + but Glibc doesn't know about the vrregs yet. */ +#ifndef PTRACE_GETVRREGS +#define PTRACE_GETVRREGS 18 +#define PTRACE_SETVRREGS 19 +#endif + +/* PTRACE requests for POWER7 VSX registers. */ +#ifndef PTRACE_GETVSXREGS +#define PTRACE_GETVSXREGS 27 +#define PTRACE_SETVSXREGS 28 +#endif + +/* Similarly for the ptrace requests for getting / setting the SPE + registers (ev0 -- ev31, acc, and spefscr). See the description of + gdb_evrregset_t for details. */ +#ifndef PTRACE_GETEVRREGS +#define PTRACE_GETEVRREGS 20 +#define PTRACE_SETEVRREGS 21 +#endif + +/* Similarly for the hardware watchpoint support. */ +#ifndef PTRACE_GET_DEBUGREG +#define PTRACE_GET_DEBUGREG 25 +#endif +#ifndef PTRACE_SET_DEBUGREG +#define PTRACE_SET_DEBUGREG 26 +#endif +#ifndef PTRACE_GETSIGINFO +#define PTRACE_GETSIGINFO 0x4202 +#endif + +/* Similarly for the general-purpose (gp0 -- gp31) + and floating-point registers (fp0 -- fp31). */ +#ifndef PTRACE_GETREGS +#define PTRACE_GETREGS 12 +#endif +#ifndef PTRACE_SETREGS +#define PTRACE_SETREGS 13 +#endif +#ifndef PTRACE_GETFPREGS +#define PTRACE_GETFPREGS 14 +#endif +#ifndef PTRACE_SETFPREGS +#define PTRACE_SETFPREGS 15 +#endif + +/* This oddity is because the Linux kernel defines elf_vrregset_t as + an array of 33 16 bytes long elements. I.e. it leaves out vrsave. + However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return + the vrsave as an extra 4 bytes at the end. I opted for creating a + flat array of chars, so that it is easier to manipulate for gdb. + + There are 32 vector registers 16 bytes longs, plus a VSCR register + which is only 4 bytes long, but is fetched as a 16 bytes + quantity. Up to here we have the elf_vrregset_t structure. + Appended to this there is space for the VRSAVE register: 4 bytes. + Even though this vrsave register is not included in the regset + typedef, it is handled by the ptrace requests. + + Note that GNU/Linux doesn't support little endian PPC hardware, + therefore the offset at which the real value of the VSCR register + is located will be always 12 bytes. -int -kernel_u_size (void) + The layout is like this (where x is the actual value of the vscr reg): */ + +/* *INDENT-OFF* */ +/* + |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| + <-------> <-------><-------><-> + VR0 VR31 VSCR VRSAVE +*/ +/* *INDENT-ON* */ + +#define SIZEOF_VRREGS 33*16+4 + +typedef char gdb_vrregset_t[SIZEOF_VRREGS]; + +/* This is the layout of the POWER7 VSX registers and the way they overlap + with the existing FPR and VMX registers. + + VSR doubleword 0 VSR doubleword 1 + ---------------------------------------------------------------- + VSR[0] | FPR[0] | | + ---------------------------------------------------------------- + VSR[1] | FPR[1] | | + ---------------------------------------------------------------- + | ... | | + | ... | | + ---------------------------------------------------------------- + VSR[30] | FPR[30] | | + ---------------------------------------------------------------- + VSR[31] | FPR[31] | | + ---------------------------------------------------------------- + VSR[32] | VR[0] | + ---------------------------------------------------------------- + VSR[33] | VR[1] | + ---------------------------------------------------------------- + | ... | + | ... | + ---------------------------------------------------------------- + VSR[62] | VR[30] | + ---------------------------------------------------------------- + VSR[63] | VR[31] | + ---------------------------------------------------------------- + + VSX has 64 128bit registers. The first 32 registers overlap with + the FP registers (doubleword 0) and hence extend them with additional + 64 bits (doubleword 1). The other 32 regs overlap with the VMX + registers. */ +#define SIZEOF_VSXREGS 32*8 + +typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; + +/* On PPC processors that support the the Signal Processing Extension + (SPE) APU, the general-purpose registers are 64 bits long. + However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER + ptrace calls only access the lower half of each register, to allow + them to behave the same way they do on non-SPE systems. There's a + separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that + read and write the top halves of all the general-purpose registers + at once, along with some SPE-specific registers. + + GDB itself continues to claim the general-purpose registers are 32 + bits long. It has unnamed raw registers that hold the upper halves + of the gprs, and the the full 64-bit SIMD views of the registers, + 'ev0' -- 'ev31', are pseudo-registers that splice the top and + bottom halves together. + + This is the structure filled in by PTRACE_GETEVRREGS and written to + the inferior's registers by PTRACE_SETEVRREGS. */ +struct gdb_evrregset_t { - return (sizeof (struct user)); + unsigned long evr[32]; + unsigned long long acc; + unsigned long spefscr; +}; + +/* Non-zero if our kernel may support the PTRACE_GETVSXREGS and + PTRACE_SETVSXREGS requests, for reading and writing the VSX + POWER7 registers 0 through 31. Zero if we've tried one of them and + gotten an error. Note that VSX registers 32 through 63 overlap + with VR registers 0 through 31. */ +int have_ptrace_getsetvsxregs = 1; + +/* Non-zero if our kernel may support the PTRACE_GETVRREGS and + PTRACE_SETVRREGS requests, for reading and writing the Altivec + registers. Zero if we've tried one of them and gotten an + error. */ +int have_ptrace_getvrregs = 1; + +/* Non-zero if our kernel may support the PTRACE_GETEVRREGS and + PTRACE_SETEVRREGS requests, for reading and writing the SPE + registers. Zero if we've tried one of them and gotten an + error. */ +int have_ptrace_getsetevrregs = 1; + +/* Non-zero if our kernel may support the PTRACE_GETREGS and + PTRACE_SETREGS requests, for reading and writing the + general-purpose registers. Zero if we've tried one of + them and gotten an error. */ +int have_ptrace_getsetregs = 1; + +/* Non-zero if our kernel may support the PTRACE_GETFPREGS and + PTRACE_SETFPREGS requests, for reading and writing the + floating-pointers registers. Zero if we've tried one of + them and gotten an error. */ +int have_ptrace_getsetfpregs = 1; + +/* *INDENT-OFF* */ +/* registers layout, as presented by the ptrace interface: +PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, +PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, +PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, +PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, +PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, +PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, +PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, +PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, +PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ +/* *INDENT_ON * */ + +static int +ppc_register_u_addr (struct gdbarch *gdbarch, int regno) +{ + int u_addr = -1; + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace + interface, and not the wordsize of the program's ABI. */ + int wordsize = sizeof (long); + + /* General purpose registers occupy 1 slot each in the buffer */ + if (regno >= tdep->ppc_gp0_regnum + && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) + u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); + + /* Floating point regs: eight bytes each in both 32- and 64-bit + ptrace interfaces. Thus, two slots each in 32-bit interface, one + slot each in 64-bit interface. */ + if (tdep->ppc_fp0_regnum >= 0 + && regno >= tdep->ppc_fp0_regnum + && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) + u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); + + /* UISA special purpose registers: 1 slot each */ + if (regno == gdbarch_pc_regnum (gdbarch)) + u_addr = PT_NIP * wordsize; + if (regno == tdep->ppc_lr_regnum) + u_addr = PT_LNK * wordsize; + if (regno == tdep->ppc_cr_regnum) + u_addr = PT_CCR * wordsize; + if (regno == tdep->ppc_xer_regnum) + u_addr = PT_XER * wordsize; + if (regno == tdep->ppc_ctr_regnum) + u_addr = PT_CTR * wordsize; +#ifdef PT_MQ + if (regno == tdep->ppc_mq_regnum) + u_addr = PT_MQ * wordsize; +#endif + if (regno == tdep->ppc_ps_regnum) + u_addr = PT_MSR * wordsize; + if (regno == PPC_ORIG_R3_REGNUM) + u_addr = PT_ORIG_R3 * wordsize; + if (regno == PPC_TRAP_REGNUM) + u_addr = PT_TRAP * wordsize; + if (tdep->ppc_fpscr_regnum >= 0 + && regno == tdep->ppc_fpscr_regnum) + { + /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the + kernel headers incorrectly contained the 32-bit definition of + PT_FPSCR. For the 32-bit definition, floating-point + registers occupy two 32-bit "slots", and the FPSCR lives in + the second half of such a slot-pair (hence +1). For 64-bit, + the FPSCR instead occupies the full 64-bit 2-word-slot and + hence no adjustment is necessary. Hack around this. */ + if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) + u_addr = (48 + 32) * wordsize; + /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit + slot and not just its second word. The PT_FPSCR supplied when + GDB is compiled as a 32-bit app doesn't reflect this. */ + else if (wordsize == 4 && register_size (gdbarch, regno) == 8 + && PT_FPSCR == (48 + 2*32 + 1)) + u_addr = (48 + 2*32) * wordsize; + else + u_addr = PT_FPSCR * wordsize; + } + return u_addr; } -static int regmap[] = -{PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, - PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, - PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, - PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, - PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, - PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, - PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, - PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, - PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ}; +/* The Linux kernel ptrace interface for POWER7 VSX registers uses the + registers set mechanism, as opposed to the interface for all the + other registers, that stores/fetches each register individually. */ +static void +fetch_vsx_register (struct regcache *regcache, int tid, int regno) +{ + int ret; + gdb_vsxregset_t regs; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + + ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Unable to fetch VSX register")); + } + + regcache_raw_supply (regcache, regno, + regs + (regno - tdep->ppc_vsr0_upper_regnum) + * vsxregsize); +} -int -ppc_register_u_addr (int ustart, int regnum) +/* The Linux kernel ptrace interface for AltiVec registers uses the + registers set mechanism, as opposed to the interface for all the + other registers, that stores/fetches each register individually. */ +static void +fetch_altivec_register (struct regcache *regcache, int tid, int regno) { - return (ustart + 4 * regmap[regnum]); + int ret; + int offset = 0; + gdb_vrregset_t regs; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + + ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getvrregs = 0; + return; + } + perror_with_name (_("Unable to fetch AltiVec register")); + } + + /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes + long on the hardware. We deal only with the lower 4 bytes of the + vector. VRSAVE is at the end of the array in a 4 bytes slot, so + there is no need to define an offset for it. */ + if (regno == (tdep->ppc_vrsave_regnum - 1)) + offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); + + regcache_raw_supply (regcache, regno, + regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); } -void -supply_gregset (gdb_gregset_t *gregsetp) +/* Fetch the top 32 bits of TID's general-purpose registers and the + SPE-specific registers, and place the results in EVRREGSET. If we + don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with + zeros. + + All the logic to deal with whether or not the PTRACE_GETEVRREGS and + PTRACE_SETEVRREGS requests are supported is isolated here, and in + set_spe_registers. */ +static void +get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) +{ + if (have_ptrace_getsetevrregs) + { + if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) + return; + else + { + /* EIO means that the PTRACE_GETEVRREGS request isn't supported; + we just return zeros. */ + if (errno == EIO) + have_ptrace_getsetevrregs = 0; + else + /* Anything else needs to be reported. */ + perror_with_name (_("Unable to fetch SPE registers")); + } + } + + memset (evrregset, 0, sizeof (*evrregset)); +} + +/* Supply values from TID for SPE-specific raw registers: the upper + halves of the GPRs, the accumulator, and the spefscr. REGNO must + be the number of an upper half register, acc, spefscr, or -1 to + supply the values of all registers. */ +static void +fetch_spe_register (struct regcache *regcache, int tid, int regno) { - int regi; - register greg_t *regp = (greg_t *) gregsetp; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + struct gdb_evrregset_t evrregs; + + gdb_assert (sizeof (evrregs.evr[0]) + == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); + gdb_assert (sizeof (evrregs.acc) + == register_size (gdbarch, tdep->ppc_acc_regnum)); + gdb_assert (sizeof (evrregs.spefscr) + == register_size (gdbarch, tdep->ppc_spefscr_regnum)); + + get_spe_registers (tid, &evrregs); + + if (regno == -1) + { + int i; + + for (i = 0; i < ppc_num_gprs; i++) + regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, + &evrregs.evr[i]); + } + else if (tdep->ppc_ev0_upper_regnum <= regno + && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) + regcache_raw_supply (regcache, regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); - for (regi = 0; regi < 32; regi++) - supply_register (regi, (char *) (regp + regi)); + if (regno == -1 + || regno == tdep->ppc_acc_regnum) + regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); - for (regi = FIRST_UISA_SP_REGNUM; regi <= LAST_UISA_SP_REGNUM; regi++) - supply_register (regi, (char *) (regp + regmap[regi])); + if (regno == -1 + || regno == tdep->ppc_spefscr_regnum) + regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, + &evrregs.spefscr); } -void -fill_gregset (gdb_gregset_t *gregsetp, int regno) +static void +fetch_register (struct regcache *regcache, int tid, int regno) { - int regi; - greg_t *regp = (greg_t *) gregsetp; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + /* This isn't really an address. But ptrace thinks of it as one. */ + CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); + int bytes_transferred; + unsigned int offset; /* Offset of registers within the u area. */ + char buf[MAX_REGISTER_SIZE]; + + if (altivec_register_p (gdbarch, regno)) + { + /* If this is the first time through, or if it is not the first + time through, and we have comfirmed that there is kernel + support for such a ptrace request, then go and fetch the + register. */ + if (have_ptrace_getvrregs) + { + fetch_altivec_register (regcache, tid, regno); + return; + } + /* If we have discovered that there is no ptrace support for + AltiVec registers, fall through and return zeroes, because + regaddr will be -1 in this case. */ + } + if (vsx_register_p (gdbarch, regno)) + { + if (have_ptrace_getsetvsxregs) + { + fetch_vsx_register (regcache, tid, regno); + return; + } + } + else if (spe_register_p (gdbarch, regno)) + { + fetch_spe_register (regcache, tid, regno); + return; + } + + if (regaddr == -1) + { + memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ + regcache_raw_supply (regcache, regno, buf); + return; + } -#define COPY_REG(_idx_,_regi_) \ - if ((regno == -1) || regno == _regi_) \ - memcpy (regp + _idx_, ®isters[REGISTER_BYTE (_regi_)], \ - REGISTER_RAW_SIZE (_regi_)) + /* Read the raw register using sizeof(long) sized chunks. On a + 32-bit platform, 64-bit floating-point registers will require two + transfers. */ + for (bytes_transferred = 0; + bytes_transferred < register_size (gdbarch, regno); + bytes_transferred += sizeof (long)) + { + errno = 0; + *(long *) &buf[bytes_transferred] + = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); + regaddr += sizeof (long); + if (errno != 0) + { + char message[128]; + sprintf (message, "reading register %s (#%d)", + gdbarch_register_name (gdbarch, regno), regno); + perror_with_name (message); + } + } - for (regi = 0; regi < 32; regi++) + /* Now supply the register. Keep in mind that the regcache's idea + of the register's size may not be a multiple of sizeof + (long). */ + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) + { + /* Little-endian values are always found at the left end of the + bytes transferred. */ + regcache_raw_supply (regcache, regno, buf); + } + else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) { - COPY_REG (regmap[regi], regi); + /* Big-endian values are found at the right end of the bytes + transferred. */ + size_t padding = (bytes_transferred - register_size (gdbarch, regno)); + regcache_raw_supply (regcache, regno, buf + padding); } + else + internal_error (__FILE__, __LINE__, + _("fetch_register: unexpected byte order: %d"), + gdbarch_byte_order (gdbarch)); +} + +static void +supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) +{ + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); - for (regi = FIRST_UISA_SP_REGNUM; regi <= LAST_UISA_SP_REGNUM; regi++) + for (i = 0; i < ppc_num_vshrs; i++) { - COPY_REG (regmap[regi], regi); + regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, + *vsxregsetp + i * vsxregsize); } } -void -supply_fpregset (gdb_fpregset_t * fpregsetp) +static void +supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) { - int regi; - for (regi = 0; regi < 32; regi++) + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; + int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); + + for (i = 0; i < num_of_vrregs; i++) { - supply_register (FP0_REGNUM + regi, (char *) (*fpregsetp + regi)); + /* The last 2 registers of this set are only 32 bit long, not + 128. However an offset is necessary only for VSCR because it + occupies a whole vector, while VRSAVE occupies a full 4 bytes + slot. */ + if (i == (num_of_vrregs - 2)) + regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize + offset); + else + regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize); } } -/* Given a pointer to a floating point register set in /proc format - (fpregset_t *), update the register specified by REGNO from gdb's idea - of the current floating point register set. If REGNO is -1, update - them all. */ +static void +fetch_vsx_registers (struct regcache *regcache, int tid) +{ + int ret; + gdb_vsxregset_t regs; + + ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Unable to fetch VSX registers")); + } + supply_vsxregset (regcache, ®s); +} -void -fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) +static void +fetch_altivec_registers (struct regcache *regcache, int tid) { - int regi; - char *to; - char *from; + int ret; + gdb_vrregset_t regs; - for (regi = 0; regi < 32; regi++) + ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getvrregs = 0; + return; + } + perror_with_name (_("Unable to fetch AltiVec registers")); + } + supply_vrregset (regcache, ®s); +} + +/* This function actually issues the request to ptrace, telling + it to get all general-purpose registers and put them into the + specified regset. + + If the ptrace request does not exist, this function returns 0 + and properly sets the have_ptrace_* flag. If the request fails, + this function calls perror_with_name. Otherwise, if the request + succeeds, then the regcache gets filled and 1 is returned. */ +static int +fetch_all_gp_regs (struct regcache *regcache, int tid) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + gdb_gregset_t gregset; + + if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) + { + if (errno == EIO) + { + have_ptrace_getsetregs = 0; + return 0; + } + perror_with_name (_("Couldn't get general-purpose registers.")); + } + + supply_gregset (regcache, (const gdb_gregset_t *) &gregset); + + return 1; +} + +/* This is a wrapper for the fetch_all_gp_regs function. It is + responsible for verifying if this target has the ptrace request + that can be used to fetch all general-purpose registers at one + shot. If it doesn't, then we should fetch them using the + old-fashioned way, which is to iterate over the registers and + request them one by one. */ +static void +fetch_gp_regs (struct regcache *regcache, int tid) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int i; + + if (have_ptrace_getsetregs) + if (fetch_all_gp_regs (regcache, tid)) + return; + + /* If we've hit this point, it doesn't really matter which + architecture we are using. We just need to read the + registers in the "old-fashioned way". */ + for (i = 0; i < ppc_num_gprs; i++) + fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); +} + +/* This function actually issues the request to ptrace, telling + it to get all floating-point registers and put them into the + specified regset. + + If the ptrace request does not exist, this function returns 0 + and properly sets the have_ptrace_* flag. If the request fails, + this function calls perror_with_name. Otherwise, if the request + succeeds, then the regcache gets filled and 1 is returned. */ +static int +fetch_all_fp_regs (struct regcache *regcache, int tid) +{ + gdb_fpregset_t fpregs; + + if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) { - if ((regno == -1) || (regno == FP0_REGNUM + regi)) + if (errno == EIO) { - from = (char *) ®isters[REGISTER_BYTE (FP0_REGNUM + regi)]; - to = (char *) (*fpregsetp + regi); - memcpy (to, from, REGISTER_RAW_SIZE (FP0_REGNUM + regi)); + have_ptrace_getsetfpregs = 0; + return 0; } + perror_with_name (_("Couldn't get floating-point registers.")); } + + supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); + + return 1; +} + +/* This is a wrapper for the fetch_all_fp_regs function. It is + responsible for verifying if this target has the ptrace request + that can be used to fetch all floating-point registers at one + shot. If it doesn't, then we should fetch them using the + old-fashioned way, which is to iterate over the registers and + request them one by one. */ +static void +fetch_fp_regs (struct regcache *regcache, int tid) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int i; + + if (have_ptrace_getsetfpregs) + if (fetch_all_fp_regs (regcache, tid)) + return; + + /* If we've hit this point, it doesn't really matter which + architecture we are using. We just need to read the + registers in the "old-fashioned way". */ + for (i = 0; i < ppc_num_fprs; i++) + fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); +} + +static void +fetch_ppc_registers (struct regcache *regcache, int tid) +{ + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + fetch_gp_regs (regcache, tid); + if (tdep->ppc_fp0_regnum >= 0) + fetch_fp_regs (regcache, tid); + fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); + if (tdep->ppc_ps_regnum != -1) + fetch_register (regcache, tid, tdep->ppc_ps_regnum); + if (tdep->ppc_cr_regnum != -1) + fetch_register (regcache, tid, tdep->ppc_cr_regnum); + if (tdep->ppc_lr_regnum != -1) + fetch_register (regcache, tid, tdep->ppc_lr_regnum); + if (tdep->ppc_ctr_regnum != -1) + fetch_register (regcache, tid, tdep->ppc_ctr_regnum); + if (tdep->ppc_xer_regnum != -1) + fetch_register (regcache, tid, tdep->ppc_xer_regnum); + if (tdep->ppc_mq_regnum != -1) + fetch_register (regcache, tid, tdep->ppc_mq_regnum); + if (ppc_linux_trap_reg_p (gdbarch)) + { + fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); + fetch_register (regcache, tid, PPC_TRAP_REGNUM); + } + if (tdep->ppc_fpscr_regnum != -1) + fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); + if (have_ptrace_getvrregs) + if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) + fetch_altivec_registers (regcache, tid); + if (have_ptrace_getsetvsxregs) + if (tdep->ppc_vsr0_upper_regnum != -1) + fetch_vsx_registers (regcache, tid); + if (tdep->ppc_ev0_upper_regnum >= 0) + fetch_spe_register (regcache, tid, -1); +} + +/* Fetch registers from the child process. Fetch all registers if + regno == -1, otherwise fetch all general registers or all floating + point registers depending upon the value of regno. */ +static void +ppc_linux_fetch_inferior_registers (struct target_ops *ops, + struct regcache *regcache, int regno) +{ + /* Overload thread id onto process id */ + int tid = TIDGET (inferior_ptid); + + /* No thread id, just use process id */ + if (tid == 0) + tid = PIDGET (inferior_ptid); + + if (regno == -1) + fetch_ppc_registers (regcache, tid); + else + fetch_register (regcache, tid, regno); +} + +/* Store one VSX register. */ +static void +store_vsx_register (const struct regcache *regcache, int tid, int regno) +{ + int ret; + gdb_vsxregset_t regs; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + + ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Unable to fetch VSX register")); + } + + regcache_raw_collect (regcache, regno, regs + + (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); + + ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); + if (ret < 0) + perror_with_name (_("Unable to store VSX register")); +} + +/* Store one register. */ +static void +store_altivec_register (const struct regcache *regcache, int tid, int regno) +{ + int ret; + int offset = 0; + gdb_vrregset_t regs; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + + ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getvrregs = 0; + return; + } + perror_with_name (_("Unable to fetch AltiVec register")); + } + + /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes + long on the hardware. */ + if (regno == (tdep->ppc_vrsave_regnum - 1)) + offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); + + regcache_raw_collect (regcache, regno, + regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); + + ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); + if (ret < 0) + perror_with_name (_("Unable to store AltiVec register")); +} + +/* Assuming TID referrs to an SPE process, set the top halves of TID's + general-purpose registers and its SPE-specific registers to the + values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do + nothing. + + All the logic to deal with whether or not the PTRACE_GETEVRREGS and + PTRACE_SETEVRREGS requests are supported is isolated here, and in + get_spe_registers. */ +static void +set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) +{ + if (have_ptrace_getsetevrregs) + { + if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) + return; + else + { + /* EIO means that the PTRACE_SETEVRREGS request isn't + supported; we fail silently, and don't try the call + again. */ + if (errno == EIO) + have_ptrace_getsetevrregs = 0; + else + /* Anything else needs to be reported. */ + perror_with_name (_("Unable to set SPE registers")); + } + } +} + +/* Write GDB's value for the SPE-specific raw register REGNO to TID. + If REGNO is -1, write the values of all the SPE-specific + registers. */ +static void +store_spe_register (const struct regcache *regcache, int tid, int regno) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + struct gdb_evrregset_t evrregs; + + gdb_assert (sizeof (evrregs.evr[0]) + == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); + gdb_assert (sizeof (evrregs.acc) + == register_size (gdbarch, tdep->ppc_acc_regnum)); + gdb_assert (sizeof (evrregs.spefscr) + == register_size (gdbarch, tdep->ppc_spefscr_regnum)); + + if (regno == -1) + /* Since we're going to write out every register, the code below + should store to every field of evrregs; if that doesn't happen, + make it obvious by initializing it with suspicious values. */ + memset (&evrregs, 42, sizeof (evrregs)); + else + /* We can only read and write the entire EVR register set at a + time, so to write just a single register, we do a + read-modify-write maneuver. */ + get_spe_registers (tid, &evrregs); + + if (regno == -1) + { + int i; + + for (i = 0; i < ppc_num_gprs; i++) + regcache_raw_collect (regcache, + tdep->ppc_ev0_upper_regnum + i, + &evrregs.evr[i]); + } + else if (tdep->ppc_ev0_upper_regnum <= regno + && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) + regcache_raw_collect (regcache, regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); + + if (regno == -1 + || regno == tdep->ppc_acc_regnum) + regcache_raw_collect (regcache, + tdep->ppc_acc_regnum, + &evrregs.acc); + + if (regno == -1 + || regno == tdep->ppc_spefscr_regnum) + regcache_raw_collect (regcache, + tdep->ppc_spefscr_regnum, + &evrregs.spefscr); + + /* Write back the modified register set. */ + set_spe_registers (tid, &evrregs); +} + +static void +store_register (const struct regcache *regcache, int tid, int regno) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + /* This isn't really an address. But ptrace thinks of it as one. */ + CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); + int i; + size_t bytes_to_transfer; + char buf[MAX_REGISTER_SIZE]; + + if (altivec_register_p (gdbarch, regno)) + { + store_altivec_register (regcache, tid, regno); + return; + } + if (vsx_register_p (gdbarch, regno)) + { + store_vsx_register (regcache, tid, regno); + return; + } + else if (spe_register_p (gdbarch, regno)) + { + store_spe_register (regcache, tid, regno); + return; + } + + if (regaddr == -1) + return; + + /* First collect the register. Keep in mind that the regcache's + idea of the register's size may not be a multiple of sizeof + (long). */ + memset (buf, 0, sizeof buf); + bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) + { + /* Little-endian values always sit at the left end of the buffer. */ + regcache_raw_collect (regcache, regno, buf); + } + else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) + { + /* Big-endian values sit at the right end of the buffer. */ + size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); + regcache_raw_collect (regcache, regno, buf + padding); + } + + for (i = 0; i < bytes_to_transfer; i += sizeof (long)) + { + errno = 0; + ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, + *(long *) &buf[i]); + regaddr += sizeof (long); + + if (errno == EIO + && (regno == tdep->ppc_fpscr_regnum + || regno == PPC_ORIG_R3_REGNUM + || regno == PPC_TRAP_REGNUM)) + { + /* Some older kernel versions don't allow fpscr, orig_r3 + or trap to be written. */ + continue; + } + + if (errno != 0) + { + char message[128]; + sprintf (message, "writing register %s (#%d)", + gdbarch_register_name (gdbarch, regno), regno); + perror_with_name (message); + } + } +} + +static void +fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) +{ + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + + for (i = 0; i < ppc_num_vshrs; i++) + regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, + *vsxregsetp + i * vsxregsize); +} + +static void +fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) +{ + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; + int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); + + for (i = 0; i < num_of_vrregs; i++) + { + /* The last 2 registers of this set are only 32 bit long, not + 128, but only VSCR is fetched as a 16 bytes quantity. */ + if (i == (num_of_vrregs - 2)) + regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize + offset); + else + regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize); + } +} + +static void +store_vsx_registers (const struct regcache *regcache, int tid) +{ + int ret; + gdb_vsxregset_t regs; + + ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getsetvsxregs = 0; + return; + } + perror_with_name (_("Couldn't get VSX registers")); + } + + fill_vsxregset (regcache, ®s); + + if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) + perror_with_name (_("Couldn't write VSX registers")); +} + +static void +store_altivec_registers (const struct regcache *regcache, int tid) +{ + int ret; + gdb_vrregset_t regs; + + ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); + if (ret < 0) + { + if (errno == EIO) + { + have_ptrace_getvrregs = 0; + return; + } + perror_with_name (_("Couldn't get AltiVec registers")); + } + + fill_vrregset (regcache, ®s); + + if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) + perror_with_name (_("Couldn't write AltiVec registers")); +} + +/* This function actually issues the request to ptrace, telling + it to store all general-purpose registers present in the specified + regset. + + If the ptrace request does not exist, this function returns 0 + and properly sets the have_ptrace_* flag. If the request fails, + this function calls perror_with_name. Otherwise, if the request + succeeds, then the regcache is stored and 1 is returned. */ +static int +store_all_gp_regs (const struct regcache *regcache, int tid, int regno) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + gdb_gregset_t gregset; + + if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) + { + if (errno == EIO) + { + have_ptrace_getsetregs = 0; + return 0; + } + perror_with_name (_("Couldn't get general-purpose registers.")); + } + + fill_gregset (regcache, &gregset, regno); + + if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) + { + if (errno == EIO) + { + have_ptrace_getsetregs = 0; + return 0; + } + perror_with_name (_("Couldn't set general-purpose registers.")); + } + + return 1; +} + +/* This is a wrapper for the store_all_gp_regs function. It is + responsible for verifying if this target has the ptrace request + that can be used to store all general-purpose registers at one + shot. If it doesn't, then we should store them using the + old-fashioned way, which is to iterate over the registers and + store them one by one. */ +static void +store_gp_regs (const struct regcache *regcache, int tid, int regno) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int i; + + if (have_ptrace_getsetregs) + if (store_all_gp_regs (regcache, tid, regno)) + return; + + /* If we hit this point, it doesn't really matter which + architecture we are using. We just need to store the + registers in the "old-fashioned way". */ + for (i = 0; i < ppc_num_gprs; i++) + store_register (regcache, tid, tdep->ppc_gp0_regnum + i); +} + +/* This function actually issues the request to ptrace, telling + it to store all floating-point registers present in the specified + regset. + + If the ptrace request does not exist, this function returns 0 + and properly sets the have_ptrace_* flag. If the request fails, + this function calls perror_with_name. Otherwise, if the request + succeeds, then the regcache is stored and 1 is returned. */ +static int +store_all_fp_regs (const struct regcache *regcache, int tid, int regno) +{ + gdb_fpregset_t fpregs; + + if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) + { + if (errno == EIO) + { + have_ptrace_getsetfpregs = 0; + return 0; + } + perror_with_name (_("Couldn't get floating-point registers.")); + } + + fill_fpregset (regcache, &fpregs, regno); + + if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) + { + if (errno == EIO) + { + have_ptrace_getsetfpregs = 0; + return 0; + } + perror_with_name (_("Couldn't set floating-point registers.")); + } + + return 1; +} + +/* This is a wrapper for the store_all_fp_regs function. It is + responsible for verifying if this target has the ptrace request + that can be used to store all floating-point registers at one + shot. If it doesn't, then we should store them using the + old-fashioned way, which is to iterate over the registers and + store them one by one. */ +static void +store_fp_regs (const struct regcache *regcache, int tid, int regno) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int i; + + if (have_ptrace_getsetfpregs) + if (store_all_fp_regs (regcache, tid, regno)) + return; + + /* If we hit this point, it doesn't really matter which + architecture we are using. We just need to store the + registers in the "old-fashioned way". */ + for (i = 0; i < ppc_num_fprs; i++) + store_register (regcache, tid, tdep->ppc_fp0_regnum + i); +} + +static void +store_ppc_registers (const struct regcache *regcache, int tid) +{ + int i; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + store_gp_regs (regcache, tid, -1); + if (tdep->ppc_fp0_regnum >= 0) + store_fp_regs (regcache, tid, -1); + store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); + if (tdep->ppc_ps_regnum != -1) + store_register (regcache, tid, tdep->ppc_ps_regnum); + if (tdep->ppc_cr_regnum != -1) + store_register (regcache, tid, tdep->ppc_cr_regnum); + if (tdep->ppc_lr_regnum != -1) + store_register (regcache, tid, tdep->ppc_lr_regnum); + if (tdep->ppc_ctr_regnum != -1) + store_register (regcache, tid, tdep->ppc_ctr_regnum); + if (tdep->ppc_xer_regnum != -1) + store_register (regcache, tid, tdep->ppc_xer_regnum); + if (tdep->ppc_mq_regnum != -1) + store_register (regcache, tid, tdep->ppc_mq_regnum); + if (tdep->ppc_fpscr_regnum != -1) + store_register (regcache, tid, tdep->ppc_fpscr_regnum); + if (ppc_linux_trap_reg_p (gdbarch)) + { + store_register (regcache, tid, PPC_ORIG_R3_REGNUM); + store_register (regcache, tid, PPC_TRAP_REGNUM); + } + if (have_ptrace_getvrregs) + if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) + store_altivec_registers (regcache, tid); + if (have_ptrace_getsetvsxregs) + if (tdep->ppc_vsr0_upper_regnum != -1) + store_vsx_registers (regcache, tid); + if (tdep->ppc_ev0_upper_regnum >= 0) + store_spe_register (regcache, tid, -1); +} + +static int +ppc_linux_check_watch_resources (int type, int cnt, int ot) +{ + int tid; + ptid_t ptid = inferior_ptid; + + /* DABR (data address breakpoint register) is optional for PPC variants. + Some variants have one DABR, others have none. So CNT can't be larger + than 1. */ + if (cnt > 1) + return 0; + + /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether + the target has DABR. If either answer is no, the ptrace call will + return -1. Fail in that case. */ + tid = TIDGET (ptid); + if (tid == 0) + tid = PIDGET (ptid); + + if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) + return 0; + return 1; +} + +/* Fetch the AT_HWCAP entry from the aux vector. */ +unsigned long ppc_linux_get_hwcap (void) +{ + CORE_ADDR field; + + if (target_auxv_search (¤t_target, AT_HWCAP, &field)) + return (unsigned long) field; + + return 0; +} + +static int +ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) +{ + /* Handle sub-8-byte quantities. */ + if (len <= 0) + return 0; + + /* addr+len must fall in the 8 byte watchable region for DABR-based + processors. DAC-based processors, like the PowerPC 440, will use + addresses aligned to 4-bytes due to the way the read/write flags are + passed at the moment. */ + if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + && (addr + len) > (addr & ~3) + 4) + || (addr + len) > (addr & ~7) + 8) + return 0; + + return 1; +} + +/* The cached DABR value, to install in new threads. */ +static long saved_dabr_value; + +/* Set a watchpoint of type TYPE at address ADDR. */ +static int +ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) +{ + struct lwp_info *lp; + ptid_t ptid; + long dabr_value; + long read_mode, write_mode; + + if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + { + /* PowerPC 440 requires only the read/write flags to be passed + to the kernel. */ + read_mode = 1; + write_mode = 2; + } + else + { + /* PowerPC 970 and other DABR-based processors are required to pass + the Breakpoint Translation bit together with the flags. */ + read_mode = 5; + write_mode = 6; + } + + dabr_value = addr & ~(read_mode | write_mode); + switch (rw) + { + case hw_read: + /* Set read and translate bits. */ + dabr_value |= read_mode; + break; + case hw_write: + /* Set write and translate bits. */ + dabr_value |= write_mode; + break; + case hw_access: + /* Set read, write and translate bits. */ + dabr_value |= read_mode | write_mode; + break; + } + + saved_dabr_value = dabr_value; + + ALL_LWPS (lp, ptid) + if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) + return -1; + + return 0; +} + +static int +ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw) +{ + struct lwp_info *lp; + ptid_t ptid; + long dabr_value = 0; + + saved_dabr_value = 0; + ALL_LWPS (lp, ptid) + if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0) + return -1; + return 0; +} + +static void +ppc_linux_new_thread (ptid_t ptid) +{ + ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value); +} + +static int +ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) +{ + struct siginfo *siginfo_p; + + siginfo_p = linux_nat_get_siginfo (inferior_ptid); + + if (siginfo_p->si_signo != SIGTRAP + || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) + return 0; + + *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr; + return 1; +} + +static int +ppc_linux_stopped_by_watchpoint (void) +{ + CORE_ADDR addr; + return ppc_linux_stopped_data_address (¤t_target, &addr); +} + +static int +ppc_linux_watchpoint_addr_within_range (struct target_ops *target, + CORE_ADDR addr, + CORE_ADDR start, int length) +{ + int mask; + + if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + mask = 3; + else + mask = 7; + + addr &= ~mask; + + /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ + return start <= addr + mask && start + length - 1 >= addr; +} + +static void +ppc_linux_store_inferior_registers (struct target_ops *ops, + struct regcache *regcache, int regno) +{ + /* Overload thread id onto process id */ + int tid = TIDGET (inferior_ptid); + + /* No thread id, just use process id */ + if (tid == 0) + tid = PIDGET (inferior_ptid); + + if (regno >= 0) + store_register (regcache, tid, regno); + else + store_ppc_registers (regcache, tid); +} + +/* Functions for transferring registers between a gregset_t or fpregset_t + (see sys/ucontext.h) and gdb's regcache. The word size is that used + by the ptrace interface, not the current program's ABI. eg. If a + powerpc64-linux gdb is being used to debug a powerpc32-linux app, we + read or write 64-bit gregsets. This is to suit the host libthread_db. */ + +void +supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) +{ + const struct regset *regset = ppc_linux_gregset (sizeof (long)); + + ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); +} + +void +fill_gregset (const struct regcache *regcache, + gdb_gregset_t *gregsetp, int regno) +{ + const struct regset *regset = ppc_linux_gregset (sizeof (long)); + + if (regno == -1) + memset (gregsetp, 0, sizeof (*gregsetp)); + ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); +} + +void +supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) +{ + const struct regset *regset = ppc_linux_fpregset (); + + ppc_supply_fpregset (regset, regcache, -1, + fpregsetp, sizeof (*fpregsetp)); +} + +void +fill_fpregset (const struct regcache *regcache, + gdb_fpregset_t *fpregsetp, int regno) +{ + const struct regset *regset = ppc_linux_fpregset (); + + ppc_collect_fpregset (regset, regcache, regno, + fpregsetp, sizeof (*fpregsetp)); +} + +static int +ppc_linux_target_wordsize (void) +{ + int wordsize = 4; + + /* Check for 64-bit inferior process. This is the case when the host is + 64-bit, and in addition the top bit of the MSR register is set. */ +#ifdef __powerpc64__ + long msr; + + int tid = TIDGET (inferior_ptid); + if (tid == 0) + tid = PIDGET (inferior_ptid); + + errno = 0; + msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); + if (errno == 0 && msr < 0) + wordsize = 8; +#endif + + return wordsize; +} + +static int +ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr, + gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) +{ + int sizeof_auxv_field = ppc_linux_target_wordsize (); + enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch); + gdb_byte *ptr = *readptr; + + if (endptr == ptr) + return 0; + + if (endptr - ptr < sizeof_auxv_field * 2) + return -1; + + *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); + ptr += sizeof_auxv_field; + *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); + ptr += sizeof_auxv_field; + + *readptr = ptr; + return 1; +} + +static const struct target_desc * +ppc_linux_read_description (struct target_ops *ops) +{ + int altivec = 0; + int vsx = 0; + int isa205 = 0; + int cell = 0; + + int tid = TIDGET (inferior_ptid); + if (tid == 0) + tid = PIDGET (inferior_ptid); + + if (have_ptrace_getsetevrregs) + { + struct gdb_evrregset_t evrregset; + + if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) + return tdesc_powerpc_e500l; + + /* EIO means that the PTRACE_GETEVRREGS request isn't supported. + Anything else needs to be reported. */ + else if (errno != EIO) + perror_with_name (_("Unable to fetch SPE registers")); + } + + if (have_ptrace_getsetvsxregs) + { + gdb_vsxregset_t vsxregset; + + if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) + vsx = 1; + + /* EIO means that the PTRACE_GETVSXREGS request isn't supported. + Anything else needs to be reported. */ + else if (errno != EIO) + perror_with_name (_("Unable to fetch VSX registers")); + } + + if (have_ptrace_getvrregs) + { + gdb_vrregset_t vrregset; + + if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) + altivec = 1; + + /* EIO means that the PTRACE_GETVRREGS request isn't supported. + Anything else needs to be reported. */ + else if (errno != EIO) + perror_with_name (_("Unable to fetch AltiVec registers")); + } + + /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases + the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this + ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only + PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher + half of the register are for Decimal Floating Point, we check if that + feature is available to decide the size of the FPSCR. */ + if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) + isa205 = 1; + + if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL) + cell = 1; + + if (ppc_linux_target_wordsize () == 8) + { + if (cell) + return tdesc_powerpc_cell64l; + else if (vsx) + return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; + else if (altivec) + return isa205? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; + + return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; + } + + if (cell) + return tdesc_powerpc_cell32l; + else if (vsx) + return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; + else if (altivec) + return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; + + return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; +} + +void _initialize_ppc_linux_nat (void); + +void +_initialize_ppc_linux_nat (void) +{ + struct target_ops *t; + + /* Fill in the generic GNU/Linux methods. */ + t = linux_target (); + + /* Add our register access methods. */ + t->to_fetch_registers = ppc_linux_fetch_inferior_registers; + t->to_store_registers = ppc_linux_store_inferior_registers; + + /* Add our watchpoint methods. */ + t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources; + t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint; + t->to_insert_watchpoint = ppc_linux_insert_watchpoint; + t->to_remove_watchpoint = ppc_linux_remove_watchpoint; + t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint; + t->to_stopped_data_address = ppc_linux_stopped_data_address; + t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range; + + t->to_read_description = ppc_linux_read_description; + t->to_auxv_parse = ppc_linux_auxv_parse; + + /* Register the target. */ + linux_nat_add_target (t); + linux_nat_set_new_thread (t, ppc_linux_new_thread); }