X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Fppc-linux-nat.c;h=a8f202dd33531da56eb3d3e27f7e2f8f27709dd6;hb=d078308a2ed1290e587b4365e2d7382d951a26af;hp=7e96032d4c028bc78abe9a90e217b0ff5e4fa780;hpb=2e077f5e67aeff78e096a250bd225cd4658a35dc;p=deliverable%2Fbinutils-gdb.git

diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index 7e96032d4c..a8f202dd33 100644
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -174,9 +174,7 @@ struct ppc_hw_breakpoint
 */
 /* *INDENT-ON* */
 
-#define SIZEOF_VRREGS 33*16+4
-
-typedef char gdb_vrregset_t[SIZEOF_VRREGS];
+typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET];
 
 /* This is the layout of the POWER7 VSX registers and the way they overlap
    with the existing FPR and VMX registers.
@@ -210,9 +208,7 @@ typedef char gdb_vrregset_t[SIZEOF_VRREGS];
    the FP registers (doubleword 0) and hence extend them with additional
    64 bits (doubleword 1).  The other 32 regs overlap with the VMX
    registers.  */
-#define SIZEOF_VSXREGS 32*8
-
-typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
+typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET];
 
 /* On PPC processors that support the Signal Processing Extension
    (SPE) APU, the general-purpose registers are 64 bits long.