X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Fspu-tdep.c;h=a45532bf8091a44e54e5c7f6c68140e113cd2878;hb=e0cd558aaae1d2c457f3963c58e78ec419f0712a;hp=7e722751be53543ef996553bd6bf6b7af5821d27;hpb=06a862851c31bb286d5f8177b9a5db6a65282fb8;p=deliverable%2Fbinutils-gdb.git

diff --git a/gdb/spu-tdep.c b/gdb/spu-tdep.c
index 7e722751be..a45532bf80 100644
--- a/gdb/spu-tdep.c
+++ b/gdb/spu-tdep.c
@@ -1079,52 +1079,47 @@ spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
 /* Software single-stepping support.  */
 
 int
-spu_software_single_step (enum target_signal signal, int insert_breakpoints_p)
+spu_software_single_step (struct regcache *regcache)
 {
-  if (insert_breakpoints_p)
-    {
-      CORE_ADDR pc, next_pc;
-      unsigned int insn;
-      int offset, reg;
-      gdb_byte buf[4];
-
-      regcache_cooked_read (current_regcache, SPU_PC_REGNUM, buf);
-      /* Mask off interrupt enable bit.  */
-      pc = extract_unsigned_integer (buf, 4) & -4;
+  CORE_ADDR pc, next_pc;
+  unsigned int insn;
+  int offset, reg;
+  gdb_byte buf[4];
 
-      if (target_read_memory (pc, buf, 4))
-	return 1;
-      insn = extract_unsigned_integer (buf, 4);
+  regcache_cooked_read (regcache, SPU_PC_REGNUM, buf);
+  /* Mask off interrupt enable bit.  */
+  pc = extract_unsigned_integer (buf, 4) & -4;
 
-       /* Next sequential instruction is at PC + 4, except if the current
-	  instruction is a PPE-assisted call, in which case it is at PC + 8.
-	  Wrap around LS limit to be on the safe side.  */
-      if ((insn & 0xffffff00) == 0x00002100)
-	next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
-      else
-	next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
+  if (target_read_memory (pc, buf, 4))
+    return 1;
+  insn = extract_unsigned_integer (buf, 4);
 
-      insert_single_step_breakpoint (next_pc);
+  /* Next sequential instruction is at PC + 4, except if the current
+     instruction is a PPE-assisted call, in which case it is at PC + 8.
+     Wrap around LS limit to be on the safe side.  */
+  if ((insn & 0xffffff00) == 0x00002100)
+    next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
+  else
+    next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
 
-      if (is_branch (insn, &offset, &reg))
-	{
-	  CORE_ADDR target = offset;
+  insert_single_step_breakpoint (next_pc);
 
-	  if (reg == SPU_PC_REGNUM)
-	    target += pc;
-	  else if (reg != -1)
-	    {
-	      regcache_cooked_read_part (current_regcache, reg, 0, 4, buf);
-	      target += extract_unsigned_integer (buf, 4) & -4;
-	    }
+  if (is_branch (insn, &offset, &reg))
+    {
+      CORE_ADDR target = offset;
 
-	  target = target & (SPU_LS_SIZE - 1);
-	  if (target != next_pc)
-	    insert_single_step_breakpoint (target);
+      if (reg == SPU_PC_REGNUM)
+	target += pc;
+      else if (reg != -1)
+	{
+	  regcache_cooked_read_part (regcache, reg, 0, 4, buf);
+	  target += extract_unsigned_integer (buf, 4) & -4;
 	}
+
+      target = target & (SPU_LS_SIZE - 1);
+      if (target != next_pc)
+	insert_single_step_breakpoint (target);
     }
-  else
-    remove_single_step_breakpoints ();
 
   return 1;
 }