X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=include%2Fopcode%2FChangeLog;h=189a1d4176c2e61975474719b4c8697416f4433a;hb=c3678916c694b6af469a882ae1df0dc15b89f44a;hp=1091973b2b1362a9471031dd2367e4ad784280d3;hpb=03f66e8a8f77e2df4ecdc9b32bcc96ab5cb0e85e;p=deliverable%2Fbinutils-gdb.git diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 1091973b2b..189a1d4176 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,6 +1,204 @@ +2013-06-23 Richard Sandiford + + * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. + +2013-06-17 Catherine Moore + Maciej W. Rozycki + Chao-Ying Fu + + * mips.h (OP_SH_EVAOFFSET): Define. + (OP_MASK_EVAOFFSET): Define. + (INSN_ASE_MASK): Delete. + (ASE_EVA): Define. + (M_CACHEE_AB, M_CACHEE_OB): New. + (M_LBE_OB, M_LBE_AB): New. + (M_LBUE_OB, M_LBUE_AB): New. + (M_LHE_OB, M_LHE_AB): New. + (M_LHUE_OB, M_LHUE_AB): New. + (M_LLE_AB, M_LLE_OB): New. + (M_LWE_OB, M_LWE_AB): New. + (M_LWLE_AB, M_LWLE_OB): New. + (M_LWRE_AB, M_LWRE_OB): New. + (M_PREFE_AB, M_PREFE_OB): New. + (M_SCE_AB, M_SCE_OB): New. + (M_SBE_OB, M_SBE_AB): New. + (M_SHE_OB, M_SHE_AB): New. + (M_SWE_OB, M_SWE_AB): New. + (M_SWLE_AB, M_SWLE_OB): New. + (M_SWRE_AB, M_SWRE_OB): New. + (MICROMIPSOP_SH_EVAOFFSET): Define. + (MICROMIPSOP_MASK_EVAOFFSET): Define. + +2013-06-12 Sandra Loosemore + + * nios2.h (OP_MATCH_ERET): Correct eret encoding. + +2013-05-22 Jürgen Urban + + * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. + +2013-05-09 Andrew Pinski + + * mips.h (OP_MASK_CODE10): Correct definition. + (OP_SH_CODE10): Likewise. + Add a comment that "+J" is used now for OP_*CODE10. + (INSN_ASE_MASK): Update. + (INSN_VIRT): New macro. + (INSN_VIRT64): New macro + +2013-05-02 Nick Clifton + + * msp430.h: Add patterns for MSP430X instructions. + +2013-04-06 David S. Miller + + * sparc.h (F_PREFERRED): Define. + (F_PREF_ALIAS): Define. + +2013-04-03 Nick Clifton + + * v850.h (V850_INVERSE_PCREL): Define. + +2013-03-27 Alexis Deruelle + + PR binutils/15068 + * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. + +2013-03-27 Alexis Deruelle + + PR binutils/15068 + * tic6xc-insn-formats.h (FLD): Add use of bitfield array. + Add 16-bit opcodes. + * tic6xc-opcode-table.h: Add 16-bit insns. + * tic6x.h: Add support for 16-bit insns. + +2013-03-21 Michael Schewe + + * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd + and mov.b/w/l Rs,@(d:32,ERd). + +2013-03-20 Alexis Deruelle + + PR gas/15082 + * tic6x-opcode-table.h: Rename mpydp's specific operand type macro + from ORREGD1324 to ORXREGD1324 and make it cross-path-able through + tic6x_operand_xregpair operand coding type. + Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' + opcode field, usu ORXREGD1324 for the src2 operand and remove the + TIC6X_FLAG_NO_CROSS. + +2013-03-20 Alexis Deruelle + + PR gas/15095 + * tic6x.h (enum tic6x_coding_method): Add + tic6x_coding_dreg_(msb|lsb) field coding type in order to encode + separately the msb and lsb of a register pair. This is needed to + encode the opcodes in the same way as TI assembler does. + * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp + and rsqrdp opcodes to use the new field coding types. + +2013-03-11 Kyrylo Tkachov + + * arm.h (CRC_EXT_ARMV8): New constant. + (ARCH_CRC_ARMV8): New macro. + +2013-02-28 Yufeng Zhang + + * aarch64.h (AARCH64_FEATURE_CRC): New macro. + +2013-02-06 Sandra Loosemore + Andrew Jenner + + Based on patches from Altera Corporation. + + * nios2.h: New file. + +2013-01-30 Yufeng Zhang + + * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. + +2013-01-28 Alexis Deruelle + + PR gas/15069 + * tic6x-opcode-table.h: Fix encoding of BNOP instruction. + +2013-01-24 Nick Clifton + + * v850.h: Add e3v5 support. + +2013-01-17 Yufeng Zhang + + * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. + +2013-01-10 Peter Bergner + + * ppc.h (PPC_OPCODE_POWER8): New define. + (PPC_OPCODE_HTM): Likewise. + +2013-01-10 Will Newton + + * metag.h: New file. + +2013-01-07 Kaushik Phatak + + * cr16.h (make_instruction): Rename to cr16_make_instruction. + (match_opcode): Rename to cr16_match_opcode. + +2013-01-04 Juergen Urban + + * mips.h: Add support for r5900 instructions including lq and sq. + +2013-01-02 Kaushik Phatak + + * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c + (make_instruction,match_opcode): Added function prototypes. + (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern. + +2012-11-23 Alan Modra + + * ppc.h (ppc_parse_cpu): Update prototype. + +2012-10-14 John David Anglin + + * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx + opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes. + +2012-10-04 Andreas Krebbel + + * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. + +2012-09-04 Sergey A. Guriev + + * ia64.h (ia64_opnd): Add new operand types. + +2012-08-21 David S. Miller + + * sparc.h (F3F4): New macro. + +2012-08-13 Ian Bolton + Laurent Desnogues + Jim MacArthur + Marcus Shawcroft + Nigel Stephens + Ramana Radhakrishnan + Richard Earnshaw + Sofiane Naci + Tejas Belagod + Yufeng Zhang + + * aarch64.h: New file. + +2012-08-13 Richard Sandiford + Maciej W. Rozycki + + * mips.h (mips_opcode): Add the exclusions field. + (OPCODE_IS_MEMBER): Remove macro. + (cpu_is_member): New inline function. + (opcode_is_member): Likewise. + 2012-07-31 Chao-Ying Fu - Catherine Moore - Maciej W. Rozycki + Catherine Moore + Maciej W. Rozycki * mips.h: Document microMIPS DSP ASE usage. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for @@ -85,7 +283,7 @@ (XRELEASE_PREFIX_OPCODE): Likewise. 2011-12-08 Andrew Pinski - Adam Nemet + Adam Nemet * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. (INSN_OCTEON2): New macro. @@ -116,7 +314,7 @@ F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. 2011-08-09 Chao-ying Fu - Maciej W. Rozycki + Maciej W. Rozycki * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. @@ -162,7 +360,7 @@ (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. 2011-07-24 Chao-ying Fu - Maciej W. Rozycki + Maciej W. Rozycki * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. (OP_MASK_STYPE, OP_SH_STYPE): Likewise. @@ -725,7 +923,7 @@ 2008-11-28 Joshua Kinard * mips.h: Define CPU_R14000, CPU_R16000. - (OPCODE_IS_MEMBER): Include R14000, R16000 in test. + (OPCODE_IS_MEMBER): Include R14000, R16000 in test. 2008-11-18 Catherine Moore @@ -964,9 +1162,9 @@ * i386.h: Replace CpuMNI with CpuSSSE3. 2006-09-26 Mark Shinwell - Joseph Myers - Ian Lance Taylor - Ben Elliston + Joseph Myers + Ian Lance Taylor + Ben Elliston * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. @@ -1009,18 +1207,18 @@ * m68k.h (mcf_mask): Define. 2006-05-05 Thiemo Seufer - David Ung + David Ung * mips.h (enum): Add macro M_CACHE_AB. 2006-05-04 Thiemo Seufer - Nigel Stephens + Nigel Stephens David Ung * mips.h: Add INSN_SMARTMIPS define. 2006-04-30 Thiemo Seufer - David Ung + David Ung * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi @@ -1545,6 +1743,12 @@ For older changes see ChangeLog-9103 +Copyright (C) 2004-2012 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. + Local Variables: mode: change-log left-margin: 8