X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=include%2Fopcode%2FChangeLog;h=d378910e4778dae7fc4ebb810a2bf90d041a9efc;hb=3d68f91c0fb05b426e554004cabd3ded4c91f9c8;hp=a46900ac1373c0f50bc2012cb9059fcc8f56d3e7;hpb=dd5181d57f54aba7df0cee40028b9b446ef55f57;p=deliverable%2Fbinutils-gdb.git diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index a46900ac13..d378910e47 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,427 @@ +2014-10-09 Jose E. Marchesi + + * sparc.h (sparc_opcode): new field `hwcaps2'. + (HWCAP2_FJATHPLUS): New define. + (HWCAP2_VIS3B): Likewise. + (HWCAP2_ADP): Likewise. + (HWCAP2_SPARC5): Likewise. + (HWCAP2_MWAIT): Likewise. + (HWCAP2_XMPMUL): Likewise. + (HWCAP2_XMONT): Likewise. + (HWCAP2_NSEC): Likewise. + (HWCAP2_FJATHHPC): Likewise. + (HWCAP2_FJDES): Likewise. + (HWCAP2_FJAES): Likewise. + Document the new operand kind `{', corresponding to the mcdper + ancillary state register. + Document the new operand kind }, which represents frsd floating + point registers (double precision) which must be the same than + frs1 in its containing instruction. + +2014-09-16 Kuan-Lin Chen + + * nds32.h: Add new opcode declaration. + +2014-09-15 Andrew Bennett + Matthew Fortune + + * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT, + OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6 + instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, + +I, +O, +R, +:, +\, +", +; + (mips_check_prev_operand): New struct. + (INSN2_FORBIDDEN_SLOT): New define. + (INSN_ISA32R6): New define. + (INSN_ISA64R6): New define. + (INSN_UPTO32R6): New define. + (INSN_UPTO64R6): New define. + (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6. + (ISA_MIPS32R6): New define. + (ISA_MIPS64R6): New define. + (CPU_MIPS32R6): New define. + (CPU_MIPS64R6): New define. + (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6. + +2014-09-03 Jiong Wang + + * aarch64.h (AARCH64_FEATURE_LSE): New feature added. + (aarch64_opnd): Add AARCH64_OPND_PAIRREG. + (aarch64_insn_class): Add lse_atomic. + (F_LSE_SZ): New field added. + (opcode_has_special_coder): Recognize F_LSE_SZ. + +2014-08-26 Maciej W. Rozycki + + * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' + over to `+J'. + +2014-07-29 Matthew Fortune + + * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... + (INSN_LOAD_COPROC): New define. + (INSN_COPROC_MOVE_DELAY): Rename to... + (INSN_COPROC_MOVE): New define. + +2014-07-01 Barney Stratford + Senthil Kumar Selvaraj + Pitchumani Sivanupandi + Soundararajan + + * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA. + (AVR_ISA_2xxxa): Define ISA without LPM. + (AVR_ISA_AVRTINY): Define avrtiny arch ISA. + Add doc for contraint used in 16 bit lds/sts. + Adjust ISA group for icall, ijmp, pop and push. + Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints. + +2014-05-19 Nick Clifton + + * msp430.h (struct msp430_operand_s): Add vshift field. + +2014-05-07 Andrew Bennett + + * mips.h (INSN_ISA_MASK): Updated. + (INSN_ISA32R3): New define. + (INSN_ISA32R5): New define. + (INSN_ISA64R3): New define. + (INSN_ISA64R5): New define. + (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 + INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. + (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and + mips64r5. + (INSN_UPTO32R3): New define. + (INSN_UPTO32R5): New define. + (INSN_UPTO64R3): New define. + (INSN_UPTO64R5): New define. + (ISA_MIPS32R3): New define. + (ISA_MIPS32R5): New define. + (ISA_MIPS64R3): New define. + (ISA_MIPS64R5): New define. + (CPU_MIPS32R3): New define. + (CPU_MIPS32R5): New define. + (CPU_MIPS64R3): New define. + (CPU_MIPS64R5): New define. + +2014-05-01 Richard Sandiford + + * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. + +2014-04-22 Christian Svensson + + * or32.h: Delete. + +2014-03-05 Alan Modra + + Update copyright years. + +2013-12-16 Andrew Bennett + + * mips.h: Updated description of +o, +u, +v and +w for MIPS and + microMIPS. + +2013-12-13 Kuan-Lin Chen + Wei-Cheng Wang + + * nds32.h: New file for Andes NDS32. + +2013-12-07 Mike Frysinger + + * bfin.h: Remove +x file mode. + +2013-11-20 Yufeng Zhang + + * aarch64.h (aarch64_pstatefields): Change element type to + aarch64_sys_reg. + +2013-11-18 Renlin Li + + * arm.h (ARM_AEXT_V7VE): New define. + (ARM_ARCH_V7VE): New define. + (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed. + +2013-11-18 Yufeng Zhang + + Revert + + 2013-11-15 Yufeng Zhang + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-15 Yufeng Zhang + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-05 Yufeng Zhang + + * aarch64.h (aarch64_sys_reg): New typedef. + (aarch64_sys_regs): Change to define with the new type. + (aarch64_sys_reg_deprecated_p): Declare. + +2013-11-05 Yufeng Zhang + + * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. + (enum aarch64_opnd): Add AARCH64_OPND_COND1. + +2013-10-14 Chao-ying Fu + + * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. + (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. + For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For MIPS, update extension character sequences after +. + (ASE_MSA): New define. + (ASE_MSA64): New define. + For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For microMIPS, update extension character sequences after +. + +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * i960.h: Fix typos. + +2013-08-19 Richard Sandiford + + * mips.h: Remove references to "+I" and imm2_expr. + +2013-08-19 Richard Sandiford + + * mips.h (M_DEXT, M_DINS): Delete. + +2013-08-19 Richard Sandiford + + * mips.h (OP_OPTIONAL_REG): New mips_operand_type. + (mips_optional_operand_p): New function. + +2013-08-04 Jürgen Urban + Richard Sandiford + + * mips.h: Document new VU0 operand characters. + (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. + (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) + (OP_REG_R5900_ACC): New mips_reg_operand_types. + (INSN2_VU0_CHANNEL_SUFFIX): New macro. + (mips_vu0_channel_mask): Declare. + +2013-08-03 Richard Sandiford + + * mips.h (mips_pcrel_operand): Inherit from mips_int_operand. + (mips_int_operand_min, mips_int_operand_max): New functions. + (mips_decode_pcrel_operand): Use mips_decode_int_operand. + +2013-08-01 Richard Sandiford + + * mips.h (mips_decode_reg_operand): New function. + (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) + (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) + (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): + New macros. + (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) + (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) + (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) + (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) + (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) + (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) + (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) + (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) + (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) + (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other + macros to cover the gaps. + (INSN2_MOD_SP): Replace with... + (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. + (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) + (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) + (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) + (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): + Delete. + +2013-08-01 Richard Sandiford + + * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) + (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) + (MIPS16_INSN_COND_BRANCH): Delete. + +2013-07-24 Anna Tikhonova + Kirill Yukhin + Michael Zolotukhin + + * i386.h (BND_PREFIX_OPCODE): New. + +2013-07-14 Richard Sandiford + + * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and + OP_SAVE_RESTORE_LIST. + (decode_mips16_operand): Declare. + +2013-07-14 Richard Sandiford + + * mips.h (mips_operand_type, mips_reg_operand_type): New enums. + (mips_operand, mips_int_operand, mips_mapped_int_operand) + (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) + (mips_pcrel_operand): New structures. + (mips_insert_operand, mips_extract_operand, mips_signed_operand) + (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. + (decode_mips_operand, decode_micromips_operand): Declare. + +2013-07-14 Richard Sandiford + + * mips.h: Document MIPS16 "I" opcode. + +2013-07-07 Richard Sandiford + + * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) + (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) + (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) + (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) + (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) + (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) + (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) + (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) + (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) + (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) + (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) + (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. + (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): + Rename to... + (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) + (M_USD_AB): ...these. + +2013-07-07 Richard Sandiford + + * mips.h: Remove documentation of "[" and "]". Update documentation + of "k" and the MDMX formats. + +2013-07-07 Richard Sandiford + + * mips.h: Update documentation of "+s" and "+S". + +2013-07-07 Richard Sandiford + + * mips.h: Document "+i". + +2013-07-07 Richard Sandiford + + * mips.h: Remove "mi" documentation. Update "mh" documentation. + (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): + Delete. + (INSN2_WRITE_GPR_MHI): Rename to... + (INSN2_WRITE_GPR_MH): ...this. + +2013-07-07 Richard Sandiford + + * mips.h: Remove documentation of "+D" and "+T". + +2013-06-26 Richard Sandiford + + * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. + Use "source" rather than "destination" for microMIPS "G". + +2013-06-25 Maciej W. Rozycki + + * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum + values. + +2013-06-23 Richard Sandiford + + * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. + +2013-06-17 Catherine Moore + Maciej W. Rozycki + Chao-Ying Fu + + * mips.h (OP_SH_EVAOFFSET): Define. + (OP_MASK_EVAOFFSET): Define. + (INSN_ASE_MASK): Delete. + (ASE_EVA): Define. + (M_CACHEE_AB, M_CACHEE_OB): New. + (M_LBE_OB, M_LBE_AB): New. + (M_LBUE_OB, M_LBUE_AB): New. + (M_LHE_OB, M_LHE_AB): New. + (M_LHUE_OB, M_LHUE_AB): New. + (M_LLE_AB, M_LLE_OB): New. + (M_LWE_OB, M_LWE_AB): New. + (M_LWLE_AB, M_LWLE_OB): New. + (M_LWRE_AB, M_LWRE_OB): New. + (M_PREFE_AB, M_PREFE_OB): New. + (M_SCE_AB, M_SCE_OB): New. + (M_SBE_OB, M_SBE_AB): New. + (M_SHE_OB, M_SHE_AB): New. + (M_SWE_OB, M_SWE_AB): New. + (M_SWLE_AB, M_SWLE_OB): New. + (M_SWRE_AB, M_SWRE_OB): New. + (MICROMIPSOP_SH_EVAOFFSET): Define. + (MICROMIPSOP_MASK_EVAOFFSET): Define. + +2013-06-12 Sandra Loosemore + + * nios2.h (OP_MATCH_ERET): Correct eret encoding. + +2013-05-22 Jürgen Urban + + * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. + +2013-05-09 Andrew Pinski + + * mips.h (OP_MASK_CODE10): Correct definition. + (OP_SH_CODE10): Likewise. + Add a comment that "+J" is used now for OP_*CODE10. + (INSN_ASE_MASK): Update. + (INSN_VIRT): New macro. + (INSN_VIRT64): New macro + +2013-05-02 Nick Clifton + + * msp430.h: Add patterns for MSP430X instructions. + +2013-04-06 David S. Miller + + * sparc.h (F_PREFERRED): Define. + (F_PREF_ALIAS): Define. + +2013-04-03 Nick Clifton + + * v850.h (V850_INVERSE_PCREL): Define. + +2013-03-27 Alexis Deruelle + + PR binutils/15068 + * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. + +2013-03-27 Alexis Deruelle + + PR binutils/15068 + * tic6xc-insn-formats.h (FLD): Add use of bitfield array. + Add 16-bit opcodes. + * tic6xc-opcode-table.h: Add 16-bit insns. + * tic6x.h: Add support for 16-bit insns. + +2013-03-21 Michael Schewe + + * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd + and mov.b/w/l Rs,@(d:32,ERd). + +2013-03-20 Alexis Deruelle + + PR gas/15082 + * tic6x-opcode-table.h: Rename mpydp's specific operand type macro + from ORREGD1324 to ORXREGD1324 and make it cross-path-able through + tic6x_operand_xregpair operand coding type. + Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' + opcode field, usu ORXREGD1324 for the src2 operand and remove the + TIC6X_FLAG_NO_CROSS. + +2013-03-20 Alexis Deruelle + + PR gas/15095 + * tic6x.h (enum tic6x_coding_method): Add + tic6x_coding_dreg_(msb|lsb) field coding type in order to encode + separately the msb and lsb of a register pair. This is needed to + encode the opcodes in the same way as TI assembler does. + * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp + and rsqrdp opcodes to use the new field coding types. + 2013-03-11 Kyrylo Tkachov * arm.h (CRC_EXT_ARMV8): New constant. @@ -870,7 +1294,7 @@ 2008-04-28 Adam Nemet - * mips.h (INSN_MACRO): Move it up to the the pinfo macros. + * mips.h (INSN_MACRO): Move it up to the pinfo macros. (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 2008-04-14 Edmar Wienskoski @@ -1644,7 +2068,7 @@ For older changes see ChangeLog-9103 -Copyright (C) 2004-2012 Free Software Foundation, Inc. +Copyright (C) 2004-2014 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright