X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=include%2Fopcode%2Faarch64.h;h=4cda1e079e03a70a808a6c03e36dcfe221751919;hb=eb5bbc482128b08d2ee8a2470951a74d8351146f;hp=813c36a465951a5337276d9a5308d98eb01680e9;hpb=73b605ec3f546ff5a1c343ae02e6322aaa451bcf;p=deliverable%2Fbinutils-gdb.git diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 813c36a465..4cda1e079e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1,6 +1,6 @@ /* AArch64 assembler/disassembler support. - Copyright (C) 2009-2018 Free Software Foundation, Inc. + Copyright (C) 2009-2019 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GNU Binutils. @@ -63,6 +63,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */ #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */ #define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */ +#define AARCH64_FEATURE_V8_6 0x00000002 /* ARMv8.6 processors. */ +#define AARCH64_FEATURE_BFLOAT16 0x00000004 /* Bfloat16 insns. */ /* Flag Manipulation insns. */ #define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL @@ -86,7 +88,15 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SSBS 0x800000000000ULL /* Memory Tagging Extension. */ #define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL +/* Transactional Memory Extension. */ +#define AARCH64_FEATURE_TME 0x2000000000000ULL +/* SVE2 instructions. */ +#define AARCH64_FEATURE_SVE2 0x000000010 +#define AARCH64_FEATURE_SVE2_AES 0x000000080 +#define AARCH64_FEATURE_SVE2_BITPERM 0x000000100 +#define AARCH64_FEATURE_SVE2_SM4 0x000000200 +#define AARCH64_FEATURE_SVE2_SHA3 0x000000400 /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -121,7 +131,9 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_SCXTNUM \ | AARCH64_FEATURE_ID_PFR2 \ | AARCH64_FEATURE_SSBS) - +#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \ + AARCH64_FEATURE_V8_6 \ + | AARCH64_FEATURE_BFLOAT16) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ @@ -184,6 +196,7 @@ enum aarch64_opnd AARCH64_OPND_Rm, /* Integer register as source. */ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ + AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ @@ -246,7 +259,9 @@ enum aarch64_opnd AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ + AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */ AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ + AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ AARCH64_OPND_BIT_NUM, /* Immediate. */ AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ @@ -284,7 +299,11 @@ enum aarch64_opnd the mnemonic name for LDUR/STUR instructions wherever there is no ambiguity. */ AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ + AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of + 16) immediate. */ AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ + AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of + 16) immediate. */ AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ @@ -322,6 +341,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [, , LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [, , LSL #2]. */ AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [, , LSL #3]. */ + AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.{, }]. */ AARCH64_OPND_SVE_ADDR_RZ, /* SVE [, Zm.D]. */ AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [, Zm.D, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [, Zm.D, LSL #2]. */ @@ -357,6 +377,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ + AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */ AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ @@ -375,8 +396,10 @@ enum aarch64_opnd AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ + AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */ AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ + AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */ AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ @@ -396,12 +419,15 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ + AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */ + AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ }; @@ -438,11 +464,13 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, - /* This type qualifier has a special meaning in that it means that 4 x 1 byte - are selected by the instruction. Other than that it has no difference - with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical - reasons and is an exception from normal AArch64 disassembly scheme. */ + /* These type qualifiers have a special meaning in that they mean 4 x 1 byte + or 2 x 2 byte are selected by the instruction. Other than that they have + no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely + for syntactical reasons and is an exception from normal AArch64 + disassembly scheme. */ AARCH64_OPND_QLF_S_4B, + AARCH64_OPND_QLF_S_2H, /* Qualifying an operand which is a SIMD vector register or a SIMD vector register list; indicating register shape. @@ -465,6 +493,10 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_P_Z, AARCH64_OPND_QLF_P_M, + /* Used in scaled signed immediate that are scaled by a Tag granule + like in stg, st2g, etc. */ + AARCH64_OPND_QLF_imm_tag, + /* Constraint on value. */ AARCH64_OPND_QLF_CR, /* CRn, CRm. */ AARCH64_OPND_QLF_imm_0_7, @@ -569,11 +601,19 @@ enum aarch64_insn_class sve_size_bhs, sve_size_bhsd, sve_size_hsd, + sve_size_hsd2, sve_size_sd, + sve_size_bh, + sve_size_sd2, + sve_size_13, + sve_shift_tsz_hsd, + sve_shift_tsz_bhsd, + sve_size_tsz_bhs, testbranch, cryptosm3, cryptosm4, dotproduct, + bfloat16, }; /* Opcode enumerators. */