X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=include%2Fopcode%2Faarch64.h;h=751d7bbaae5243f17ee2cb3d65818a46cdfd0b9b;hb=755b748fd9fbee8cad2e55535d23298e8ac76b15;hp=ea45a416e732cbf41045367fed7ac839dc85cdaf;hpb=c05e0c5af35ebbb1ca39bb1efffae2adecdfa253;p=deliverable%2Fbinutils-gdb.git diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ea45a416e7..751d7bbaae 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1,6 +1,6 @@ /* AArch64 assembler/disassembler support. - Copyright (C) 2009-2017 Free Software Foundation, Inc. + Copyright (C) 2009-2018 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GNU Binutils. @@ -37,6 +37,11 @@ extern "C" { typedef uint32_t aarch64_insn; /* The following bitmasks control CPU features. */ +#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */ +#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */ +#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */ +#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */ +#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */ #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ @@ -56,6 +61,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */ #define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */ #define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */ +#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */ /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -75,12 +81,16 @@ typedef uint32_t aarch64_insn; AARCH64_FEATURE_V8_3 \ | AARCH64_FEATURE_RCPC \ | AARCH64_FEATURE_COMPNUM) +#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \ + AARCH64_FEATURE_V8_4 \ + | AARCH64_FEATURE_DOTPROD \ + | AARCH64_FEATURE_F16_FML) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ /* CPU-specific features. */ -typedef unsigned long aarch64_feature_set; +typedef unsigned long long aarch64_feature_set; #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ ((~(CPU) & (FEAT)) == 0) @@ -159,6 +169,7 @@ enum aarch64_opnd AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ + AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ @@ -167,6 +178,8 @@ enum aarch64_opnd AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ + AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when + qualifier is S_H. */ AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single @@ -177,6 +190,7 @@ enum aarch64_opnd AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ + AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ @@ -191,6 +205,7 @@ enum aarch64_opnd AARCH64_OPND_IMMS, /* Immediate # in e.g. BFM. */ AARCH64_OPND_WIDTH, /* Immediate # in e.g. BFI. */ AARCH64_OPND_IMM, /* Immediate. */ + AARCH64_OPND_IMM_2, /* Immediate. */ AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ @@ -234,6 +249,7 @@ enum aarch64_opnd AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ + AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ AARCH64_OPND_SYSREG, /* System register operand. */ @@ -258,6 +274,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [, #*2]. */ AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [, #*4]. */ AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [, #*8]. */ + AARCH64_OPND_SVE_ADDR_R, /* SVE []. */ AARCH64_OPND_SVE_ADDR_RR, /* SVE [, ]. */ AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [, , LSL #1]. */ AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [, , LSL #2]. */ @@ -346,6 +363,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ }; /* Qualifier constrains an operand. It either specifies a variant of an @@ -381,6 +399,11 @@ enum aarch64_opnd_qualifier AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, + /* This type qualifier has a special meaning in that it means that 4 x 1 byte + are selected by the instruction. Other than that it has no difference + with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical + reasons and is an exception from normal AArch64 disassembly scheme. */ + AARCH64_OPND_QLF_S_4B, /* Qualifying an operand which is a SIMD vector register or a SIMD vector register list; indicating register shape. @@ -388,6 +411,7 @@ enum aarch64_opnd_qualifier a use is only for the ease of operand encoding/decoding and qualifier sequence matching; such a use should not be applied widely; use the value constraint qualifiers for immediate operands wherever possible. */ + AARCH64_OPND_QLF_V_4B, AARCH64_OPND_QLF_V_8B, AARCH64_OPND_QLF_V_16B, AARCH64_OPND_QLF_V_2H, @@ -508,6 +532,8 @@ enum aarch64_insn_class sve_size_hsd, sve_size_sd, testbranch, + cryptosm3, + cryptosm4, dotproduct, }; @@ -615,6 +641,16 @@ enum aarch64_op OP_TOTAL_NUM, /* Pseudo. */ }; +/* Error types. */ +enum err_type +{ + ERR_OK, + ERR_UND, + ERR_UNP, + ERR_NYI, + ERR_NR_ENTRIES +}; + /* Maximum number of operands an instruction can have. */ #define AARCH64_MAX_OPND_NUM 6 /* Maximum number of qualifier sequences an instruction can have. */ @@ -636,6 +672,13 @@ empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) return TRUE; } +/* Forward declare error reporting type. */ +typedef struct aarch64_operand_error aarch64_operand_error; +/* Forward declare instruction sequence type. */ +typedef struct aarch64_instr_sequence aarch64_instr_sequence; +/* Forward declare instruction definition. */ +typedef struct aarch64_inst aarch64_inst; + /* This structure holds information for a particular opcode. */ struct aarch64_opcode @@ -674,14 +717,19 @@ struct aarch64_opcode aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; /* Flags providing information about this instruction */ - uint32_t flags; + uint64_t flags; + + /* Extra constraints on the instruction that the verifier checks. */ + uint32_t constraints; /* If nonzero, this operand and operand 0 are both registers and are required to have the same register number. */ unsigned char tied_operand; /* If non-NULL, a function to verify that a given instruction is valid. */ - bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); + enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn, + bfd_vma, bfd_boolean, aarch64_operand_error *, + struct aarch64_instr_sequence *); }; typedef struct aarch64_opcode aarch64_opcode; @@ -741,7 +789,22 @@ extern aarch64_opcode aarch64_opcode_table[]; #define F_LSE_SZ (1 << 27) /* Require an exact qualifier match, even for NIL qualifiers. */ #define F_STRICT (1ULL << 28) -/* Next bit is 29. */ +/* This system instruction is used to read system registers. */ +#define F_SYS_READ (1ULL << 29) +/* This system instruction is used to write system registers. */ +#define F_SYS_WRITE (1ULL << 30) +/* This instruction has an extra constraint on it that imposes a requirement on + subsequent instructions. */ +#define F_SCAN (1ULL << 31) +/* Next bit is 32. */ + +/* Instruction constraints. */ +/* This instruction has a predication constraint on the instruction at PC+4. */ +#define C_SCAN_MOVPRFX (1U << 0) +/* This instruction's operation width is determined by the operand with the + largest element size. */ +#define C_MAX_ELEM (1U << 1) +/* Next bit is 2. */ static inline bfd_boolean alias_opcode_p (const aarch64_opcode *opcode) @@ -933,9 +996,17 @@ struct aarch64_opnd_info unsigned preind : 1; /* Pre-indexed. */ unsigned postind : 1; /* Post-indexed. */ } addr; + + struct + { + /* The encoding of the system register. */ + aarch64_insn value; + + /* The system register flags. */ + uint32_t flags; + } sysreg; + const aarch64_cond *cond; - /* The encoding of the system register. */ - aarch64_insn sysreg; /* The encoding of the PSTATE field. */ aarch64_insn pstatefield; const aarch64_sys_ins_reg *sysins_op; @@ -1069,16 +1140,30 @@ struct aarch64_operand_error int index; const char *error; int data[3]; /* Some data for extra information. */ + bfd_boolean non_fatal; }; -typedef struct aarch64_operand_error aarch64_operand_error; +/* AArch64 sequence structure used to track instructions with F_SCAN + dependencies for both assembler and disassembler. */ +struct aarch64_instr_sequence +{ + /* The instruction that caused this sequence to be opened. */ + aarch64_inst *instr; + /* The number of instructions the above instruction allows to be kept in the + sequence before an automatic close is done. */ + int num_insns; + /* The instructions currently added to the sequence. */ + aarch64_inst **current_insns; + /* The number of instructions already in the sequence. */ + int next_insn; +}; /* Encoding entrypoint. */ extern int aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, aarch64_insn *, aarch64_opnd_qualifier_t *, - aarch64_operand_error *); + aarch64_operand_error *, aarch64_instr_sequence *); extern const aarch64_opcode * aarch64_replace_opcode (struct aarch64_inst *, @@ -1093,7 +1178,8 @@ aarch64_get_opcode (enum aarch64_op); /* Generate the string representation of an operand. */ extern void aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, - const aarch64_opnd_info *, int, int *, bfd_vma *); + const aarch64_opnd_info *, int, int *, bfd_vma *, + char **); /* Miscellaneous interface. */ @@ -1113,8 +1199,9 @@ aarch64_stack_pointer_p (const aarch64_opnd_info *); extern int aarch64_zero_register_p (const aarch64_opnd_info *); -extern int -aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); +extern enum err_type +aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean, + aarch64_operand_error *errors); /* Given an operand qualifier, return the expected data element size of a qualified operand. */