X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=include%2Fopcode%2Fmips.h;h=bf0f11573f111baf0ba4160abcd5a984094af6ac;hb=b015e599c772eeb5f818d710119ee43e7df0feff;hp=ef81bbe2bfec939646dc50ad7d67031fa7b1bf86;hpb=4e45246814db0733e986df0bccf8c165d2880f79;p=deliverable%2Fbinutils-gdb.git

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index ef81bbe2bf..bf0f11573f 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -212,6 +212,10 @@
 #define	OP_OP_SDC2		0x3e
 #define	OP_OP_SDC3		0x3f	/* a.k.a. sd */
 
+/* MIPS VIRT ASE */
+#define OP_MASK_CODE10		0x3ff
+#define OP_SH_CODE10		11
+
 /* Values in the 'VSEL' field.  */
 #define MDMX_FMTSEL_IMM_QH	0x1d
 #define MDMX_FMTSEL_IMM_OB	0x1e
@@ -255,8 +259,6 @@
    of the operand handling in GAS.  The fields below only exist
    in the microMIPS encoding, so define each one to have an empty
    range.  */
-#define OP_MASK_CODE10		0
-#define OP_SH_CODE10		0
 #define OP_MASK_TRAP		0
 #define OP_SH_TRAP		0
 #define OP_MASK_OFFSET10	0
@@ -486,6 +488,9 @@ struct mips_opcode
    "~" 12 bit offset (OP_*_OFFSET12)
    "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
 
+   VIRT ASE usage:
+   "+J" 10-bit hypcall code (OP_*CODE10)
+
    UDI immediates:
    "+1" UDI immediate bits 6-10
    "+2" UDI immediate bits 6-15
@@ -528,7 +533,7 @@ struct mips_opcode
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
    "1234"
-   "ABCDEFGHIPQSTXZ"
+   "ABCDEFGHIJPQSTXZ"
    "abcpstxz"
 */
 
@@ -726,7 +731,7 @@ static const unsigned int mips_isa_table[] =
 #define INSN_OCTEON2		  0x00000100
 
 /* Masks used for MIPS-defined ASEs.  */
-#define INSN_ASE_MASK		  0x3c00f010
+#define INSN_ASE_MASK		  0x3c00f0d0
 
 /* DSP ASE */ 
 #define INSN_DSP                  0x00001000
@@ -735,6 +740,10 @@ static const unsigned int mips_isa_table[] =
 /* MIPS R5900 instruction */
 #define INSN_5900                 0x00004000
 
+/* Virtualization ASE */
+#define INSN_VIRT		  0x00000080
+#define INSN_VIRT64		  0x00000040
+
 /* MIPS-3D ASE */
 #define INSN_MIPS3D               0x00008000