X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=0c232f7fa4c8fb7767395793ca3b07f80e8beb70;hb=67ce483baa43121a17195efe4b14a183e9fd8232;hp=0586af694cf3f79504fc2ec962e173ee96d96068;hpb=06cfb1c89510d08217da8b3ccea05ecd4cdb5bc6;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0586af694c..0c232f7fa4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,502 @@ +2018-07-24 Alan Modra + + PR 23430 + * or1k-desc.h: Regenerate. + +2018-07-24 Jan Beulich + + * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd, + vcvtusi2ss, and vcvtusi2sd. + * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss): + Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms. + * i386-tbl.h: Re-generate. + +2018-07-23 Claudiu Zissulescu + + * arc-opc.c (extract_w6): Fix extending the sign. + +2018-07-23 Claudiu Zissulescu + + * arc-tbl.h (vewt): Allow it for ARC EM family. + +2018-07-23 Alan Modra + + PR 23419 + * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended + opcode variants for mtspr/mfspr encodings. + +2018-07-20 Chenghua Xu + Maciej W. Rozycki + + * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and + loongson3a descriptors. + (parse_mips_ase_option): Handle -M loongson-mmi option. + (print_mips_disassembler_options): Document -M loongson-mmi. + * mips-opc.c (LMMI): New macro. + (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI + instructions. + +2018-07-19 Jan Beulich + + * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, + vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop + IgnoreSize and [XYZ]MMword where applicable. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl (vfpclasspd, vfpclassps): Fold. + (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord. + (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord. + (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ, + AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and + VPCLMULQDQ templates into their respective AVX512VL counterparts + where possible, using Disp8ShiftVL and CheckRegSize instead of + Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512DQ templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512BW templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512CD templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.h (DISP8_SHIFT_VL): New. + * i386-opc.tbl (Disp8ShiftVL): Define. + (various): Fold AVX512VL templates into their respective + AVX512F counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * Makefile.am: Change dependencies and rule for + $(srcdir)/i386-init.h. + * Makefile.in: Re-generate. + * i386-gen.c (process_i386_opcodes): New local variable + "marker". Drop opening of input file. Recognize marker and line + number directives. + * i386-opc.tbl (OPCODE_I386_H): Define. + (i386-opc.h): Include it. + (None): Undefine. + +2018-07-18 H.J. Lu + + PR gas/23418 + * i386-opc.h (Byte): Update comments. + (Word): Likewise. + (Dword): Likewise. + (Fword): Likewise. + (Qword): Likewise. + (Tbyte): Likewise. + (Xmmword): Likewise. + (Ymmword): Likewise. + (Zmmword): Likewise. + * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and + vcvttps2uqq. + * i386-tbl.h: Regenerated. + +2018-07-12 Sudakshina Das + + * aarch64-tbl.h (aarch64_opcode_table): Add entry for + ssbb and pssbb and update dsb flags to F_HAS_ALIAS. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2018-07-12 Tamar Christina + + PR binutils/23192 + * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, + mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, + umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, + sqdmulh, sqrdmulh): Use Em16. + +2018-07-11 Sudakshina Das + + * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move + csdb together with them. + (thumb32_opcodes): Likewise. + +2018-07-11 Jan Beulich + + * i386-opc.tbl (monitor, monitorx): Add 64-bit template + requiring 32-bit registers as operands 2 and 3. Improve + comments. + (mwait, mwaitx): Fold templates. Improve comments. + OPERAND_TYPE_INOUTPORTREG. + * i386-tbl.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-gen.c (operand_type_init): Remove + OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of + OPERAND_TYPE_INOUTPORTREG. + * i386-init.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-opc.tbl (wrssd, wrussd): Add Dword. + (wrssq, wrussq): Add Qword. + * i386-tbl.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-opc.h: Rename OTMax to OTNum. + (OTNumOfUints): Adjust calculation. + (OTUnused): Directly alias to OTNum. + +2018-07-09 Maciej W. Rozycki + + * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to + `reg_xys'. + (lea_reg_xys): Likewise. + (print_insn_loop_primitive): Rename `reg' local variable to + `reg_dxy'. + +2018-07-06 Tamar Christina + + PR binutils/23242 + * aarch64-tbl.h (ldarh): Fix disassembly mask. + +2018-07-06 Tamar Christina + + PR binutils/23369 + * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, + vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. + +2018-07-02 Maciej W. Rozycki + + PR tdep/8282 + * mips-dis.c (mips_option_arg_t): New enumeration. + (mips_options): New variable. + (disassembler_options_mips): New function. + (print_mips_disassembler_options): Reimplement in terms of + `disassembler_options_mips'. + * arm-dis.c (disassembler_options_arm): Adapt to using the + `disasm_options_and_args_t' structure. + * ppc-dis.c (disassembler_options_powerpc): Likewise. + * s390-dis.c (disassembler_options_s390): Likewise. + +2018-07-02 Thomas Preud'homme + + * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in + expected result. + * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. + * testsuite/ld-arm/tls-longplt-lib.d: Likewise. + * testsuite/ld-arm/tls-longplt.d: Likewise. + +2018-06-29 Tamar Christina + + PR binutils/23192 + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. + * aarch64-opc.c (operand_general_constraint_met_p, + aarch64_print_operand): Likewise. + * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, + smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, + fmlal2, fmlsl2. + (AARCH64_OPERANDS): Add Em2. + +2018-06-26 Nick Clifton + + * po/uk.po: Updated Ukranian translation. + * po/de.po: Updated German translation. + * po/pt_BR.po: Updated Brazilian Portuguese translation. + +2018-06-26 Nick Clifton + + * nfp-dis.c: Fix spelling mistake. + +2018-06-24 Nick Clifton + + * configure: Regenerate. + * po/opcodes.pot: Regenerate. + +2018-06-24 Nick Clifton + + 2.31 branch created. + +2018-06-19 Tamar Christina + + * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + +2018-06-21 Maciej W. Rozycki + + * mips-dis.c (print_mips_disassembler_options): Fix a typo in + `-M ginv' option description. + +2018-06-20 Sebastian Huber + + PR gas/23305 + * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for + la and lla. + +2018-06-19 Simon Marchi + + * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11. + * configure.ac: Remove AC_PREREQ. + * Makefile.in: Re-generate. + * aclocal.m4: Re-generate. + * configure: Re-generate. + +2018-06-14 Faraz Shahbazker + + * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and + mips64r6 descriptors. + (parse_mips_ase_option): Handle -Mginv option. + (print_mips_disassembler_options): Document -Mginv. + * mips-opc.c (decode_mips_operand) <+\>: New operand format. + (GINV): New macro. + (mips_opcodes): Define ginvi and ginvt. + +2018-06-13 Scott Egerton + Faraz Shahbazker + + * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. + * mips-opc.c (CRC, CRC64): New macros. + (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, + crc32cb, crc32ch and crc32cw for CRC. Define crc32d and + crc32cd for CRC64. + +2018-06-08 Egeyar Bagcioglu + + PR 20319 + * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV. + (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV. + +2018-06-06 Alan Modra + + * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after + setjmp. Move init for some other vars later too. + +2018-06-04 Max Filippov + + * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes. + (dis_private): Add new fields for property section tracking. + (xtensa_coalesce_insn_tables, xtensa_find_table_entry) + (xtensa_instruction_fits): New functions. + (fetch_data): Bump minimal fetch size to 4. + (print_insn_xtensa): Make struct dis_private static. + Load and prepare property table on section change. + Don't disassemble literals. Don't disassemble instructions that + cross property table boundaries. + +2018-06-01 H.J. Lu + + * configure: Regenerated. + +2018-06-01 Jan Beulich + + * i386-opc.tbl (mov, movq): Fold to/from SReg* forms. + * i386-tbl.h: Re-generate. + +2018-06-01 Jan Beulich + + * i386-opc.tbl (sldt, str): Add NoRex64. + * i386-tbl.h: Re-generate. + +2018-06-01 Jan Beulich + + * i386-opc.tbl (invpcid): Add Oword. + * i386-tbl.h: Re-generate. + +2018-06-01 Alan Modra + + * sysdep.h (_bfd_error_handler): Don't declare. + * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here. + * rl78-decode.opc: Likewise. + * msp430-decode.c: Regenerate. + * rl78-decode.c: Regenerate. + +2018-05-30 Amit Pawar + + * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS. + * i386-init.h : Regenerated. + +2018-05-25 Alan Modra + + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2018-05-21 Peter Bergner + + * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, + insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. + (insert_bab, extract_bab, insert_btab, extract_btab, + insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. + (BAT, BBA VBA RBS XB6S): Delete macros. + (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. + (BB, BD, RBX, XC6): Update for new macros. + (powerpc_opcodes) : Likewise. + * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. + +2018-05-18 John Darrington + + * Makefile.am: Add support for s12z architecture. + * configure.ac: Likewise. + * disassemble.c: Likewise. + * disassemble.h: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * s12z-dis.c: New file. + * s12z.h: New file. + +2018-05-18 Alan Modra + + * nfp-dis.c: Don't #include libbfd.h. + (init_nfp3200_priv): Use bfd_get_section_contents. + (nit_nfp6000_mecsr_sec): Likewise. + +2018-05-17 Nick Clifton + + * po/zh_CN.po: Updated simplified Chinese translation. + +2018-05-16 Tamar Christina + + PR binutils/23109 + * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot. + * aarch64-dis-2.c: Regenerate. + +2018-05-15 Tamar Christina + + PR binutils/21446 + * aarch64-asm.c (opintl.h): Include. + (aarch64_ins_sysreg): Enforce read/write constraints. + * aarch64-dis.c (aarch64_ext_sysreg): Likewise. + * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. + (F_REG_READ, F_REG_WRITE): New. + * aarch64-opc.c (aarch64_print_operand): Generate notes for + AARCH64_OPND_SYSREG. + (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. + (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, + mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, + id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, + id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, + id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, + mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, + id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, + id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, + id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, + csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, + rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, + mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, + mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, + pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. + * aarch64-tbl.h (aarch64_opcode_table): Add constraints to + msr (F_SYS_WRITE), mrs (F_SYS_READ). + +2018-05-15 Tamar Christina + + PR binutils/21446 + * aarch64-dis.c (no_notes: New. + (parse_aarch64_dis_option): Support notes. + (aarch64_decode_insn, print_operands): Likewise. + (print_aarch64_disassembler_options): Document notes. + * aarch64-opc.c (aarch64_print_operand): Support notes. + +2018-05-15 Tamar Christina + + PR binutils/21446 + * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean + and take error struct. + * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, + aarch64_ins_reglist, aarch64_ins_ldst_reglist, + aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, + aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, + aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, + aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, + aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, + aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, + aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, + aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, + aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, + aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, + aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, + aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, + aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, + aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, + aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, + aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, + aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, + aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, + aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, + aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, + aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, + aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, + aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. + * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. + * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, + aarch64_ext_reglist, aarch64_ext_ldst_reglist, + aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, + aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, + aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, + aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, + aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, + aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, + aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, + aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, + aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, + aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, + aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, + aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, + aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, + aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, + aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, + aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, + aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, + aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, + aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, + aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, + aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, + aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, + aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. + (determine_disassembling_preference, aarch64_decode_insn, + print_insn_aarch64_word, print_insn_data): Take errors struct. + (print_insn_aarch64): Use errors. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-gen.c (print_operand_inserter): Use errors and change type to + boolean in aarch64_insert_operan. + (print_operand_extractor): Likewise. + * aarch64-opc.c (aarch64_print_operand): Use sysreg struct. + +2018-05-15 Francois H. Theron + + * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma. + 2018-05-09 H.J. Lu * i386-opc.tbl: Remove Disp from movidir{i,64b}.