X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=2e970e532915fb023dd5b8df656c56439c75e4c3;hb=5e377ed2f2fe756468a14385ad7364053d637025;hp=21b8bcf67599b0042a2c6360c06b79aaf1840f27;hpb=e358a062c9ec667b888e307c333fe72a64ba4d6a;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 21b8bcf675..2e970e5329 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,188 @@ +Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Fix typo/thinko in "eret" instruction. + +start-sanitize-r5900 +Mon Jul 28 22:07:14 1997 Andrew Cagney + + * mips-opc.c: Fix coding of mtsa. + +start-sanitize-r5900 +Thu Jul 24 13:03:26 1997 Doug Evans + + * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. + Make array const. + * sparc-dis.c (sorted_opcodes): New static local. + (struct opcode_hash): `opcode' is pointer to const element. + (build_hash): First arg is now table of sorted pointers. + (print_insn_sparc): Sort opcodes by sorting table of pointers. + (compare_opcodes): Update. + +Tue Jul 15 12:05:23 1997 Doug Evans + + * cgen-opc.c: #include . + (hash_keyword_name): New arg `case_sensitive_p'. Callers updated. + Handle case insensitive hashing. + (hash_keyword_value): Change type of `value' to unsigned int. + +Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c (mips_builtin_opcodes): If an insn uses single + precision FP, mark it as such. Likewise for double precision + FP. Mark ISA1 insns. Consolidate duplicate opcodes where + possible. +start-sanitize-r5900 + (mips_builtin_opcodes): Remove non-existant r5900 instructions +end-sanitize-r5900 + +start-sanitize-r5900 +Thu Jun 26 16:20:27 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and + "pexew" as synonyms for "pintoh", "pexoh", "pexow". + +end-sanitize-5900 +Wed Jun 25 15:25:57 1997 Felix Lee + + * ppc-opc.c (extract_nsi): make unsigned expression signed before + negating it. + (UNUSED): remove one level of parens, so MSVC doesn't choke on + nesting depth when all the macros are expanded. + +Tue Jun 17 17:02:17 1997 Ian Lance Taylor + + * sparc-opc.c: The fcmp v9a instructions take an integer register + as a destination, not a floating point register. From Christian + Kuehnke . + +Mon Jun 16 14:13:18 1997 Ian Lance Taylor + + * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() + syntax. From Roman Hodek + . + + * i386-dis.c (twobyte_has_modrm): Fix pand. + +Mon Jun 16 14:08:38 1997 Michael Taylor + + * i386-dis.c (dis386_twobyte): Fix pand and pandn. + +Tue Jun 10 11:26:47 1997 H.J. Lu + + * arm-dis.c: Add prototypes for arm_decode_shift and + print_insn_arm. + +Mon Jun 2 11:39:04 1997 Gavin Koch + + * mips-opc.c: Add r3900 insns. + +Tue May 27 15:55:44 1997 Ian Lance Taylor + + * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't + print delay slot instructions on the same line. When using a PC + relative load, add a comment with the value being loaded if it can + be obtained. + +Tue May 27 11:02:08 1997 Alan Modra + + * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl + to pushS/popS for segment regs and byte constant so that + pushw/popw printed when in 16 bit data mode. + + * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to + print cbtw, cwtd in 16 bit data mode. + * i386-dis.c (putop): extra case W to support above. + + * i386-dis.c (print_insn_x86): print addr32 prefix when given + address size prefix in 16 bit address mode. + +Fri May 23 16:47:23 1997 Ian Lance Taylor + + * sh-dis.c: Reindent. Rename local variable fprintf to + fprintf_fn. + +Thu May 22 14:06:02 1997 Doug Evans + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. + +Tue May 20 11:26:27 1997 Gavin Koch + + * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new + field membership. + * mips16-opc.c (mip16_opcodes): same. + +Mon May 12 15:10:53 1997 Jim Wilson + + * m68k-opc.c (moveb): Change $d to %d. + +Mon May 5 14:28:41 1997 Ian Lance Taylor + + * i386-dis.c: (dis386_twobyte): Add MMX instructions. + (twobyte_has_modrm): Likewise. + (grps): Likewise. + (OP_MMX, OP_EM, OP_MS): New static functions. + + * i386-dis.c: Revert patch of April 4. The output now matches + what gcc generates. + +Fri May 2 12:48:37 1997 Doug Evans + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead + of $simm16. + +Thu May 1 15:34:15 1997 Doug Evans + + * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU. + +Tue Apr 15 12:40:08 1997 Ian Lance Taylor + + * Makefile.in (install): Depend upon installdirs. + (installdirs): New target. + +Mon Apr 14 12:13:51 1997 Ian Lance Taylor + + From Thomas Graichen : + * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub. + * configure: Rebuild. + +Sun Apr 13 17:50:41 1997 Doug Evans + + * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. + Delete string{,s}.h support. + +Thu Apr 10 14:44:56 1997 Doug Evans + + * cgen-asm.c (cgen_parse_operand_fn): New global. + (cgen_parse_{{,un}signed_integer,address}): Update call to + cgen_parse_operand_fn. + (cgen_init_parse_operand): New function. + * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed + from cgen_asm_init_parse. + (m32r_cgen_assemble_insn): New operand `errmsg'. + Delete call to as_bad, return error message to caller. + (m32r_cgen_asm_hash_keywords): #if 0 out. + +Wed Apr 9 12:05:25 1997 Andreas Schwab + + * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register, + not data register. + [case 'J']: Fix typo in register name. + +Mon Apr 7 16:48:22 1997 Ian Lance Taylor + + * configure.in: Substitute SHLIB_LIBS. + * configure: Rebuild. + * Makefile.in (SHLIB_LIBS): New variable. + ($(SHLIB)): Use $(SHLIB_LIBS). + +Mon Apr 7 11:45:44 1997 Doug Evans + + * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. + + * cgen-opc.c (hash_keyword_name): Improve algorithm. + + * disassemble.c (disassembler): Handle m32r. + Fri Apr 4 12:29:38 1997 Doug Evans * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files.