X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=34b2b62d51facbc6a8efbfc36fd04d0fb342711b;hb=4a3e3e228280ebbd6320743c1bc2f1401e70300c;hp=3c74fbf3d870be9fe33718b8e14024ede66c9353;hpb=5b316d90e4ec9845a890fd21ad86cf1043fb2ca3;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3c74fbf3d8..34b2b62d51 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,245 @@ +2020-11-09 Przemyslaw Wirkus + + * aarch64-opc.c: Add ACCDATA_EL1 system register + +2020-11-09 Przemyslaw Wirkus + + * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64 + print. + * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with + Rt_ls64 operands. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-11-06 Przemyslaw Wirkus + + * aarch64-tbl.h (PAC): Handle for PAC feature. + (PAC_INSN): New PAC instruction. + (struct aarch64_opcode): Move PAC instructions from V8_3_INSN to + PAC_INSN. + +2020-11-04 Przemyslaw Wirkus + + * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1, + ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1. + +2020-11-03 Przemyslaw Wirkus + + * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores. + (LS64): Handler with +ls64 feature flags. + (_LS64_INSN): New instruction group macro. + (struct aarch64_opcode): Add LS64 instructions. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-30 Przemyslaw Wirkus + + * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-27 Przemyslaw Wirkus + + * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out. + * aarch64-tbl.h (CSRE): New CSRE feature handler. + (_CSRE_INSN): New CSRE instruction type. + (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-27 Przemyslaw Wirkus + + * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding + and operand description. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-26 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16. + +2020-10-26 Cooper Qu + + * csky-dis.c (csky_output_operand): Add handler for + OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. + * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum. + (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add + some instructions for VDSPV1. + +2020-10-26 Lili Cui + + * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix. + +2020-10-23 Przemyslaw Wirkus + + * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. + * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter + ins_barrier_dsb_nx. + * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. + * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor + ext_barrier_dsb_nx. + * aarch64-opc.c (aarch64_print_operand): New options table + aarch64_barrier_dsb_nxs_options. + * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. + * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier + Armv8.7-a instruction. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-22 H.J. Lu + + * po/es.po: Remove the duplicated entry. + +2020-10-20 Dr. David Alan Gilbert + + * po/es.po: Fix printf format. + +2020-10-20 Ganesh Gopalasubramanian + + * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb. + * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS, + CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS. + Add CPU_ZNVER3_FLAGS. + (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. + * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. + * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate, + rmpupdate, rmpadjust. + * i386-init.h: Re-generated. + * i386-tbl.h: Re-generated. + +2020-10-16 Lili Cui + + * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix + and move it from cpu_flags to opcode_modifiers. + Use VexW0 and VexVVVV in the AVX-VNNI instructions. + * i386-gen.c: Likewise. + * i386-opc.h: Likewise. + * i386-opc.h: Likewise. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2020-10-16 Przemyslaw Wirkus + + * aarch64-tbl.h (ARMV8_7): New macro. + +2020-10-14 H.J. Lu + Lili Cui + + * i386-dis.c (PREFIX_VEX_0F3850): New. + (PREFIX_VEX_0F3851): Likewise. + (PREFIX_VEX_0F3852): Likewise. + (PREFIX_VEX_0F3853): Likewise. + (VEX_W_0F3850_P_2): Likewise. + (VEX_W_0F3851_P_2): Likewise. + (VEX_W_0F3852_P_2): Likewise. + (VEX_W_0F3853_P_2): Likewise. + (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851, + PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853. + (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2, + VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2. + (putop): Add support for "XV" to print "{vex3}" pseudo prefix. + * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in + CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and + CPU_ANY_AVX_VNNI_FLAGS. + (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX. + * i386-opc.h (CpuAVX_VNNI): New. + (CpuVEX_PREFIX): Likewise. + (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix. + * i386-opc.tbl: Add Intel AVX VNNI instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2020-10-14 Lili Cui + H.J. Lu + + * i386-dis.c (PREFIX_0F3A0F): New. + (MOD_0F3A0F_PREFIX_1): Likewise. + (REG_0F3A0F_PREFIX_1_MOD_3): Likewise. + (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise. + (prefix_table): Add PREFIX_0F3A0F. + (mod_table): Add MOD_0F3A0F_PREFIX_1. + (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3. + (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0. + * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS, + CPU_ANY_HRESET_FLAGS. + (cpu_flags): Add CpuHRESET. + (output_i386_opcode): Allow 4 byte base_opcode. + * i386-opc.h (enum): Add CpuHRESET. + (i386_cpu_flags): Add cpuhreset. + * i386-opc.tbl: Add Intel HRESET instruction. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-10-14 Lili Cui + + * i386-dis.c (enum): Add + PREFIX_MOD_3_0F01_REG_5_RM_4, + PREFIX_MOD_3_0F01_REG_5_RM_5, + PREFIX_MOD_3_0F01_REG_5_RM_6, + PREFIX_MOD_3_0F01_REG_5_RM_7, + X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, + X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, + X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, + X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, + X86_64_0FC7_REG_6_MOD_3_PREFIX_1. + (prefix_table): New instructions (see prefixes above). + (rm_table): Likewise + * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS, + CPU_ANY_UINTR_FLAGS. + (cpu_flags): Add CpuUINTR. + * i386-opc.h (enum): Add CpuUINTR. + (i386_cpu_flags): Add cpuuintr. + * i386-opc.tbl: Add UINTR insns. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-10-14 H.J. Lu + + * i386-gen.c (process_i386_opcode_modifier): Return 1 for + non-VEX/EVEX/prefix encoding. + (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode + has a prefix byte. + * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX + base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3. + * i386-tbl.h: Regenerated. + +2020-10-13 H.J. Lu + + * i386-gen.c (opcode_modifiers): Replace VexOpcode with + OpcodePrefix. + * i386-opc.h (VexOpcode): Renamed to ... + (OpcodePrefix): This. + (PREFIX_NONE): New. + (PREFIX_0X66): Likewise. + (PREFIX_0XF2): Likewise. + (PREFIX_0XF3): Likewise. + * i386-opc.tbl (Prefix_0X66): New. + (Prefix_0XF2): Likewise. + (Prefix_0XF3): Likewise. + Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd. + Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq. + * i386-tbl.h: Regenerated. + +2020-10-08 Przemyslaw Wirkus + + * aarch64-opc.c: Add BRBE system registers. + +2020-10-08 Przemyslaw Wirkus + + * aarch64-opc.c: New CSRE system registers defined. + +2020-10-05 Samanta Navarro + + * cgen-asm.c: Fix spelling mistakes. + * cgen-dis.c: Fix spelling mistakes. + * tic30-dis.c: Fix spelling mistakes. + 2020-10-05 H.J. Lu PR binutils/26704