X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=34b2b62d51facbc6a8efbfc36fd04d0fb342711b;hb=4a3e3e228280ebbd6320743c1bc2f1401e70300c;hp=af4dac6105dbee5704602480a34cf2277f21811b;hpb=4449c81a85eef44b10532032207e8db5858c00ee;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index af4dac6105..34b2b62d51 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,602 @@ +2020-11-09 Przemyslaw Wirkus + + * aarch64-opc.c: Add ACCDATA_EL1 system register + +2020-11-09 Przemyslaw Wirkus + + * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64 + print. + * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with + Rt_ls64 operands. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-11-06 Przemyslaw Wirkus + + * aarch64-tbl.h (PAC): Handle for PAC feature. + (PAC_INSN): New PAC instruction. + (struct aarch64_opcode): Move PAC instructions from V8_3_INSN to + PAC_INSN. + +2020-11-04 Przemyslaw Wirkus + + * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1, + ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1. + +2020-11-03 Przemyslaw Wirkus + + * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores. + (LS64): Handler with +ls64 feature flags. + (_LS64_INSN): New instruction group macro. + (struct aarch64_opcode): Add LS64 instructions. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-30 Przemyslaw Wirkus + + * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-27 Przemyslaw Wirkus + + * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out. + * aarch64-tbl.h (CSRE): New CSRE feature handler. + (_CSRE_INSN): New CSRE instruction type. + (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-27 Przemyslaw Wirkus + + * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding + and operand description. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-26 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16. + +2020-10-26 Cooper Qu + + * csky-dis.c (csky_output_operand): Add handler for + OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. + * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum. + (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add + some instructions for VDSPV1. + +2020-10-26 Lili Cui + + * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix. + +2020-10-23 Przemyslaw Wirkus + + * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. + * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter + ins_barrier_dsb_nx. + * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. + * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor + ext_barrier_dsb_nx. + * aarch64-opc.c (aarch64_print_operand): New options table + aarch64_barrier_dsb_nxs_options. + * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. + * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier + Armv8.7-a instruction. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-10-22 H.J. Lu + + * po/es.po: Remove the duplicated entry. + +2020-10-20 Dr. David Alan Gilbert + + * po/es.po: Fix printf format. + +2020-10-20 Ganesh Gopalasubramanian + + * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb. + * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS, + CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS. + Add CPU_ZNVER3_FLAGS. + (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. + * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. + * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate, + rmpupdate, rmpadjust. + * i386-init.h: Re-generated. + * i386-tbl.h: Re-generated. + +2020-10-16 Lili Cui + + * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix + and move it from cpu_flags to opcode_modifiers. + Use VexW0 and VexVVVV in the AVX-VNNI instructions. + * i386-gen.c: Likewise. + * i386-opc.h: Likewise. + * i386-opc.h: Likewise. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2020-10-16 Przemyslaw Wirkus + + * aarch64-tbl.h (ARMV8_7): New macro. + +2020-10-14 H.J. Lu + Lili Cui + + * i386-dis.c (PREFIX_VEX_0F3850): New. + (PREFIX_VEX_0F3851): Likewise. + (PREFIX_VEX_0F3852): Likewise. + (PREFIX_VEX_0F3853): Likewise. + (VEX_W_0F3850_P_2): Likewise. + (VEX_W_0F3851_P_2): Likewise. + (VEX_W_0F3852_P_2): Likewise. + (VEX_W_0F3853_P_2): Likewise. + (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851, + PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853. + (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2, + VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2. + (putop): Add support for "XV" to print "{vex3}" pseudo prefix. + * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in + CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and + CPU_ANY_AVX_VNNI_FLAGS. + (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX. + * i386-opc.h (CpuAVX_VNNI): New. + (CpuVEX_PREFIX): Likewise. + (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix. + * i386-opc.tbl: Add Intel AVX VNNI instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2020-10-14 Lili Cui + H.J. Lu + + * i386-dis.c (PREFIX_0F3A0F): New. + (MOD_0F3A0F_PREFIX_1): Likewise. + (REG_0F3A0F_PREFIX_1_MOD_3): Likewise. + (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise. + (prefix_table): Add PREFIX_0F3A0F. + (mod_table): Add MOD_0F3A0F_PREFIX_1. + (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3. + (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0. + * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS, + CPU_ANY_HRESET_FLAGS. + (cpu_flags): Add CpuHRESET. + (output_i386_opcode): Allow 4 byte base_opcode. + * i386-opc.h (enum): Add CpuHRESET. + (i386_cpu_flags): Add cpuhreset. + * i386-opc.tbl: Add Intel HRESET instruction. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-10-14 Lili Cui + + * i386-dis.c (enum): Add + PREFIX_MOD_3_0F01_REG_5_RM_4, + PREFIX_MOD_3_0F01_REG_5_RM_5, + PREFIX_MOD_3_0F01_REG_5_RM_6, + PREFIX_MOD_3_0F01_REG_5_RM_7, + X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, + X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, + X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, + X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, + X86_64_0FC7_REG_6_MOD_3_PREFIX_1. + (prefix_table): New instructions (see prefixes above). + (rm_table): Likewise + * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS, + CPU_ANY_UINTR_FLAGS. + (cpu_flags): Add CpuUINTR. + * i386-opc.h (enum): Add CpuUINTR. + (i386_cpu_flags): Add cpuuintr. + * i386-opc.tbl: Add UINTR insns. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-10-14 H.J. Lu + + * i386-gen.c (process_i386_opcode_modifier): Return 1 for + non-VEX/EVEX/prefix encoding. + (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode + has a prefix byte. + * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX + base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3. + * i386-tbl.h: Regenerated. + +2020-10-13 H.J. Lu + + * i386-gen.c (opcode_modifiers): Replace VexOpcode with + OpcodePrefix. + * i386-opc.h (VexOpcode): Renamed to ... + (OpcodePrefix): This. + (PREFIX_NONE): New. + (PREFIX_0X66): Likewise. + (PREFIX_0XF2): Likewise. + (PREFIX_0XF3): Likewise. + * i386-opc.tbl (Prefix_0X66): New. + (Prefix_0XF2): Likewise. + (Prefix_0XF3): Likewise. + Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd. + Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq. + * i386-tbl.h: Regenerated. + +2020-10-08 Przemyslaw Wirkus + + * aarch64-opc.c: Add BRBE system registers. + +2020-10-08 Przemyslaw Wirkus + + * aarch64-opc.c: New CSRE system registers defined. + +2020-10-05 Samanta Navarro + + * cgen-asm.c: Fix spelling mistakes. + * cgen-dis.c: Fix spelling mistakes. + * tic30-dis.c: Fix spelling mistakes. + +2020-10-05 H.J. Lu + + PR binutils/26704 + * i386-dis.c (putop): Always display suffix for %LQ in 64bit. + +2020-10-05 H.J. Lu + + PR binutils/26705 + * i386-dis.c (print_insn): Clear modrm if not needed. + (putop): Check need_modrm for modrm.mod != 3. Don't check + need_modrm for modrm.mod == 3. + +2020-09-28 Przemyslaw Wirkus + + * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn, + TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, + TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET, + TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1, + TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R, + TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, + TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, + TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR + WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3, + TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn, + TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn, + TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR, + TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, + TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn. + +2020-09-28 Przemyslaw Wirkus + + * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR. + +2020-09-28 Przemyslaw Wirkus + + * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , + TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1. + +2020-09-26 Alan Modra + + * csky-opc.h: Formatting. + (GENERAL_REG_BANK): Correct spelling. Update use throughout file. + (get_register_name): Mask arch with CSKY_ARCH_MASK for shift, + and shift 1u. + (get_register_number): Likewise. + * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag. + +2020-09-24 Lili Cui + + PR 26654 + * i386-dis.c (enum): Put MOD_VEX_0F38* together. + +2020-09-24 Andrew Burgess + + * csky-dis.c (csky_output_operand): Enclose body of if in curly + braces. + +2020-09-24 Lili Cui + + * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, + PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, + X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, + X86_64_0F01_REG_1_RM_7_P_2. + (prefix_table): Likewise. + (x86_64_table): Likewise. + (rm_table): Likewise. + * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS + and CPU_ANY_TDX_FLAGS. + (cpu_flags): Add CpuTDX. + * i386-opc.h (enum): Add CpuTDX. + (i386_cpu_flags): Add cputdx. + * i386-opc.tbl: Add TDX insns. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-09-17 Cooper Qu <> + + * csky-dis.c (using_abi): New. + (parse_csky_dis_options): New function. + (get_gr_name): New function. + (get_cr_name): New function. + (csky_output_operand): Use get_gr_name and get_cr_name to + disassemble and add handle of OPRND_TYPE_IMM5b_LS. + (print_insn_csky): Parse disassembler options. + * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum. + (GENARAL_REG_BANK): Define. + (REG_SUPPORT_ALL): Define. + (REG_SUPPORT_ALL): New. + (ASH): Define. + (REG_SUPPORT_A): Define. + (REG_SUPPORT_B): Define. + (REG_SUPPORT_C): Define. + (REG_SUPPORT_D): Define. + (REG_SUPPORT_E): Define. + (csky_abiv1_general_regs): New. + (csky_abiv1_control_regs): New. + (csky_abiv2_general_regs): New. + (csky_abiv2_control_regs): New. + (get_register_name): New function. + (get_register_number): New function. + (csky_get_general_reg_name): New function. + (csky_get_general_regno): New function. + (csky_get_control_reg_name): New function. + (csky_get_control_regno): New function. + (csky_v2_opcodes): Prefer two oprerans format for bclri and + bseti, strengthen the operands legality check of addc, zext + and sext. + +2020-09-23 Lili Cui + + * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, + MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, + MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, + MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, + PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. + (reg_table): New instructions (see prefixes above). + (prefix_table): Likewise. + (three_byte_table): Likewise. + (mod_table): Likewise + * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, + CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. + (cpu_flags): Likewise. + (operand_type_init): Likewise. + * i386-opc.h (enum): Add CpuKL and CpuWide_KL. + (i386_cpu_flags): Add cpukl and cpuwide_kl. + * i386-opc.tbl: Add KL and WIDE_KL insns. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-09-21 Alan Modra + + * rx-dis.c (flag_names): Add missing comma. + (register_names, flag_names, double_register_names), + (double_register_high_names, double_register_low_names), + (double_control_register_names, double_condition_names): Remove + trailing commas. + +2020-09-18 David Faust + + * bpf-desc.c: Regenerate. + * bpf-desc.h: Likewise. + * bpf-opc.c: Likewise. + * bpf-opc.h: Likewise. + +2020-09-16 Andrew Burgess + + * csky-dis.c (csky_get_disassembler): Don't return NULL when there + is no BFD. + +2020-09-16 Alan Modra + + * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation. + +2020-09-10 Nick Clifton + + * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false + for hidden, local, no-type symbols. + (disassemble_init_powerpc): Point the symbol_is_valid field in the + info structure at the new function. + +2020-09-10 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions. + * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva + opcode fixing. + +2020-09-10 Nick Clifton + + * csky-dis.c (csky_output_operand): Coerce the immediate values to + long before printing. + +2020-09-10 Alan Modra + + * csky-dis.c (csky_output_operand): Don't sprintf str to itself. + +2020-09-07 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's + ISA flag. + +2020-09-07 Cooper Qu + + * csky-dis.c (csky_output_operand): Add handlers for + OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and + OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH + to support FPUV3 instructions. + * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b, + OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and + OPRND_TYPE_DFLOAT_FMOVI. + (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8, + OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24, + OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22, + OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25, + OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25, + OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21, + OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24, + OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25, + OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20, + OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25, + OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24, + OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20, + OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define. + (csky_v2_opcodes): Add FPUV3 instructions. + +2020-09-08 Alex Coplan + + * aarch64-dis.c (print_operands): Pass CPU features to + aarch64_print_operand(). + * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine + preferred disassembly of system registers. + (SR_RNG): Refactor to use new SR_FEAT2 macro. + (SR_FEAT2): New. + (SR_V8_1_A): New. + (SR_V8_4_A): New. + (SR_V8_A): New. + (SR_V8_R): New. + (SR_EXPAND_ELx): New. + (SR_EXPAND_EL12): New. + (aarch64_sys_regs): Specify which registers are only on + A-profile, add R-profile system registers. + (ENC_BARLAR): New. + (PRBARn_ELx): New. + (PRLARn_ELx): New. + (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for + Armv8-R AArch64. + +2020-09-08 Alex Coplan + + * aarch64-tbl.h (aarch64_feature_v8_r): New. + (ARMV8_R): New. + (V8_R_INSN): New. + (aarch64_opcode_table): Add dfb. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + +2020-09-08 Alex Coplan + + * aarch64-dis.c (arch_variant): New. + (determine_disassembling_preference): Disassemble according to + arch variant. + (select_aarch64_variant): New. + (print_insn_aarch64): Set feature set. + +2020-09-02 Alan Modra + + * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3), + (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9), + (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16), + (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9), + (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID), + (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP), + (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long + for value parameter and update code to suit. + (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16), + (extract_d22, extract_d23, extract_i9): Use unsigned long variables. + +2020-09-02 Alan Modra + + * i386-dis.c (OP_E_memory): Don't cast to signed type when + negating. + (get32, get32s): Use unsigned types in shift expressions. + +2020-09-02 Alan Modra + + * csky-dis.c (print_insn_csky): Use unsigned type for "given". + +2020-09-02 Alan Modra + + * crx-dis.c: Whitespace. + (print_arg): Use unsigned type for longdisp and mask variables, + and for left shift constant. + +2020-09-02 Alan Modra + + * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift. + * bpf-ibld.c: Regenerate. + * epiphany-ibld.c: Regenerate. + * fr30-ibld.c: Regenerate. + * frv-ibld.c: Regenerate. + * ip2k-ibld.c: Regenerate. + * iq2000-ibld.c: Regenerate. + * lm32-ibld.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * mep-ibld.c: Regenerate. + * mt-ibld.c: Regenerate. + * or1k-ibld.c: Regenerate. + * xc16x-ibld.c: Regenerate. + * xstormy16-ibld.c: Regenerate. + +2020-09-02 Alan Modra + + * bfin-dis.c (MASKBITS): Use SIGNBIT. + +2020-09-02 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Move divul and divsl + to CSKYV2_ISA_3E3R3 instruction set. + +2020-09-02 Cooper Qu + + * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws. + +2020-09-01 Alan Modra + + * mep-ibld.c: Regenerate. + +2020-08-31 Cooper Qu + + * csky-dis.c (csky_output_operand): Assign dis_info.value for + OPRND_TYPE_VREG. + +2020-08-30 Alan Modra + + * cr16-dis.c: Formatting. + (parameter): Delete struct typedef. Use dwordU instead + throughout file. + (make_argument ): Simplify detection of cbitb, sbitb + and tbitb. + (make_argument ): Extract 20-bit field not 16-bit. + +2020-08-29 Alan Modra + + PR 26446 + * csky-opc.h (MAX_OPRND_NUM): Define to 5. + (union csky_operand): Use MAX_OPRND_NUM to size oprnds array. + +2020-08-28 Alan Modra + + PR 26449 + PR 26450 + * cgen-ibld.in (insert_1): Use 1UL in forming mask. + (extract_normal): Likewise. + (insert_normal): Likewise, and move past zero length test. + (put_insn_int_value): Handle mask for zero length, use 1UL. + * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, + * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, + * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, + * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. + +2020-08-28 Cooper Qu + + * csky-dis.c (CSKY_DEFAULT_ISA): Define. + (csky_dis_info): Add member isa. + (csky_find_inst_info): Skip instructions that do not belong to + current CPU. + (csky_get_disassembler): Get infomation from attribute section. + (print_insn_csky): Set defualt ISA flag. + * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2. + * csky-opc.h (struct csky_opcode): Change isa_flag16 and + isa_flag32'type to unsigned 64 bits. + +2020-08-26 Jose E. Marchesi + + * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX. + 2020-08-26 David Faust * bpf-desc.c: Regenerate. @@ -561,7 +1160,7 @@ EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42, EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these - respectively. + respectively. (dis386_twobyte, three_byte_table, vex_table, vex_len_table, vex_w_table, mod_table): Replace / remove respective entries. (print_insn): Move up dp->prefix_requirement handling. Handle @@ -2385,7 +2984,7 @@ 2020-01-16 Andre Vieira PR 25376 - * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. + * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting @@ -2439,13 +3038,13 @@ * i386-dis.c (print_insn): Initialize the insn info fields, and detect jumps. -2012-01-13 Claudiu Zissulescu +2020-01-13 Claudiu Zissulescu * arc-opc.c (C_NE): Make it required. -2012-01-13 Claudiu Zissulescu +2020-01-13 Claudiu Zissulescu - * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo + * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo reserved register name. 2020-01-13 Alan Modra @@ -2582,13 +3181,13 @@ * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from uzip{1,2}. - * opcodes/aarch64-dis-2.c: Re-generate. + * aarch64-dis-2.c: Re-generate. 2020-01-03 Jan Beulich * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit FMMLA encoding. - * opcodes/aarch64-dis-2.c: Re-generate. + * aarch64-dis-2.c: Re-generate. 2020-01-02 Sergey Belyashov