X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=35cdbcfdfd2636066093768040f434dc68221640;hb=55c144e691ec05a7b8231b5c58dc6d6659a1c4eb;hp=1ca97eec29b950c6aad8b45784f9da4c71907e61;hpb=e292aa7a9529771c04e9578a2307b8c95bb5591c;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1ca97eec29..35cdbcfdfd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,264 @@ +2015-12-11 Matthew Wahab + + * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1, + pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1, + pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and + pmscr_el2. + (aarch64_sys_reg_supported_p): Add architecture feature tests for + the new registers. + +2015-12-10 Matthew Wahab + + * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp". + (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register + feature test for "s1e1rp" and "s1e1wp". + +2015-12-10 Matthew Wahab + + * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". + (aarch64_sys_ins_reg_supported_p): New. + +2015-12-10 Matthew Wahab + + * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt + with aarch64_sys_ins_reg_has_xt. + (aarch64_ext_sysins_op): Likewise. + * aarch64-opc.c (operand_general_constraint_met_p): Likewise. + (F_HASXT): New. + (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. + (aarch64_sys_regs_dc): Likewise. + (aarch64_sys_regs_at): Likewise. + (aarch64_sys_regs_tlbi): Likewise. + (aarch64_sys_ins_reg_has_xt): New. + +2015-12-10 Matthew Wahab + + * aarch64-opc.c (aarch64_sys_regs): Add "uao". + (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao". + (aarch64_pstatefields): Add "uao". + (aarch64_pstatefield_supported_p): Add checks for "uao". + +2015-12-10 Matthew Wahab + + * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1", + "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1", + "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2". + (aarch64_sys_reg_supported_p): Add architecture feature tests for + new registers. + +2015-12-10 Matthew Wahab + + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-tbl.h (aarch64_feature_ras): New. + (RAS): New. + (aarch64_opcode_table): Add "esb". + +2015-12-09 H.J. Lu + + * i386-dis.c (MOD_0F01_REG_5): New. + (RM_0F01_REG_5): Likewise. + (reg_table): Use MOD_0F01_REG_5. + (mod_table): Add MOD_0F01_REG_5. + (rm_table): Add RM_0F01_REG_5. + * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS. + (cpu_flags): Add CpuOSPKE. + * i386-opc.h (CpuOSPKE): New. + (i386_cpu_flags): Add cpuospke. + * i386-opc.tbl: Add rdpkru and wrpkru instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2015-12-07 DJ Delorie + + * rl78-decode.opc: Enable MULU for all ISAs. + * rl78-decode.c: Regenerate. + +2015-12-07 Alan Modra + + * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by + major opcode/xop. + +2015-12-04 Claudiu Zissulescu + + * arc-dis.c (special_flag_p): Match full mnemonic. + * arc-opc.c (print_insn_arc): Check section size to read + appropriate number of bytes. Fix printing. + * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without + arguments. + +2015-12-02 Andre Vieira + + * arm-dis.c (arm_opcodes): : Fix typo... + : ... to this. + +2015-11-27 Matthew Wahab + + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New. + (QL_INT2FP_H, QL_FP2INT_H): New. + (QL_FP2_H, QL_FP3_H, QL_FP4_H): New + (QL_DST_H): New. + (QL_FCCMP_H): New. + (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf, + fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau, + fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp, + fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm, + frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax, + fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and + fcsel. + +2015-11-27 Matthew Wahab + + * aarch64-opc.c (half_conv_t): New. + (expand_fp_imm): Replace is_dp flag with the parameter size to + specify the number of bytes for the required expansion. Treat + a 16-bit expansion like a 32-bit expansion. Add check for an + unsupported size request. Update comment. + (aarch64_print_operand): Update to support 16-bit floating point + values. Update for changes to expand_fp_imm. + +2015-11-27 Matthew Wahab + + * aarch64-tbl.h (aarch64_feature_fp_f16): New. + (FP_F16): New. + +2015-11-27 Matthew Wahab + + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add + "rev64". + +2015-11-27 Matthew Wahab + + * aarch64-asm-2.c: Regenerate. + * aarch64-asm.c (convert_bfc_to_bfm): New. + (convert_to_real): Add case for OP_BFC. + * aarch64-dis-2.c: Regenerate. + * aarch64-dis.c: (convert_bfm_to_bfc): New. + (convert_to_alias): Add case for OP_BFC. + * aarch64-opc-2.c: Regenerate. + * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert + to allow width operand in three-operand instructions. + * aarch64-tbl.h (QL_BF1): New. + (aarch64_feature_v8_2): New. + (ARMV8_2): New. + (aarch64_opcode_table): Add "bfc". + +2015-11-27 Matthew Wahab + + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-dis.c: Weaken assert. + * aarch64-gen.c: Include the instruction in the list of its + possible aliases. + +2015-11-27 Matthew Wahab + + * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1". + (aarch64_sys_reg_supported_p): Add ARMv8.2 system register + feature test. + +2015-11-23 Tristan Gingold + + * arm-dis.c (print_insn): Also set is_thumb for Mach-O. + +2015-11-20 Matthew Wahab + + * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, + sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, + tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, + amair_el12, vbar_el12, contextidr_el2, contextidr_el12, + cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, + cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, + cnthv_ctl_el2, cnthv_cval_el2. + (aarch64_sys_reg_supported_p): Update for the new system + registers. + +2015-11-20 Nick Clifton + + PR binutils/19224 + * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause. + +2015-11-20 Nick Clifton + + * po/zh_CN.po: Updated simplified Chinese translation. + +2015-11-19 Matthew Wahab + + * aarch64-opc.c (operand_general_constraint_met_p): Check validity + of MSR PAN immediate operand. + +2015-11-16 Nick Clifton + + * rx-dis.c (condition_names): Replace always and never with + invalid, since the always/never conditions can never be legal. + +2015-11-13 Tristan Gingold + + * configure: Regenerate. + +2015-11-11 Alan Modra + Peter Bergner + + * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. + Add PPC_OPCODE_VSX3 to the vsx entry. + (powerpc_init_dialect): Set default dialect to power9. + * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, + insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, + extract_l1 insert_xtq6, extract_xtq6): New static functions. + (insert_esync): Test for illegal L operand value. + (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, + XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, + XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, + XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, + PPCVSX3): New defines. + (powerpc_opcodes) : Use XBF_MASK. + : Use XBFRARB_MASK. + : New instructions. + : Disable on POWER9. + : Add additional operands. + +2015-11-02 Nick Clifton + + * rx-decode.opc (rx_decode_opcode): Decode extra NOP + instructions. + * rx-decode.c: Regenerate. + 2015-11-02 Nick Clifton * rx-decode.opc (rx_disp): If the displacement is zero, set the