X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=392fcacfb6d7c63fbd83af16046ddc269e3fa6c3;hb=8063ab7e37c1a2abfa272d10e8d2c7ae192b1787;hp=314ef7f9e4ee38a232553fda6deef98ba6fda467;hpb=9d3bf266fd601031d12584982ef43df22c95e933;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 314ef7f9e4..392fcacfb6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,203 @@ +2019-09-10 Miod Vallat + + PR 24982 + * m68k-opc.c: Correct aliases for tdivsl and tdivul. + +2019-09-09 Phil Blundell + + binutils 2.33 branch created. + +2019-09-03 Nick Clifton + + PR 24961 + * tic30-dis.c (get_indirect_operand): Check for bufcnt being + greater than zero before indexing via (bufcnt -1). + +2019-09-03 Nick Clifton + + PR 24958 + * mmix-dis.c (MAX_REG_NAME_LEN): Define. + (MAX_SPEC_REG_NAME_LEN): Define. + (struct mmix_dis_info): Use defined constants for array lengths. + (get_reg_name): New function. + (get_sprec_reg_name): New function. + (print_insn_mmix): Use new functions. + +2019-08-27 Srinath Parvathaneni + + * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. + (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. + (print_insn_mve): Add condition to check Qm==Qn of VORR instruction. + +2019-08-22 Kyrylo Tkachov + + * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, + tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. + (aarch64_sys_reg_supported_p): Update checks for the above. + +2019-08-12 Srinath Parvathaneni + + * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for + cases MVE_SQRSHRL and MVE_UQRSHLL. + (print_insn_mve): Add case for specifier 'k' to check + specific bit of the instruction. + +2019-08-07 Phillipe Antoine + + PR 24854 + * arc-dis.c (arc_insn_length): Return 0 rather than aborting when + encountering an unknown machine type. + (print_insn_arc): Handle arc_insn_length returning 0. In error + cases return -1 rather than calling abort. + +2019-08-07 Jan Beulich + + * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms. + (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by + IgnoreSize. + * i386-tbl.h: Re-generate. + +2019-08-05 Barnaby Wilks + + * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH + instructions. + +2019-07-30 Mel Chen + + * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, + fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. + + * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, + fscsr. + +2019-07-24 Claudiu Zissulescu + + * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, + and MPY class instructions. + (parse_option): Add nps400 option. + (print_arc_disassembler_options): Add nps400 info. + +2019-07-24 Claudiu Zissulescu + + * arc-ext-tbl.h (bspeek): Remove it, added to main table. + (bspop): Likewise. + (modapp): Likewise. + * arc-opc.c (RAD_CHK): Add. + * arc-tbl.h: Regenerate. + +2019-07-23 Kyrylo Tkachov + + * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry. + (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding. + +2019-07-22 Barnaby Wilks + + * arm-dis.c (is_mve_unpredictable): Stop marking some MVE + instructions as UNPREDICTABLE. + +2019-07-19 Jose E. Marchesi + + * bpf-desc.c: Regenerated. + +2019-07-17 Jan Beulich + + * i386-gen.c (static_assert): Define. + (main): Use it. + * i386-opc.h (Opcode_Modifier_Max): Rename to ... + (Opcode_Modifier_Num): ... this. + (Mem): Delete. + +2019-07-16 Jan Beulich + + * i386-gen.c (operand_types): Move RegMem ... + (opcode_modifiers): ... here. + * i386-opc.h (RegMem): Move to opcode modifer enum. + (union i386_operand_type): Move regmem field ... + (struct i386_opcode_modifier): ... here. + * i386-opc.tbl (RegMem): Define. + (mov, movq): Move RegMem on segment, control, debug, and test + register flavors. + (pextrb): Move RegMem on register only flavors. Add IgnoreSize + to non-SSE2AVX flavor. + (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw): + Move RegMem on register only flavors. Drop IgnoreSize from + legacy encoding flavors. + (movss, movsd, vmovss, vmovsd): Drop RegMem from register only + flavors. + (vpinsrb, vpinsrw): Drop IgnoreSize where still present on + register only flavors. + (vmovd): Move RegMem and drop IgnoreSize on register only + flavor. Change opcode and operand order to store form. + * opcodes/i386-init.h, i386-tbl.h: Re-generate. + +2019-07-16 Jan Beulich + + * i386-gen.c (operand_type_init, operand_types): Replace SReg + entries. + * i386-opc.h (SReg2, SReg3): Replace by ... + (SReg): ... this. + (union i386_operand_type): Replace sreg fields. + * i386-opc.tbl (mov, ): Use SReg. + (push, pop): Likewies. Drop i386 and x86-64 specific segment + register flavors. + * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg. + * opcodes/i386-init.h, i386-tbl.h: Re-generate. + +2019-07-15 Jose E. Marchesi + + * bpf-desc.c: Regenerate. + * bpf-opc.c: Likewise. + * bpf-opc.h: Likewise. + +2019-07-14 Jose E. Marchesi + + * bpf-desc.c: Regenerate. + * bpf-opc.c: Likewise. + +2019-07-10 Hans-Peter Nilsson + + * arm-dis.c (print_insn_coprocessor): Rename index to + index_operand. + +2019-07-05 Kito Cheng + + * riscv-opc.c (riscv_insn_types): Add r4 type. + + * riscv-opc.c (riscv_insn_types): Add b and j type. + + * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect + format for sb type and correct s type. + +2019-07-02 Richard Sandiford + + * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the + SVE FMOV alias of FCPY. + +2019-07-02 Richard Sandiford + + * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags + to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries. + +2019-07-02 Richard Sandiford + + * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the + registers in an instruction prefixed by MOVPRFX. + +2019-07-01 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new + sve_size_13 icode to account for variant behaviour of + pmull{t,b}. + * aarch64-dis-2.c: Regenerate. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new + sve_size_13 icode to account for variant behaviour of + pmull{t,b}. + * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. + (OP_SVE_VVV_Q_D): Add new qualifier. + (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. + (struct aarch64_opcode): Split pmull{t,b} into those requiring + AES and those not. + 2019-07-01 Jan Beulich * opcodes/i386-gen.c (operand_type_init): Remove