X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=3d26869e51f6225131c1e899f1907b63d1f2ce8c;hb=1f38083f425e03faf55595414daf291306738222;hp=76c554fd9a3d8c058c6067adc3375d0c9323d7ec;hpb=ec6f095abc396e60f46e1b4724d0eb2e4d18213d;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 76c554fd9a..3d26869e51 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,296 @@ +2018-10-19 Tamar Christina + + * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode. + (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode. + (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them. + +2018-10-16 Matthew Malcomson + + * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data + corresponding to AARCH64_OPND_QLF_S_4B qualifier. + +2018-10-10 Jan Beulich + + * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and + Size64. Add Size. + * i386-opc.h (Size16, Size32, Size64): Delete. + (Size): New. + (SIZE16, SIZE32, SIZE64): Define. + (struct i386_opcode_modifier): Drop size16, size32, and size64. + Add size. + * i386-opc.tbl (Size16, Size32, Size64): Define. + * i386-tbl.h: Re-generate. + +2018-10-09 Sudakshina Das + + * aarch64-opc.c (operand_general_constraint_met_p): Add + SSBS in the check for one-bit immediate. + (aarch64_sys_regs): New entry for SSBS. + (aarch64_sys_reg_supported_p): New check for above. + (aarch64_pstatefields): New entry for SSBS. + (aarch64_pstatefield_supported_p): New check for above. + +2018-10-09 Sudakshina Das + + * aarch64-opc.c (aarch64_sys_regs): New entries for + scxtnum_el[0,1,2,3,12] and id_pfr2_el1. + (aarch64_sys_reg_supported_p): New checks for above. + +2018-10-09 Sudakshina Das + + * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. + (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag + with the hint immediate. + * aarch64-opc.c (aarch64_hint_options): New entries for + c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. + (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET + while checking for HINT_OPD_F_NOPRINT flag. + * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to + extract value. + * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. + (aarch64_opcode_table): Add entry for BTI. + (AARCH64_OPERANDS): Add new description for BTI targets. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2018-10-09 Sudakshina Das + + * aarch64-opc.c (aarch64_sys_regs): New entries for + rndr and rndrrs. + (aarch64_sys_reg_supported_p): New check for above. + +2018-10-09 Sudakshina Das + + * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. + (aarch64_sys_ins_reg_supported_p): New check for above. + +2018-10-09 Sudakshina Das + + * aarch64-dis.c (aarch64_ext_sysins_op): Add case for + AARCH64_OPND_SYSREG_SR. + * aarch64-opc.c (aarch64_print_operand): Likewise. + (aarch64_sys_regs_sr): Define table. + (aarch64_sys_ins_reg_supported_p): Check for RCTX with + AARCH64_FEATURE_PREDRES. + * aarch64-tbl.h (aarch64_feature_predres): New. + (PREDRES, PREDRES_INSN): New. + (aarch64_opcode_table): Add entries for cfp, dvp and cpp. + (AARCH64_OPERANDS): Add new description for SYSREG_SR. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2018-10-09 Sudakshina Das + + * aarch64-tbl.h (aarch64_feature_sb): New. + (SB, SB_INSN): New. + (aarch64_opcode_table): Add entry for sb. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2018-10-09 Sudakshina Das + + * aarch64-tbl.h (aarch64_feature_flagmanip): New. + (aarch64_feature_frintts): New. + (FLAGMANIP, FRINTTS): New. + (aarch64_opcode_table): Add entries for xaflag, axflag + and frint[32,64][x,z] instructions. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2018-10-09 Sudakshina Das + + * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New. + (ARMV8_5, V8_5_INSN): New. + +2018-10-08 Tamar Christina + + * aarch64-opc.c (verify_constraints): Use memset instead of {0}. + +2018-10-05 H.J. Lu + + * i386-dis.c (rm_table): Add enclv. + * i386-opc.tbl: Add enclv. + * i386-tbl.h: Regenerated. + +2018-10-05 Sudakshina Das + + * arm-dis.c (arm_opcodes): Add sb. + (thumb32_opcodes): Likewise. + +2018-10-05 Richard Henderson + Stafford Horne + + * or1k-desc.c: Regenerate. + * or1k-desc.h: Regenerate. + * or1k-opc.c: Regenerate. + * or1k-opc.h: Regenerate. + * or1k-opinst.c: Regenerate. + +2018-10-05 Richard Henderson + + * or1k-asm.c: Regenerated. + * or1k-desc.c: Regenerated. + * or1k-desc.h: Regenerated. + * or1k-dis.c: Regenerated. + * or1k-ibld.c: Regenerated. + * or1k-opc.c: Regenerated. + * or1k-opc.h: Regenerated. + * or1k-opinst.c: Regenerated. + +2018-10-05 Richard Henderson + + * or1k-asm.c: Regenerate. + +2018-10-03 Tamar Christina + + * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier. + * aarch64-dis.c (print_operands): Refactor to take notes. + (print_verifier_notes): New. + (print_aarch64_insn): Apply constraint verifier. + (print_insn_aarch64_word): Update call to print_aarch64_insn. + * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format. + +2018-10-03 Tamar Christina + + * aarch64-opc.c (init_insn_block): New. + (verify_constraints, aarch64_is_destructive_by_operands): New. + * aarch64-opc.h (verify_constraints): New. + +2018-10-03 Tamar Christina + + * aarch64-dis.c (aarch64_opcode_decode): Update verifier call. + * aarch64-opc.c (verify_ldpsw): Update arguments. + +2018-10-03 Tamar Christina + + * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove. + (aarch64_decode_insn, print_insn_aarch64_word): Use err_type. + +2018-10-03 Tamar Christina + + * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence. + * aarch64-dis.c (insn_sequence): New. + +2018-10-03 Tamar Christina + + * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN, + _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN, + _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN, + V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize + constraints. + (_SVE_INSNC): New. + (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize + constraints. + (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and + F_SCAN flags. + (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf, + sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech, + sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb, + sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd, + uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub, + uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add + C_SCAN_MOVPRFX and C_MAX_ELEM constraints. + +2018-10-02 Palmer Dabbelt + + * riscv-opc.c (riscv_opcodes) : New opcode. + +2018-09-23 Sandra Loosemore + + * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions + are used when extracting signed fields and converting them to + potentially 64-bit types. + +2018-09-21 Simon Marchi + + * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS. + * Makefile.in: Re-generate. + * aclocal.m4: Re-generate. + * configure: Re-generate. + * configure.ac: Remove check for -Wno-missing-field-initializers. + * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element. + (csky_v2_opcodes): Likewise. + +2018-09-20 Maciej W. Rozycki + + * arc-nps400-tbl.h: Append `ull' to large constants throughout. + +2018-09-20 Nelson Chu + + * nds32-asm.c (operand_fields): Remove the unused fields. + (nds32_opcodes): Remove the unused instructions. + * nds32-dis.c (nds32_ex9_info): Removed. + (nds32_parse_opcode): Updated. + (print_insn_nds32): Likewise. + * nds32-asm.c (config.h, stdlib.h, string.h): New includes. + (LEX_SET_FIELD, LEX_GET_FIELD): Update defines. + (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table, + build_opcode_hash_table): New functions. + (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table, + nds32_opcode_table): New. + (hw_ktabs): Declare it to a pointer rather than an array. + (build_hash_table): Removed. + * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT, + SYN_ROPT and upadte HW_GPR and HW_INT. + * nds32-dis.c (keywords): Remove const. + (match_field): New function. + (nds32_parse_opcode): Updated. + * disassemble.c (disassemble_init_for_target): + Add disassemble_init_nds32. + * nds32-dis.c (eum map_type): New. + (nds32_private_data): Likewise. + (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid, + nds32_add_opcode_hash_table, disassemble_init_nds32): New functions. + (print_insn_nds32): Updated. + * nds32-asm.c (parse_aext_reg): Add new parameter. + (parse_re, parse_re2, parse_aext_reg): Only reduced registers + are allowed to use. + All callers changed. + * nds32-asm.c (keyword_usr, keyword_sr): Updated. + (operand_fields): Add new fields. + (nds32_opcodes): Add new instructions. + (keyword_aridxi_mx): New keyword. + * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX + and NASM_ATTR_ZOL. + (ALU2_1, ALU2_2, ALU2_3): New macros. + * nds32-dis.c (nds32_filter_unknown_insn): Updated. + +2018-09-17 Kito Cheng + + * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu. + +2018-09-17 H.J. Lu + + PR gas/23670 + * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, + EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. + (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. + (EVEX_LEN_0F7E_P_1): Likewise. + (EVEX_LEN_0F7E_P_2): Likewise. + (EVEX_LEN_0FD6_P_2): Likewise. + * i386-dis.c (USE_EVEX_LEN_TABLE): New. + (EVEX_LEN_TABLE): Likewise. + (EVEX_LEN_0F6E_P_2): New enum. + (EVEX_LEN_0F7E_P_1): Likewise. + (EVEX_LEN_0F7E_P_2): Likewise. + (EVEX_LEN_0FD6_P_2): Likewise. + (evex_len_table): New. + (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. + * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. + * i386-tbl.h: Regenerated. + +2018-09-17 H.J. Lu + + PR gas/23665 + * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and + VEX_LEN_0F7E_P_2 entries. + * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. + * i386-tbl.h: Regenerated. + 2018-09-17 H.J. Lu * i386-dis.c (VZERO_Fixup): Removed.