X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=4c748af9be1e6c1d12c2d46d0d3ec7d012c2000c;hb=920d2ddccb72a366140ed28283165b274f7a9045;hp=967de6f3d132c46adc94349fa883cc0c58355984;hpb=047cd301d40288d13e44f3322541ac28ebe06078;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 967de6f3d1..4c748af9be 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,234 @@ +2016-11-02 Igor Tsimbalist + + * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A, + PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB. + * i386-dis-evex.h (evex_table): Updated. + * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS, + CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS. + (cpu_flags): Add CpuAVX512_4FMAPS. + (opcode_modifiers): Add ImplicitQuadGroup modifier. + * i386-opc.h (AVX512_4FMAP): New. + (i386_cpu_flags): Add cpuavx512_4fmaps. + (ImplicitQuadGroup): New. + (i386_opcode_modifier): Add implicitquadgroup. + * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions. + * i386-init.h: Regenerate. + * i386-tbl.h: Ditto. + +2016-11-01 Palmer Dabbelt + Andrew Waterman + + Add support for RISC-V architecture. + * configure.ac: Add entry for bfd_riscv_arch. + * configure: Regenerate. + * disassemble.c (disassembler): Add support for riscv. + (disassembler_usage): Likewise. + * riscv-dis.c: New file. + * riscv-opc.c: New file. + +2016-10-21 H.J. Lu + + * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. + (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry. + (rm_table): Update the RM_0FAE_REG_7 entry. + * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS. + (cpu_flags): Remove CpuPCOMMIT. + * i386-opc.h (CpuPCOMMIT): Removed. + (i386_cpu_flags): Remove cpupcommit. + * i386-opc.tbl: Remove pcommit. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2016-10-20 H.J. Lu + + PR binutis/20705 + * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and + the highest bit in VEX.vvvv for the 3-byte VEX prefix in + 32-bit mode. Don't check vex.register_specifier in 32-bit + mode. + (OP_VEX): Check for invalid mask registers. + +2016-10-18 H.J. Lu + + PR binutis/20699 + * i386-dis.c (OP_E_memory): Check addr32flag in stead of + sizeflag. + +2016-10-18 H.J. Lu + + PR binutis/20704 + * i386-dis.c (three_byte_table): Remove the remaining SSE5 support. + +2016-10-18 Maciej W. Rozycki + + * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index' + local variable to `index_regno'. + +2016-10-17 Cupertino Miranda + + * arc-tbl.h: Removed any "inv.+" instructions from the table. + +2016-10-14 Claudiu Zissulescu + + * arc-dis.c (find_format_from_table): Discriminate LIMM indicator + usage on ISA basis. + +2016-10-11 Jiong Wang + + PR target/20666 + * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index. + +2016-10-07 Jiong Wang + + PR target/20667 + * aarch64-opc.c (aarch64_print_operand): Always print operand if it's + available. + +2016-10-07 Alan Modra + + * sh-opc.h (sh_merge_bfd_arch): Delete prototype. + +2016-10-06 Alan Modra + + * aarch64-opc.c: Spell fall through comments consistently. + * i386-dis.c: Likewise. + * aarch64-dis.c: Add missing fall through comments. + * aarch64-opc.c: Likewise. + * arc-dis.c: Likewise. + * arm-dis.c: Likewise. + * i386-dis.c: Likewise. + * m68k-dis.c: Likewise. + * mep-asm.c: Likewise. + * ns32k-dis.c: Likewise. + * sh-dis.c: Likewise. + * tic4x-dis.c: Likewise. + * tic6x-dis.c: Likewise. + * vax-dis.c: Likewise. + +2016-10-06 Alan Modra + + * arc-ext.c (create_map): Add missing break. + * msp430-decode.opc (encode_as): Likewise. + * msp430-decode.c: Regenerate. + +2016-10-06 Alan Modra + + * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic. + * crx-dis.c (print_insn_crx): Likewise. + +2016-09-30 H.J. Lu + + PR binutils/20657 + * i386-dis.c (putop): Don't assign alt twice. + +2016-09-29 Jiong Wang + + PR target/20553 + * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field. + +2016-09-29 Alan Modra + + * ppc-opc.c (L): Make compulsory. + (LOPT): New, optional form of L. + (HTM_R): Define as LOPT. + (L0, L1): Delete. + (L32OPT): New, optional for 32-bit L. + (L2OPT): New, 2-bit L for dcbf. + (SVC_LEC): Update. + (L2): Define. + (insert_l0, extract_l0, insert_l1, extract_l2): Delete. + (powerpc_opcodes ): Use L32OPT. + : Use L2OPT. + : Use LOPT. + : Use L2. + +2016-09-26 Vlad Zakharov + + * Makefile.in: Regenerate. + * configure: Likewise. + +2016-09-26 Claudiu Zissulescu + + * arc-ext-tbl.h (EXTINSN2OPF): Define. + (EXTINSN2OP): Use EXTINSN2OPF. + (bspeekm, bspop, modapp): New extension instructions. + * arc-opc.c (F_DNZ_ND): Define. + (F_DNZ_D): Likewise. + (F_SIZEB1): Changed. + (C_DNZ_D): Define. + (C_HARD): Changed. + * arc-tbl.h (dbnz): New instruction. + (prealloc): Allow it for ARC EM. + (xbfu): Likewise. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (print_immediate_offset_address): Print spaces + after commas in addresses. + (aarch64_print_operand): Likewise. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (operand_general_constraint_met_p): Use "must be" + rather than "should be" or "expected to be" in error messages. + +2016-09-21 Richard Sandiford + + * aarch64-dis.c (remove_dot_suffix): New function, split out from... + (print_mnemonic_name): ...here. + (print_comment): New function. + (print_aarch64_insn): Call it. + * aarch64-opc.c (aarch64_conds): Add SVE names. + (aarch64_print_operand): Print alternative condition names in + a comment. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) + (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) + (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) + (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) + (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) + (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) + (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) + (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) + (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) + (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) + (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) + (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) + (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) + (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) + (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) + (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) + (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) + (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) + (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) + (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) + (OP_SVE_XWU, OP_SVE_XXU): New macros. + (aarch64_feature_sve): New variable. + (SVE): New macro. + (_SVE_INSN): Likewise. + (aarch64_opcode_table): Add SVE instructions. + * aarch64-opc.h (extract_fields): Declare. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.c (extract_fields): Make global. + (do_misc_decoding): Handle the new SVE aarch64_ops. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) + (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New + aarch64_field_kinds. + * aarch64-opc.c (fields): Add corresponding entries. + * aarch64-asm.c (aarch64_get_variant): New function. + (aarch64_encode_variant_using_iclass): Likewise. + (aarch64_opcode_encode): Call it. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. + (aarch64_opcode_decode): Call it. + 2016-09-21 Richard Sandiford * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core