X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=592b8b568f2d74fab27059f22acb24247722dd82;hb=07f5af7d3c635234284e7a0f7dd7a410b1628b8b;hp=f231ea38e4923d6689c5073f1c9edf67545c1306;hpb=c8f785f220bab3c17fc93445ac509495d00d5afe;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f231ea38e4..592b8b568f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,333 @@ +2016-06-03 H.J. Lu + + PR binutis/18386 + * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. + (indir_v_mode): New. + Add comments for '&'. + (reg_table): Replace "{T|}" with "{&|}" on call and jmp. + (putop): Handle '&'. + (intel_operand_size): Handle indir_v_mode. + (OP_E_register): Likewise. + * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add + 64-bit indirect call/jmp for AMD64. + * i386-tbl.h: Regenerated + +2016-06-02 Andrew Burgess + + * arc-dis.c (struct arc_operand_iterator): New structure. + (find_format_from_table): All the old content from find_format, + with some minor adjustments, and parameter renaming. + (find_format_long_instructions): New function. + (find_format): Rewritten. + (arc_insn_length): Add LSB parameter. + (extract_operand_value): New function. + (operand_iterator_next): New function. + (print_insn_arc): Use new functions to find opcode, and iterator + over operands. + * arc-opc.c (insert_nps_3bit_dst_short): New function. + (extract_nps_3bit_dst_short): New function. + (insert_nps_3bit_src2_short): New function. + (extract_nps_3bit_src2_short): New function. + (insert_nps_bitop1_size): New function. + (extract_nps_bitop1_size): New function. + (insert_nps_bitop2_size): New function. + (extract_nps_bitop2_size): New function. + (insert_nps_bitop_mod4_msb): New function. + (extract_nps_bitop_mod4_msb): New function. + (insert_nps_bitop_mod4_lsb): New function. + (extract_nps_bitop_mod4_lsb): New function. + (insert_nps_bitop_dst_pos3_pos4): New function. + (extract_nps_bitop_dst_pos3_pos4): New function. + (insert_nps_bitop_ins_ext): New function. + (extract_nps_bitop_ins_ext): New function. + (arc_operands): Add new operands. + (arc_long_opcodes): New global array. + (arc_num_long_opcodes): New global. + * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes. + +2016-06-01 Trevor Saunders + + * nds32-asm.h: Add extern "C". + * sh-opc.h: Likewise. + +2016-06-01 Graham Markall + + * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and + 0,b,limm to the rflt instruction. + +2016-05-31 Trevor Saunders + + * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned + constant. + +2016-05-29 H.J. Lu + + PR gas/20145 + * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, + CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, + CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, + CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, + CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. + * i386-init.h: Regenerated. + +2016-05-27 H.J. Lu + + PR gas/20145 + * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove + CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from + CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. + Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and + CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from + CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, + CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. + Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, + CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, + CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, + CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX + for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable + CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and + CpuRegMask for AVX512. + (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM + and CpuRegMask. + (set_bitfield_from_cpu_flag_init): New function. + (set_bitfield): Remove const on f. Call + set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. + * i386-opc.h (CpuRegMMX): New. + (CpuRegXMM): Likewise. + (CpuRegYMM): Likewise. + (CpuRegZMM): Likewise. + (CpuRegMask): Likewise. + (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm + and cpuregmask. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2016-05-27 H.J. Lu + + PR gas/20154 + * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. + (opcode_modifiers): Add AMD64 and Intel64. + (main): Properly verify CpuMax. + * i386-opc.h (CpuAMD64): Removed. + (CpuIntel64): Likewise. + (CpuMax): Set to CpuNo64. + (i386_cpu_flags): Remove cpuamd64 and cpuintel64. + (AMD64): New. + (Intel64): Likewise. + (i386_opcode_modifier): Add amd64 and intel64. + (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 + on call and jmp. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2016-05-27 H.J. Lu + + PR gas/20154 + * i386-gen.c (main): Fail if CpuMax is incorrect. + * i386-opc.h (CpuMax): Set to CpuIntel64. + * i386-tbl.h: Regenerated. + +2016-05-27 Nick Clifton + + PR target/20150 + * msp430-dis.c (msp430dis_read_two_bytes): New function. + (msp430dis_opcode_unsigned): New function. + (msp430dis_opcode_signed): New function. + (msp430_singleoperand): Use the new opcode reading functions. + Only disassenmble bytes if they were successfully read. + (msp430_doubleoperand): Likewise. + (msp430_branchinstr): Likewise. + (msp430x_callx_instr): Likewise. + (print_insn_msp430): Check that it is safe to read bytes before + attempting disassembly. Use the new opcode reading functions. + +2016-05-26 Peter Bergner + + * ppc-opc.c (CY): New define. Document it. + (powerpc_opcodes) : New mnemonics. + +2016-05-25 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, + CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS + and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, + CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to + CPU_ANY_AVX_FLAGS. + * i386-init.h: Regenerated. + +2016-05-25 H.J. Lu + + PR gas/20141 + * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, + CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. + * i386-init.h: Regenerated. + +2016-05-25 H.J. Lu + + * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to + CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. + * i386-init.h: Regenerated. + +2016-05-23 Claudiu Zissulescu + + * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type + information. + (print_insn_arc): Set insn_type information. + * arc-opc.c (C_CC): Add F_CLASS_COND. + * arc-tbl.h (bbit0, bbit1): Update subclass to COND. + (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. + (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. + (breq, breq_s, brge, brhs, brlo, brlt): Likewise. + (brne, brne_s, jeq_s, jne_s): Likewise. + +2016-05-23 Claudiu Zissulescu + + * arc-tbl.h (neg): New instruction variant. + +2016-05-23 Cupertino Miranda + + * arc-dis.c (find_format, find_format, get_auxreg) + (print_insn_arc): Changed. + * arc-ext.h (INSERT_XOP): Likewise. + +2016-05-23 Trevor Saunders + + * tic54x-dis.c (sprint_mmr): Adjust. + * tic54x-opc.c: Likewise. + +2016-05-19 Alan Modra + + * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi. + +2016-05-19 Alan Modra + + * ppc-opc.c: Formatting. + (NSISIGNOPT): Define. + (powerpc_opcodes ): Use NSISIGNOPT. + +2016-05-18 Maciej W. Rozycki + + * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, + replacing references to `micromips_ase' throughout. + (_print_insn_mips): Don't use file-level microMIPS annotation to + determine the disassembly mode with the symbol table. + +2016-05-13 Peter Bergner + + * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. + +2016-05-11 Andrew Bennett + + * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and + mips64r6. + * mips-opc.c (D34): New macro. + (mips_builtin_opcodes): Define bposge32c for DSPr3. + +2016-05-10 Alexander Fomin + + * i386-dis.c (prefix_table): Add RDPID instruction. + * i386-gen.c (cpu_flag_init): Add RDPID flag. + (cpu_flags): Add RDPID bitfield. + * i386-opc.h (enum): Add RDPID element. + (i386_cpu_flags): Add RDPID field. + * i386-opc.tbl: Add RDPID instruction. + * i386-init.h: Regenerate. + * i386-tbl.h: Regenerate. + +2016-05-10 Thomas Preud'homme + + * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get + branch type of a symbol. + (print_insn): Likewise. + +2016-05-10 Thomas Preud'homme + + * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M + Mainline Security Extensions instructions. + (thumb_opcodes): Add entries for narrow ARMv8-M Security + Extensions instructions. + (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions + instructions. + (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions + special registers. + +2016-05-09 Jose E. Marchesi + + * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. + +2016-05-03 Claudiu Zissulescu + + * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. + (arcExtMap_genOpcode): Likewise. + * arc-opc.c (arg_32bit_rc): Define new variable. + (arg_32bit_u6): Likewise. + (arg_32bit_limm): Likewise. + +2016-05-03 Szabolcs Nagy + + * aarch64-gen.c (VERIFIER): Define. + * aarch64-opc.c (VERIFIER): Define. + (verify_ldpsw): Use static linkage. + * aarch64-opc.h (verify_ldpsw): Remove. + * aarch64-tbl.h: Use VERIFIER for verifiers. + +2016-04-28 Nick Clifton + + PR target/19722 + * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. + * aarch64-opc.c (verify_ldpsw): New function. + * aarch64-opc.h (verify_ldpsw): New prototype. + * aarch64-tbl.h: Add initialiser for verifier field. + (LDPSW): Set verifier to verify_ldpsw. + +2016-04-23 H.J. Lu + + PR binutils/19983 + PR binutils/19984 + * i386-dis.c (print_insn): Return -1 if size of bfd_vma is + smaller than address size. + +2016-04-20 Trevor Saunders + + * alpha-dis.c: Regenerate. + * crx-dis.c: Likewise. + * disassemble.c: Likewise. + * epiphany-opc.c: Likewise. + * fr30-opc.c: Likewise. + * frv-opc.c: Likewise. + * ip2k-opc.c: Likewise. + * iq2000-opc.c: Likewise. + * lm32-opc.c: Likewise. + * lm32-opinst.c: Likewise. + * m32c-opc.c: Likewise. + * m32r-opc.c: Likewise. + * m32r-opinst.c: Likewise. + * mep-opc.c: Likewise. + * mt-opc.c: Likewise. + * or1k-opc.c: Likewise. + * or1k-opinst.c: Likewise. + * tic80-opc.c: Likewise. + * xc16x-opc.c: Likewise. + * xstormy16-opc.c: Likewise. + +2016-04-19 Andrew Burgess + + * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, + fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp, + calcsd, and calcxd instructions. + * arc-opc.c (insert_nps_bitop_size): Delete. + (extract_nps_bitop_size): Delete. + (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. + (extract_nps_qcmp_m3): Define. + (extract_nps_qcmp_m2): Define. + (extract_nps_qcmp_m1): Define. + (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. + (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL + (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, + NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, + NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and + NPS_QCMP_M3. + 2016-04-19 Andrew Burgess * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.