X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=62223fa1cb3231017d8c746e1b392accf69b03ab;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=a4106125e9c3a72b30da4385f87ec6cf118dff50;hpb=c5d7be0c97a75ff20b49d57bff078360464125fb;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a4106125e9..62223fa1cb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,798 @@ +2020-06-03 Nick Clifton + + * po/sr.po: Updated Serbian translation. + +2020-06-03 Nelson Chu + + * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int. + (riscv_get_priv_spec_class): Likewise. + +2020-06-01 Alan Modra + + * bpf-desc.c: Regenerate. + +2020-05-28 Jose E. Marchesi + David Faust + + * bpf-desc.c: Regenerate. + * bpf-opc.h: Likewise. + * bpf-opc.c: Likewise. + * bpf-dis.c: Likewise. + +2020-05-28 Alan Modra + + * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative + values. + +2020-05-28 Alan Modra + + * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for + immediates. + (print_insn_ns32k): Revert last change. + +2020-05-28 Nick Clifton + + * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to + static. + +2020-05-26 Sandra Loosemore + + Fix extraction of signed constants in nios2 disassembler (again). + + * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to + extractions of signed fields. + +2020-05-26 Stefan Schulze Frielinghaus + + * s390-opc.txt: Relocate vector load/store instructions with + additional alignment parameter and change architecture level + constraint from z14 to z13. + +2020-05-21 Alan Modra + + * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout. + * sparc-dis.c: Likewise. + * tic4x-dis.c: Likewise. + * xtensa-dis.c: Likewise. + * bpf-desc.c: Regenerate. + * epiphany-desc.c: Regenerate. + * fr30-desc.c: Regenerate. + * frv-desc.c: Regenerate. + * ip2k-desc.c: Regenerate. + * iq2000-desc.c: Regenerate. + * lm32-desc.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32r-desc.c: Regenerate. + * mep-asm.c: Regenerate. + * mep-desc.c: Regenerate. + * mt-desc.c: Regenerate. + * or1k-desc.c: Regenerate. + * xc16x-desc.c: Regenerate. + * xstormy16-desc.c: Regenerate. + +2020-05-20 Nelson Chu + + * riscv-opc.c (riscv_ext_version_table): The table used to store + all information about the supported spec and the corresponding ISA + versions. Currently, only Zicsr is supported to verify the + correctness of Z sub extension settings. Others will be supported + in the future patches. + (struct isa_spec_t, isa_specs): List for all supported ISA spec + classes and the corresponding strings. + (riscv_get_isa_spec_class): New function. Get the corresponding ISA + spec class by giving a ISA spec string. + * riscv-opc.c (struct priv_spec_t): New structure. + (struct priv_spec_t priv_specs): List for all supported privilege spec + classes and the corresponding strings. + (riscv_get_priv_spec_class): New function. Get the corresponding + privilege spec class by giving a spec string. + (riscv_get_priv_spec_name): New function. Get the corresponding + privilege spec string by giving a CSR version class. + * riscv-dis.c: Updated since DECLARE_CSR is changed. + * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR + according to the chosen version. Build a hash table riscv_csr_hash to + store the valid CSR for the chosen pirv verison. Dump the direct + CSR address rather than it's name if it is invalid. + (parse_riscv_dis_option_without_args): New function. Parse the options + without arguments. + (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to + parse the options without arguments first, and then handle the options + with arguments. Add the new option -Mpriv-spec, which has argument. + * riscv-dis.c (print_riscv_disassembler_options): Add description + about the new OBJDUMP option. + +2020-05-19 Peter Bergner + + * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new + WC values on POWER10 sync, dcbf and wait instructions. + (insert_pl, extract_pl): New functions. + (L2OPT, LS, WC): Use insert_ls and extract_ls. + (LS3): New , 3-bit L for sync. + (LS3, L3OPT): New, 3-bit L for sync and dcbf. + (SC2, PL): New, 2-bit SC and PL for sync and wait. + (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. + (XOPL3, XWCPL, XSYNCLS): New opcode macros. + (powerpc_opcodes) : New extended mnemonics. + : Enable PL operand on POWER10. + : Enable L3OPT operand on POWER10. + : Enable SC2 operand on POWER10. + +2020-05-19 Stafford Horne + + PR 25184 + * or1k-asm.c: Regenerate. + * or1k-desc.c: Regenerate. + * or1k-desc.h: Regenerate. + * or1k-dis.c: Regenerate. + * or1k-ibld.c: Regenerate. + * or1k-opc.c: Regenerate. + * or1k-opc.h: Regenerate. + * or1k-opinst.c: Regenerate. + +2020-05-11 Alan Modra + + * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, + xsmaxcqp, xsmincqp. + +2020-05-11 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, + stxvrbx, stxvrhx, stxvrwx, stxvrdx. + +2020-05-11 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. + +2020-05-11 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr, + vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr.. + +2020-05-11 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) : New + mnemonics. + +2020-05-11 Alan Modra + + * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. + (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, + vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. + (prefix_opcodes): Add xxeval. + +2020-05-11 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, + xxgenpcvwm, xxgenpcvdm. + +2020-05-11 Alan Modra + + * ppc-opc.c (MP, VXVAM_MASK): Define. + (VXVAPS_MASK): Use VXVA_MASK. + (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm, + vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm, + vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, + vcntmbb, vcntmbh, vcntmbw, vcntmbd. + +2020-05-11 Alan Modra + Peter Bergner + + * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): + New functions. + (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, + YMSK2, XA6a, XA6ap, XB6a entries. + (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define + (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. + (PPCVSX4): Define. + (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, + xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, + xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, + xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, + xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, + xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, + xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. + (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, + pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, + pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, + pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, + pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, + pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, + pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. + +2020-05-11 Alan Modra + + * ppc-opc.c (insert_imm32, extract_imm32): New functions. + (insert_xts, extract_xts): New functions. + (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. + (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. + (VXRC_MASK, VXSH_MASK): Define. + (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, + vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, + vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, + vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, + vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. + (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, + xxblendvh, xxblendvw, xxblendvd, xxpermx. + +2020-05-11 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi, + vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd, + vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd, + vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz, + xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq. + +2020-05-11 Alan Modra + + * ppc-opc.c (insert_xtp, extract_xtp): New functions. + (XTP, DQXP, DQXP_MASK): Define. + (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. + (prefix_opcodes): Add plxvp and pstxvp. + +2020-05-11 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, + vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, + vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. + +2020-05-11 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) : New mnemonics. + +2020-05-11 Peter Bergner + + * ppc-opc.c (insert_l1opt, extract_l1opt): New functions. + (L1OPT): Define. + (powerpc_opcodes) : Add L operand for cpu POWER10. + +2020-05-11 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) : Add variant with L operand. + +2020-05-11 Alan Modra + + * ppc-dis.c (powerpc_init_dialect): Default to "power10". + +2020-05-11 Alan Modra + + * ppc-dis.c (ppc_opts): Add "power10" entry. + (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. + * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses. + +2020-05-11 Nick Clifton + + * po/fr.po: Updated French translation. + +2020-04-30 Alex Coplan + + * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. + * aarch64-opc.c (fields): Add entry for FLD_imm16_2. + (operand_general_constraint_met_p): validate + AARCH64_OPND_UNDEFINED. + * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry + for FLD_imm16_2. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-04-29 Nick Clifton + + PR 22699 + * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC + and SETRC insns. + +2020-04-29 Nick Clifton + + * po/sv.po: Updated Swedish translation. + +2020-04-29 Nick Clifton + + PR 22699 + * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use + IMM0_8S for arithmetic insns and IMM0_8U for logical insns. + * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add + IMM0_8U case. + +2020-04-21 Andreas Schwab + + PR 25848 + * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of + cmpi only on m68020up and cpu32. + +2020-04-20 Sudakshina Das + + * aarch64-asm.c (aarch64_ins_none): New. + * aarch64-asm.h (ins_none): New declaration. + * aarch64-dis.c (aarch64_ext_none): New. + * aarch64-dis.h (ext_none): New declaration. + * aarch64-opc.c (aarch64_print_operand): Update case for + AARCH64_OPND_BARRIER_PSB. + * aarch64-tbl.h (aarch64_opcode_table): Add tsb. + (AARCH64_OPERANDS): Update inserter/extracter for + AARCH64_OPND_BARRIER_PSB to use new dummy functions. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-04-20 Sudakshina Das + + * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. + (aarch64_feature_ras, RAS): Likewise. + (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. + (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, + autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, + autiaz, autiasp, autibz, autibsp to be CORE_INSN. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2020-04-17 Fredrik Strupe + + * arm-dis.c (neon_opcodes): Fix VDUP instruction masks. + (print_insn_neon): Support disassembly of conditional + instructions. + +2020-02-16 David Faust + + * bpf-desc.c: Regenerate. + * bpf-desc.h: Likewise. + * bpf-opc.c: Regenerate. + * bpf-opc.h: Likewise. + +2020-04-07 Lili Cui + + * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1, + (prefix_table): New instructions (see prefixes above). + (rm_table): Likewise + * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS, + CPU_ANY_TSXLDTRK_FLAGS. + (cpu_flags): Add CpuTSXLDTRK. + * i386-opc.h (enum): Add CpuTSXLDTRK. + (i386_cpu_flags): Add cputsxldtrk. + * i386-opc.tbl: Add XSUSPLDTRK insns. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-04-02 Lili Cui + + * i386-dis.c (prefix_table): New instructions serialize. + * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS, + CPU_ANY_SERIALIZE_FLAGS. + (cpu_flags): Add CpuSERIALIZE. + * i386-opc.h (enum): Add CpuSERIALIZE. + (i386_cpu_flags): Add cpuserialize. + * i386-opc.tbl: Add SERIALIZE insns. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2020-03-26 Alan Modra + + * disassemble.h (opcodes_assert): Declare. + (OPCODES_ASSERT): Define. + * disassemble.c: Don't include assert.h. Include opintl.h. + (opcodes_assert): New function. + * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT. + (bfd_h8_disassemble): Reduce size of data array. Correctly + calculate maxlen. Omit insn decoding when insn length exceeds + maxlen. Exit from nibble loop when looking for E, before + accessing next data byte. Move processing of E outside loop. + Replace tests of maxlen in loop with assertions. + +2020-03-26 Alan Modra + + * arc-dis.c (find_format): Init needs_limm. Simplify use of limm. + +2020-03-25 Alan Modra + + * z80-dis.c (suffix): Init mybuf. + +2020-03-22 Alan Modra + + * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that + successflly read from section. + +2020-03-22 Alan Modra + + * arc-dis.c (find_format): Use ISO C string concatenation rather + than line continuation within a string. Don't access needs_limm + before testing opcode != NULL. + +2020-03-22 Alan Modra + + * ns32k-dis.c (print_insn_arg): Update comment. + (print_insn_ns32k): Reduce size of index_offset array, and + initialize, passing -1 to print_insn_arg for args that are not + an index. Don't exit arg loop early. Abort on bad arg number. + +2020-03-22 Alan Modra + + * s12z-dis.c (abstract_read_memory): Don't print error on EOI. + * s12z-opc.c: Formatting. + (operands_f): Return an int. + (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. + (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), + (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), + (exg_sex_discrim): Likewise. + (create_immediate_operand, create_bitfield_operand), + (create_register_operand_with_size, create_register_all_operand), + (create_register_all16_operand, create_simple_memory_operand), + (create_memory_operand, create_memory_auto_operand): Don't + segfault on malloc failure. + (z_ext24_decode): Return an int status, negative on fail, zero + on success. + (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), + (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), + (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), + (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), + (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), + (mov_imm_opr, ld_18bit_decode, exg_sex_decode), + (loop_primitive_decode, shift_decode, psh_pul_decode), + (bit_field_decode): Similarly. + (z_decode_signed_value, decode_signed_value): Similarly. Add arg + to return value, update callers. + (x_opr_decode_with_size): Check all reads, returning NULL on fail. + Don't segfault on NULL operand. + (decode_operation): Return OP_INVALID on first fail. + (decode_s12z): Check all reads, returning -1 on fail. + +2020-03-20 Alan Modra + + * metag-dis.c (print_insn_metag): Don't ignore status from + read_memory_func. + +2020-03-20 Alan Modra + + * nds32-dis.c (print_insn_nds32): Remove unnecessary casts. + Initialize parts of buffer not written when handling a possible + 2-byte insn at end of section. Don't attempt decoding of such + an insn by the 4-byte machinery. + +2020-03-20 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of + partially filled buffer. Prevent lookup of 4-byte insns when + only VLE 2-byte insns are possible due to section size. Print + ".word" rather than ".long" for 2-byte leftovers. + +2020-03-17 Sergey Belyashov + + PR 25641 + * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes. + +2020-03-13 Jan Beulich + + * i386-dis.c (X86_64_0D): Rename to ... + (X86_64_0E): ... this. + +2020-03-09 H.J. Lu + + * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP). + * Makefile.in: Regenerated. + +2020-03-09 Jan Beulich + + * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp* + 3-operand pseudos. + * i386-tbl.h: Re-generate. + +2020-03-09 Jan Beulich + + * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*, + vprot*, vpsha*, and vpshl*. + * i386-tbl.h: Re-generate. + +2020-03-09 Jan Beulich + + * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps, + vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops. + * i386-tbl.h: Re-generate. + +2020-03-09 Jan Beulich + + * i386-gen.c (set_bitfield): Ignore zero-length field names. + * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps, + cmpss, cmppd, and cmpsd 2-operand pseudo-ops. + * i386-tbl.h: Re-generate. + +2020-03-09 Jan Beulich + + * i386-gen.c (struct template_arg, struct template_instance, + struct template_param, struct template, templates, + parse_template, expand_templates): New. + (process_i386_opcodes): Various local variables moved to + expand_templates. Call parse_template and expand_templates. + * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc. + * i386-tbl.h: Re-generate. + +2020-03-06 Jan Beulich + + * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph, + vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate + register and memory source templates. Replace VexW= by VexW* + where applicable. + * i386-tbl.h: Re-generate. + +2020-03-06 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace + VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable. + * i386-tbl.h: Re-generate. + +2020-03-06 Jan Beulich + + * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax. + * i386-tbl.h: Re-generate. + +2020-03-06 Jan Beulich + + * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants. + (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps, + pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use + VexW0 on SSE2AVX variants. + (vmovq): Drop NoRex64 from XMM/XMM variants. + (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb, + vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where + applicable use VexW0. + * i386-tbl.h: Re-generate. + +2020-03-06 Jan Beulich + + * i386-gen.c (opcode_modifiers): Remove Rex64 field. + * i386-opc.h (Rex64): Delete. + (struct i386_opcode_modifier): Remove rex64 field. + * i386-opc.tbl (crc32): Drop Rex64. + Replace Rex64 with Size64 everywhere else. + * i386-tbl.h: Re-generate. + +2020-03-06 Jan Beulich + + * i386-dis.c (OP_E_memory): Exclude recording of used address + prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit + addressed memory operands for MPX insns. + +2020-03-06 Jan Beulich + + * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept, + invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx, + adox, mwaitx, rdpid, movdiri): Add IgnoreSize. + (ptwrite): Split into non-64-bit and 64-bit forms. + * i386-tbl.h: Re-generate. + +2020-03-06 Jan Beulich + + * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand + template. + * i386-tbl.h: Re-generate. + +2020-03-04 Jan Beulich + + * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New. + (prefix_table): Move vmmcall here. Add vmgexit. + (rm_table): Replace vmmcall entry by prefix_table[] escape. + * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry. + (cpu_flags): Add CpuSEV_ES entry. + * i386-opc.h (CpuSEV_ES): New. + (union i386_cpu_flags): Add cpusev_es field. + * i386-opc.tbl (vmgexit): New. + * i386-init.h, i386-tbl.h: Re-generate. + +2020-03-03 H.J. Lu + + * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize + with MnemonicSize. + * i386-opc.h (IGNORESIZE): New. + (DEFAULTSIZE): Likewise. + (IgnoreSize): Removed. + (DefaultSize): Likewise. + (MnemonicSize): New. + (i386_opcode_modifier): Replace ignoresize/defaultsize with + mnemonicsize. + * i386-opc.tbl (IgnoreSize): New. + (DefaultSize): Likewise. + * i386-tbl.h: Regenerated. + +2020-03-03 Sergey Belyashov + + PR 25627 + * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX + instructions. + +2020-03-03 H.J. Lu + + PR gas/25622 + * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, + vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. + * i386-tbl.h: Regenerated. + +2020-02-26 Alan Modra + + * aarch64-asm.c: Indent labels correctly. + * aarch64-dis.c: Likewise. + * aarch64-gen.c: Likewise. + * aarch64-opc.c: Likewise. + * alpha-dis.c: Likewise. + * i386-dis.c: Likewise. + * nds32-asm.c: Likewise. + * nfp-dis.c: Likewise. + * visium-dis.c: Likewise. + +2020-02-25 Claudiu Zissulescu + + * arc-regs.h (int_vector_base): Make it available for all ARC + CPUs. + +2020-02-20 Nelson Chu + + * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is + changed. + +2020-02-19 Nelson Chu + + * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed + c.mv/c.li if rs1 is zero. + +2020-02-17 H.J. Lu + + * i386-gen.c (cpu_flag_init): Replace CpuABM with + CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add + CPU_POPCNT_FLAGS. + (cpu_flags): Remove CpuABM. Add CpuPOPCNT. + * i386-opc.h (CpuABM): Removed. + (CpuPOPCNT): New. + (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. + * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on + popcnt. Remove CpuABM from lzcnt. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2020-02-17 Jan Beulich + + * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss): + Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/ + VexW1 instead of open-coding them. + * i386-tbl.h: Re-generate. + +2020-02-17 Jan Beulich + + * i386-opc.tbl (AddrPrefixOpReg): Define. + (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx, + umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64 + templates. Drop NoRex64. + * i386-tbl.h: Re-generate. + +2020-02-17 Jan Beulich + + PR gas/6518 + * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, + vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms + into Intel syntax instance (with Unpsecified) and AT&T one + (without). + (vcvtneps2bf16): Likewise, along with folding the two so far + separate ones. + * i386-tbl.h: Re-generate. + +2020-02-16 H.J. Lu + + * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from + CPU_ANY_SSE4A_FLAGS. + +2020-02-17 Alan Modra + + * i386-gen.c (cpu_flag_init): Correct last change. + +2020-02-16 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove + CPU_ANY_SSE4_FLAGS. + +2020-02-14 H.J. Lu + + * i386-opc.tbl (movsx): Remove Intel syntax comments. + (movzx): Likewise. + +2020-02-14 Jan Beulich + + PR gas/25438 + * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as + destination for Cpu64-only variant. + (movzx): Fold patterns. + * i386-tbl.h: Re-generate. + +2020-02-13 Jan Beulich + + * i386-gen.c (cpu_flag_init): Move CpuSSE4a from + CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add + CPU_ANY_SSE4_FLAGS entry. + * i386-init.h: Re-generate. + +2020-02-12 Jan Beulich + + * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form + with Unspecified, making the present one AT&T syntax only. + * i386-tbl.h: Re-generate. + +2020-02-12 Jan Beulich + + * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. + * i386-tbl.h: Re-generate. + +2020-02-12 Jan Beulich + + PR gas/24546 + * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. + * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into + Amd64 and Intel64 templates. + (call, jmp): Likewise for far indirect variants. Dro + Unspecified. + * i386-tbl.h: Re-generate. + +2020-02-11 Jan Beulich + + * i386-gen.c (opcode_modifiers): Remove ShortForm entry. + * i386-opc.h (ShortForm): Delete. + (struct i386_opcode_modifier): Remove shortform field. + * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, + fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, + fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, + ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): + Drop ShortForm. + * i386-tbl.h: Re-generate. + +2020-02-11 Jan Beulich + + * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, + fucompi): Drop ShortForm from operand-less templates. + * i386-tbl.h: Re-generate. + +2020-02-11 Alan Modra + + * cgen-ibld.in (extract_normal): Set *valuep on all return paths. + * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, + * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, + * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, + * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. + +2020-02-10 Matthew Malcomson + + * arm-dis.c (print_insn_cde): Define 'V' parse character. + (cde_opcodes): Add VCX* instructions. + +2020-02-10 Stam Markianos-Wright + Matthew Malcomson + + * arm-dis.c (struct cdeopcode32): New. + (CDE_OPCODE): New macro. + (cde_opcodes): New disassembly table. + (regnames): New option to table. + (cde_coprocs): New global variable. + (print_insn_cde): New + (print_insn_thumb32): Use print_insn_cde. + (parse_arm_disassembler_options): Parse coprocN args. + +2020-02-10 H.J. Lu + + PR gas/25516 + * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 + with ISA64. + * i386-opc.h (AMD64): Removed. + (Intel64): Likewose. + (AMD64): New. + (INTEL64): Likewise. + (INTEL64ONLY): Likewise. + (i386_opcode_modifier): Replace amd64 and intel64 with isa64. + * i386-opc.tbl (Amd64): New. + (Intel64): Likewise. + (Intel64Only): Likewise. + Replace AMD64 with Amd64. Update sysenter/sysenter with + Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. + * i386-tbl.h: Regenerated. + +2020-02-07 Sergey Belyashov + + PR 25469 + * z80-dis.c: Add support for GBZ80 opcodes. + 2020-02-04 Alan Modra * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.