X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=63271f2dd89e6fae890ee18c0eb6bfb17307df5e;hb=ab3b8fcfdb06695d27eaec4eedb019ada4a5713e;hp=2e2aaf5cb21fcd30cad6448bbb6f5b13534dd818;hpb=16a1fa25be5705102b84ef0ea6eea71312328c2c;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2e2aaf5cb2..63271f2dd8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,943 @@ +2016-09-21 Richard Sandiford + + * aarch64-opc.c (operand_general_constraint_met_p): Use "must be" + rather than "should be" or "expected to be" in error messages. + +2016-09-21 Richard Sandiford + + * aarch64-dis.c (remove_dot_suffix): New function, split out from... + (print_mnemonic_name): ...here. + (print_comment): New function. + (print_aarch64_insn): Call it. + * aarch64-opc.c (aarch64_conds): Add SVE names. + (aarch64_print_operand): Print alternative condition names in + a comment. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) + (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) + (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) + (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) + (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) + (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) + (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) + (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) + (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) + (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) + (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) + (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) + (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) + (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) + (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) + (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) + (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) + (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) + (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) + (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) + (OP_SVE_XWU, OP_SVE_XXU): New macros. + (aarch64_feature_sve): New variable. + (SVE): New macro. + (_SVE_INSN): Likewise. + (aarch64_opcode_table): Add SVE instructions. + * aarch64-opc.h (extract_fields): Declare. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.c (extract_fields): Make global. + (do_misc_decoding): Handle the new SVE aarch64_ops. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) + (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New + aarch64_field_kinds. + * aarch64-opc.c (fields): Add corresponding entries. + * aarch64-asm.c (aarch64_get_variant): New function. + (aarch64_encode_variant_using_iclass): Likewise. + (aarch64_opcode_encode): Call it. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. + (aarch64_opcode_decode): Call it. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core + and FP register operands. + * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm) + (FLD_SVE_Vn): New aarch64_field_kinds. + * aarch64-opc.c (fields): Add corresponding entries. + (aarch64_print_operand): Handle the new SVE core and FP register + operands. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm-2.c: Likewise. + * aarch64-dis-2.c: Likewise. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP + immediate operands. + * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. + * aarch64-opc.c (fields): Add corresponding entry. + (operand_general_constraint_met_p): Handle the new SVE FP immediate + operands. + (aarch64_print_operand): Likewise. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) + (ins_sve_float_zero_one): New inserters. + * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. + (aarch64_ins_sve_float_half_two): Likewise. + (aarch64_ins_sve_float_zero_one): Likewise. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) + (ext_sve_float_zero_one): New extractors. + * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. + (aarch64_ext_sve_float_half_two): Likewise. + (aarch64_ext_sve_float_zero_one): Likewise. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE + integer immediate operands. + * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) + (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) + (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. + * aarch64-opc.c (fields): Add corresponding entries. + (operand_general_constraint_met_p): Handle the new SVE integer + immediate operands. + (aarch64_print_operand): Likewise. + (aarch64_sve_dupm_mov_immediate_p): New function. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) + (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. + * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... + (aarch64_ins_limm): ...here. + (aarch64_ins_inv_limm): New function. + (aarch64_ins_sve_aimm): Likewise. + (aarch64_ins_sve_asimm): Likewise. + (aarch64_ins_sve_limm_mov): Likewise. + (aarch64_ins_sve_shlimm): Likewise. + (aarch64_ins_sve_shrimm): Likewise. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) + (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. + * aarch64-dis.c (decode_limm): New function, split out from... + (aarch64_ext_limm): ...here. + (aarch64_ext_inv_limm): New function. + (decode_sve_aimm): Likewise. + (aarch64_ext_sve_aimm): Likewise. + (aarch64_ext_sve_asimm): Likewise. + (aarch64_ext_sve_limm_mov): Likewise. + (aarch64_top_bit): Likewise. + (aarch64_ext_sve_shlimm): Likewise. + (aarch64_ext_sve_shrimm): Likewise. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL + operands. + * aarch64-opc.c (aarch64_operand_modifiers): Initialize + the AARCH64_MOD_MUL_VL entry. + (value_aligned_p): Cope with non-power-of-two alignments. + (operand_general_constraint_met_p): Handle the new MUL VL addresses. + (print_immediate_offset_address): Likewise. + (aarch64_print_operand): Likewise. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) + (ins_sve_addr_ri_s9xvl): New inserters. + * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. + (aarch64_ins_sve_addr_ri_s6xvl): Likewise. + (aarch64_ins_sve_addr_ri_s9xvl): Likewise. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) + (ext_sve_addr_ri_s9xvl): New extractors. + * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. + (aarch64_ext_sve_addr_ri_s4xvl): Likewise. + (aarch64_ext_sve_addr_ri_s6xvl): Likewise. + (aarch64_ext_sve_addr_ri_s9xvl): Likewise. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE + address operands. + * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) + (FLD_SVE_xs_22): New aarch64_field_kinds. + (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. + (get_operand_specific_data): New function. + * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, + FLD_SVE_xs_14 and FLD_SVE_xs_22. + (operand_general_constraint_met_p): Handle the new SVE address + operands. + (sve_reg): New array. + (get_addr_sve_reg_name): New function. + (aarch64_print_operand): Handle the new SVE address operands. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) + (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) + (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. + * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. + (aarch64_ins_sve_addr_rr_lsl): Likewise. + (aarch64_ins_sve_addr_rz_xtw): Likewise. + (aarch64_ins_sve_addr_zi_u5): Likewise. + (aarch64_ins_sve_addr_zz): Likewise. + (aarch64_ins_sve_addr_zz_lsl): Likewise. + (aarch64_ins_sve_addr_zz_sxtw): Likewise. + (aarch64_ins_sve_addr_zz_uxtw): Likewise. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) + (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) + (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. + * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. + (aarch64_ext_sve_addr_ri_u6): Likewise. + (aarch64_ext_sve_addr_rr_lsl): Likewise. + (aarch64_ext_sve_addr_rz_xtw): Likewise. + (aarch64_ext_sve_addr_zi_u5): Likewise. + (aarch64_ext_sve_addr_zz): Likewise. + (aarch64_ext_sve_addr_zz_lsl): Likewise. + (aarch64_ext_sve_addr_zz_sxtw): Likewise. + (aarch64_ext_sve_addr_zz_uxtw): Likewise. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for + AARCH64_OPND_SVE_PATTERN_SCALED. + * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. + * aarch64-opc.c (fields): Add a corresponding entry. + (set_multiplier_out_of_range_error): New function. + (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. + (operand_general_constraint_met_p): Handle + AARCH64_OPND_SVE_PATTERN_SCALED. + (print_register_offset_address): Use PRIi64 to print the + shift amount. + (aarch64_print_operand): Likewise. Handle + AARCH64_OPND_SVE_PATTERN_SCALED. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.h (ins_sve_scale): New inserter. + * aarch64-asm.c (aarch64_ins_sve_scale): New function. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_sve_scale): New inserter. + * aarch64-dis.c (aarch64_ext_sve_scale): New function. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for + AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. + * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. + (FLD_SVE_prfop): Likewise. + * aarch64-opc.c: Include libiberty.h. + (aarch64_sve_pattern_array): New variable. + (aarch64_sve_prfop_array): Likewise. + (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. + (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and + AARCH64_OPND_SVE_PRFOP. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for + AARCH64_OPND_QLF_P_[ZM]. + (aarch64_print_operand): Print /z and /m where appropriate. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. + * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) + (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) + (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) + (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. + * aarch64-opc.c (fields): Add corresponding entries here. + (operand_general_constraint_met_p): Check that SVE register lists + have the correct length. Check the ranges of SVE index registers. + Check for cases where p8-p15 are used in 3-bit predicate fields. + (aarch64_print_operand): Handle the new SVE operands. + * aarch64-opc-2.c: Regenerate. + * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. + * aarch64-asm.c (aarch64_ins_sve_index): New function. + (aarch64_ins_sve_reglist): Likewise. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. + * aarch64-dis.c (aarch64_ext_sve_index): New function. + (aarch64_ext_sve_reglist): Likewise. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN) + (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN) + (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field. + * aarch64-opc.c (aarch64_match_operands_constraint): Check for + tied operands. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (get_offset_int_reg_name): New function. + (print_immediate_offset_address): Likewise. + (print_register_offset_address): Take the base and offset + registers as parameters. + (aarch64_print_operand): Update caller accordingly. Use + print_immediate_offset_address. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (BANK): New macro. + (R32, R64): Take a register number as argument + (int_reg): Use BANK. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (print_register_list): Add a prefix parameter. + (aarch64_print_operand): Update accordingly. + +2016-09-21 Richard Sandiford + + * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm + for FPIMM. + * aarch64-asm.h (ins_fpimm): New inserter. + * aarch64-asm.c (aarch64_ins_fpimm): New function. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_fpimm): New extractor. + * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. + (aarch64_ext_fpimm): New function. + * aarch64-dis-2.c: Regenerate. + +2016-09-21 Richard Sandiford + + * aarch64-asm.c: Include libiberty.h. + (insert_fields): New function. + (aarch64_ins_imm): Use it. + * aarch64-dis.c (extract_fields): New function. + (aarch64_ext_imm): Use it. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32 + with an esize parameter. + (operand_general_constraint_met_p): Update accordingly. + Fix misindented code. + * aarch64-asm.c (aarch64_ins_limm): Update call to + aarch64_logical_immediate_p. + +2016-09-21 Richard Sandiford + + * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. + +2016-09-21 Richard Sandiford + + * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit. + +2016-09-15 Claudiu Zissulescu + + * arc-dis.c (find_format): Walk the linked list pointed by einsn. + +2016-09-14 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) : New mnemonic. + : Delete mnemonics. + : Rename mnemonic from ... + : ...to this. + : Change to a X form instruction. + : Change to 1 operand form. + : Delete mnemonic. + : Rename mnemonic from ... + : ...to this. + : Delete mnemonics. + : Rename mnemonic from ... + : ...to this. + +2016-09-14 Anton Kolesov + + * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully. + +2016-09-12 Andreas Krebbel + + * s390-mkopc.c (main): Support alternate arch strings. + +2016-09-12 Patrick Steuer + + * s390-opc.txt: Fix kmctr instruction type. + +2016-09-07 H.J. Lu + + * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS. + * i386-init.h: Regenerated. + +2016-08-30 Cupertino Miranda + + * opcodes/arc-dis.c (print_insn_arc): Changed. + +2016-08-26 Jose E. Marchesi + + * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi -> + camellia_fl. + +2016-08-26 Thomas Preud'homme + + * arm-dis.c (psr_name): Use hex as case labels. Add detection for + MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, + FAULTMASK_NS, CONTROL_NS and SP_NS special registers. + +2016-08-24 H.J. Lu + + * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. + (PREFIX_MOD_3_0FAE_REG_4): Likewise. + (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and + PREFIX_MOD_3_0FAE_REG_4. + (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and + PREFIX_MOD_3_0FAE_REG_4. + * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. + (cpu_flags): Add CpuPTWRITE. + * i386-opc.h (CpuPTWRITE): New. + (i386_cpu_flags): Add cpuptwrite. + * i386-opc.tbl: Add ptwrite instruction. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2016-08-24 Anton Kolesov + + * arc-dis.h: Wrap around in extern "C". + +2016-08-23 Richard Sandiford + + * aarch64-tbl.h (V8_2_INSN): New macro. + (aarch64_opcode_table): Use it. + +2016-08-23 Richard Sandiford + + * aarch64-tbl.h (aarch64_opcode_table): Make more use of + CORE_INSN, __FP_INSN and SIMD_INSN. + +2016-08-23 Richard Sandiford + + * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter. + (aarch64_opcode_table): Update uses accordingly. + +2016-07-25 Andrew Jenner + Kwok Cheung Yeung + + opcodes/ + * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and + 'e_cmplwi' to 'e_cmpli' instead. + (OPVUPRT, OPVUPRT_MASK): Define. + (powerpc_opcodes): Add E200Z4 insns. + (vle_opcodes): Add context save/restore insns. + +2016-07-27 Maciej W. Rozycki + + * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", + "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to + "j". + +2016-07-27 Graham Markall + + * arc-nps400-tbl.h: Change block comments to GNU format. + * arc-dis.c: Add new globals addrtypenames, + addrtypenames_max, and addtypeunknown. + (get_addrtype): New function. + (print_insn_arc): Print colons and address types when + required. + * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to + define insert and extract functions for all address types. + (arc_operands): Add operands for colon and all address + types. + * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. + * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, + insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. + * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. + * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, + insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. + +2016-07-21 H.J. Lu + + * configure: Regenerated. + +2016-07-20 Claudiu Zissulescu + + * arc-dis.c (skipclass): New structure. + (decodelist): New variable. + (is_compatible_p): New function. + (new_element): Likewise. + (skip_class_p): Likewise. + (find_format_from_table): Use skip_class_p function. + (find_format): Decode first the extension instructions. + (print_insn_arc): Select either ARCEM or ARCHS based on elf + e_flags. + (parse_option): New function. + (parse_disassembler_options): Likewise. + (print_arc_disassembler_options): Likewise. + (print_insn_arc): Use parse_disassembler_options function. Proper + select ARCv2 cpu variant. + * disassemble.c (disassembler_usage): Add ARC disassembler + options. + +2016-07-13 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS + annotation from the "nal" entry and reorder it beyond "bltzal". + +2016-07-12 Jose E. Marchesi + + * sparc-opc.c (ldtxa): New macro. + (sparc_opcodes): Use the macro defined above to add entries for + the LDTXA instructions. + (asi_table): Add the ASI_TWINX_* asis used in the LDTXA + instruction. + +2016-07-07 James Bowman + + * ft32-opc.c (ft32_opc_info): Correct mask for "callc" + and "jmpc". + +2016-07-01 Jan Beulich + + * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove. + (movzb): Adjust to cover all permitted suffixes. + (movzw): New. + * i386-tbl.h: Re-generate. + +2016-07-01 Jan Beulich + + * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant. + (lgdt): Remove Tbyte from non-64-bit variant. + (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64, + xsaves64, xsavec64): Remove Disp16. + (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd): + Remove Disp32S from non-64-bit variants. Remove Disp16 from + 64-bit variants. + (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd, + vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi, + vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from + 64-bit variants. + * i386-tbl.h: Re-generate. + +2016-07-01 Jan Beulich + + * i386-opc.tbl (xlat): Remove RepPrefixOk. + * i386-tbl.h: Re-generate. + +2016-06-30 Yao Qi + + * arm-dis.c (print_insn): Fix typo in comment. + +2016-06-28 Richard Sandiford + + * aarch64-opc.c (operand_general_constraint_met_p): Check the + range of ldst_elemlist operands. + (print_register_list): Use PRIi64 to print the index. + (aarch64_print_operand): Likewise. + +2016-06-25 Trevor Saunders + + * mcore-opc.h: Remove sentinal. + * mcore-dis.c (print_insn_mcore): Adjust. + +2016-06-23 Graham Markall + + * arc-opc.c: Correct description of availability of NPS400 + features. + +2016-06-22 Peter Bergner + + * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. + (powerpc_opcodes) : New mnemonics. + : Change to a VX form instruction. + (insert_sh6): Add support for rldixor. + (extract_sh6): Likewise. + +2016-06-22 Trevor Saunders + + * arc-ext.h: Wrap in extern C. + +2016-06-21 Graham Markall + + * arc-dis.c (arc_insn_length): Add comment on instruction length. + Use same method for determining instruction length on ARC700 and + NPS-400. + (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. + * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions + with the NPS400 subclass. + * arc-opc.c: Likewise. + +2016-06-17 Jose E. Marchesi + + * sparc-opc.c (rdasr): New macro. + (wrasr): Likewise. + (rdpr): Likewise. + (wrpr): Likewise. + (rdhpr): Likewise. + (wrhpr): Likewise. + (sparc_opcodes): Use the macros above to fix and expand the + definition of read/write instructions from/to + asr/privileged/hyperprivileged instructions. + * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and + %hva_mask_nz. Prefer softint_set and softint_clear over + set_softint and clear_softint. + (print_insn_sparc): Support %ver in Rd. + +2016-06-17 Jose E. Marchesi + + * sparc-opc.c (sparc_opcodes): Adjust instructions opcode + architecture according to the hardware capabilities they require. + +2016-06-17 Jose E. Marchesi + + * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. + (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and + bfd_mach_sparc_v9{c,d,e,v,m}. + * sparc-opc.c (MASK_V9C): Define. + (MASK_V9D): Likewise. + (MASK_V9E): Likewise. + (MASK_V9V): Likewise. + (MASK_V9M): Likewise. + (v6): Add MASK_V9{C,D,E,V,M}. + (v6notlet): Likewise. + (v7): Likewise. + (v8): Likewise. + (v9): Likewise. + (v9andleon): Likewise. + (v9a): Likewise. + (v9b): Likewise. + (v9c): Define. + (v9d): Likewise. + (v9e): Likewise. + (v9v): Likewise. + (v9m): Likewise. + (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}. + +2016-06-15 Nick Clifton + + * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer + constants to match expected behaviour. + (nds32_parse_opcode): Likewise. Also for whitespace. + +2016-06-15 Andrew Burgess + + * arc-opc.c (extract_rhv1): Extract value from insn. + +2016-06-14 Graham Markall + + * arc-nps400-tbl.h: Add ldbit instruction. + * arc-opc.c: Add flag classes required for ldbit. + +2016-06-14 Graham Markall + + * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf + * arc-opc.c: Add flag classes, insert/extract functions, and operands to + support the above instructions. + +2016-06-14 Graham Markall + + * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb, + imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms, + csma, cbba, zncv, and hofs. + * arc-opc.c: Add flag classes, insert/extract functions, and operands to + support the above instructions. + +2016-06-06 Graham Markall + + * arc-nps400-tbl.h: Add andab and orab instructions. + +2016-06-06 Graham Markall + + * arc-nps400-tbl.h: Add addl-like instructions. + +2016-06-06 Graham Markall + + * arc-nps400-tbl.h: Add mxb and imxb instructions. + +2016-06-06 Graham Markall + + * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey + instructions. + +2016-06-10 Andreas Krebbel + + * s390-dis.c (option_use_insn_len_bits_p): New file scope + variable. + (init_disasm): Handle new command line option "insnlength". + (print_s390_disassembler_options): Mention new option in help + output. + (print_insn_s390): Use the encoded insn length when dumping + unknown instructions. + +2016-06-03 Pitchumani Sivanupandi + + * avr-dis.c (avr_operand): Add default data address space origin (0x800000) + to the address and set as symbol address for LDS/ STS immediate operands. + +2016-06-07 Alan Modra + + * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default + cpu for "vle" to e500. + * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. + (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. + (PPCNONE): Delete, substitute throughout. + (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" + except for major opcode 4 and 31. + (vle_opcodes ): Add PPCRFMCI to flags. + +2016-06-07 Matthew Wahab + + * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with + ARM_EXT_RAS in relevant entries. + +2016-06-03 Peter Bergner + + PR binutils/20196 + * ppc-opc.c (powerpc_opcodes ): Enable + opcodes for E6500. + +2016-06-03 H.J. Lu + + PR binutis/18386 + * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. + (indir_v_mode): New. + Add comments for '&'. + (reg_table): Replace "{T|}" with "{&|}" on call and jmp. + (putop): Handle '&'. + (intel_operand_size): Handle indir_v_mode. + (OP_E_register): Likewise. + * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add + 64-bit indirect call/jmp for AMD64. + * i386-tbl.h: Regenerated + +2016-06-02 Andrew Burgess + + * arc-dis.c (struct arc_operand_iterator): New structure. + (find_format_from_table): All the old content from find_format, + with some minor adjustments, and parameter renaming. + (find_format_long_instructions): New function. + (find_format): Rewritten. + (arc_insn_length): Add LSB parameter. + (extract_operand_value): New function. + (operand_iterator_next): New function. + (print_insn_arc): Use new functions to find opcode, and iterator + over operands. + * arc-opc.c (insert_nps_3bit_dst_short): New function. + (extract_nps_3bit_dst_short): New function. + (insert_nps_3bit_src2_short): New function. + (extract_nps_3bit_src2_short): New function. + (insert_nps_bitop1_size): New function. + (extract_nps_bitop1_size): New function. + (insert_nps_bitop2_size): New function. + (extract_nps_bitop2_size): New function. + (insert_nps_bitop_mod4_msb): New function. + (extract_nps_bitop_mod4_msb): New function. + (insert_nps_bitop_mod4_lsb): New function. + (extract_nps_bitop_mod4_lsb): New function. + (insert_nps_bitop_dst_pos3_pos4): New function. + (extract_nps_bitop_dst_pos3_pos4): New function. + (insert_nps_bitop_ins_ext): New function. + (extract_nps_bitop_ins_ext): New function. + (arc_operands): Add new operands. + (arc_long_opcodes): New global array. + (arc_num_long_opcodes): New global. + * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes. + +2016-06-01 Trevor Saunders + + * nds32-asm.h: Add extern "C". + * sh-opc.h: Likewise. + +2016-06-01 Graham Markall + + * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and + 0,b,limm to the rflt instruction. + +2016-05-31 Trevor Saunders + + * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned + constant. + +2016-05-29 H.J. Lu + + PR gas/20145 + * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, + CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, + CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, + CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, + CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. + * i386-init.h: Regenerated. + +2016-05-27 H.J. Lu + + PR gas/20145 + * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove + CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from + CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. + Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and + CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from + CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, + CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. + Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, + CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, + CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, + CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX + for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable + CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and + CpuRegMask for AVX512. + (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM + and CpuRegMask. + (set_bitfield_from_cpu_flag_init): New function. + (set_bitfield): Remove const on f. Call + set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. + * i386-opc.h (CpuRegMMX): New. + (CpuRegXMM): Likewise. + (CpuRegYMM): Likewise. + (CpuRegZMM): Likewise. + (CpuRegMask): Likewise. + (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm + and cpuregmask. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2016-05-27 H.J. Lu + + PR gas/20154 + * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. + (opcode_modifiers): Add AMD64 and Intel64. + (main): Properly verify CpuMax. + * i386-opc.h (CpuAMD64): Removed. + (CpuIntel64): Likewise. + (CpuMax): Set to CpuNo64. + (i386_cpu_flags): Remove cpuamd64 and cpuintel64. + (AMD64): New. + (Intel64): Likewise. + (i386_opcode_modifier): Add amd64 and intel64. + (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 + on call and jmp. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2016-05-27 H.J. Lu + + PR gas/20154 + * i386-gen.c (main): Fail if CpuMax is incorrect. + * i386-opc.h (CpuMax): Set to CpuIntel64. + * i386-tbl.h: Regenerated. + +2016-05-27 Nick Clifton + + PR target/20150 + * msp430-dis.c (msp430dis_read_two_bytes): New function. + (msp430dis_opcode_unsigned): New function. + (msp430dis_opcode_signed): New function. + (msp430_singleoperand): Use the new opcode reading functions. + Only disassenmble bytes if they were successfully read. + (msp430_doubleoperand): Likewise. + (msp430_branchinstr): Likewise. + (msp430x_callx_instr): Likewise. + (print_insn_msp430): Check that it is safe to read bytes before + attempting disassembly. Use the new opcode reading functions. + +2016-05-26 Peter Bergner + + * ppc-opc.c (CY): New define. Document it. + (powerpc_opcodes) : New mnemonics. + +2016-05-25 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, + CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS + and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, + CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to + CPU_ANY_AVX_FLAGS. + * i386-init.h: Regenerated. + +2016-05-25 H.J. Lu + + PR gas/20141 + * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, + CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. + * i386-init.h: Regenerated. + +2016-05-25 H.J. Lu + + * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to + CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. + * i386-init.h: Regenerated. + +2016-05-23 Claudiu Zissulescu + + * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type + information. + (print_insn_arc): Set insn_type information. + * arc-opc.c (C_CC): Add F_CLASS_COND. + * arc-tbl.h (bbit0, bbit1): Update subclass to COND. + (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. + (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. + (breq, breq_s, brge, brhs, brlo, brlt): Likewise. + (brne, brne_s, jeq_s, jne_s): Likewise. + +2016-05-23 Claudiu Zissulescu + + * arc-tbl.h (neg): New instruction variant. + +2016-05-23 Cupertino Miranda + + * arc-dis.c (find_format, find_format, get_auxreg) + (print_insn_arc): Changed. + * arc-ext.h (INSERT_XOP): Likewise. + +2016-05-23 Trevor Saunders + + * tic54x-dis.c (sprint_mmr): Adjust. + * tic54x-opc.c: Likewise. + +2016-05-19 Alan Modra + + * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi. + +2016-05-19 Alan Modra + + * ppc-opc.c: Formatting. + (NSISIGNOPT): Define. + (powerpc_opcodes ): Use NSISIGNOPT. + +2016-05-18 Maciej W. Rozycki + + * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, + replacing references to `micromips_ase' throughout. + (_print_insn_mips): Don't use file-level microMIPS annotation to + determine the disassembly mode with the symbol table. + +2016-05-13 Peter Bergner + + * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. + +2016-05-11 Andrew Bennett + + * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and + mips64r6. + * mips-opc.c (D34): New macro. + (mips_builtin_opcodes): Define bposge32c for DSPr3. + +2016-05-10 Alexander Fomin + + * i386-dis.c (prefix_table): Add RDPID instruction. + * i386-gen.c (cpu_flag_init): Add RDPID flag. + (cpu_flags): Add RDPID bitfield. + * i386-opc.h (enum): Add RDPID element. + (i386_cpu_flags): Add RDPID field. + * i386-opc.tbl: Add RDPID instruction. + * i386-init.h: Regenerate. + * i386-tbl.h: Regenerate. + +2016-05-10 Thomas Preud'homme + + * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get + branch type of a symbol. + (print_insn): Likewise. + 2016-05-10 Thomas Preud'homme * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M