X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=7c06b8f91be005d1a76b83e03650bcd5eeeede3e;hb=0a40490e6aa43a28c471f4db8a18a4820cbf58c3;hp=8a575af3ebf62712598a2a5b0a82174b8ac691e2;hpb=7ffdda930bd033f3d6205f3694e9ea0a2755187d;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8a575af3eb..7c06b8f91b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,7 +1,663 @@ +2005-02-07 Jim Blandy + + * Makefile.am (CGEN): Load guile.scm before calling the main + application script. + * Makefile.in: Regenerated. + * cgen.sh: Be prepared for the 'cgen' argument to contain spaces. + Simply pass the cgen-opc.scm path to ${cgen} as its first + argument; ${cgen} itself now contains the '-s', or whatever is + appropriate for the Scheme being used. + +2005-01-31 Andrew Cagney + + * configure: Regenerate to track ../gettext.m4. + +2005-01-31 Jan Beulich + + * ia64-gen.c (NELEMS): Define. + (shrink): Generate alias with missing second predicate register when + opcode has two outputs and these are both predicates. + * ia64-opc-i.c (FULL17): Define. + (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17 + here to generate output template. + (TBITCM, TNATCM): Undefine after use. + * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as + first input. Add ld16 aliases without ar.csd as second output. Add + st16 aliases without ar.csd as second input. Add cmpxchg aliases + without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/ + ar.ccv as third/fourth inputs. Consolidate through... + (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8, + CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define. + * ia64-asmtab.c: Regenerate. + +2005-01-27 Andrew Cagney + + * configure: Regenerate to track ../gettext.m4 change. + +2005-01-25 Alexandre Oliva + + 2004-11-10 Alexandre Oliva + * frv-asm.c: Rebuilt. + * frv-desc.c: Rebuilt. + * frv-desc.h: Rebuilt. + * frv-dis.c: Rebuilt. + * frv-ibld.c: Rebuilt. + * frv-opc.c: Rebuilt. + * frv-opc.h: Rebuilt. + +2005-01-24 Andrew Cagney + + * configure: Regenerate, ../gettext.m4 was updated. + +2005-01-21 Fred Fish + + * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS. + Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. + Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. + * mips-dis.c: Ditto. + +2005-01-20 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel. + +2005-01-19 Fred Fish + + * mips-dis.c (no_aliases): New disassembly option flag. + (set_default_mips_dis_options): Init no_aliases to zero. + (parse_mips_dis_option): Handle no-aliases option. + (print_insn_mips): Ignore table entries that are aliases + if no_aliases is set. + (print_insn_mips16): Ditto. + * mips-opc.c (mips_builtin_opcodes): Add initializer column for + new pinfo2 member and add INSN_ALIAS initializers as needed. Also + move WR_MACC and RD_MACC initializers from pinfo to pinfo2. + * mips16-opc.c (mips16_opcodes): Ditto. + +2005-01-17 Andrew Stubbs + + * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition. + (inheritance diagram): Add missing edge. + (arch_sh1_up): Rename arch_sh_up to match external name to make life + easier for the testsuite. + (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up. + (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up. + (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing + arch_sh2a_or_sh4_up child. + (sh_table): Do renaming as above. + Correct comment for ldc.l for gas testsuite to read. + Remove rogue mul.l from sh1 (duplicate of the one for sh2). + Correct comments for movy.w and movy.l for gas testsuite to read. + Correct comments for fmov.d and fmov.s for gas testsuite to read. + +2005-01-12 H.J. Lu + + * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode. + +2005-01-12 H.J. Lu + + * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB. + +2005-01-10 Andreas Schwab + + * disassemble.c (disassemble_init_for_target) : Set skip_zeroes to 16. + : Set skip_zeroes to 32. + +2004-12-23 Tomer Levi + + * crx-opc.c: Mark 'bcop' instruction as RELAXABLE. + +2004-12-14 Svein E. Seldal + + * avr-dis.c: Prettyprint. Added printing of symbol names in all + memory references. Convert avr_operand() to C90 formatting. + +2004-12-05 Tomer Levi + + * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing. + +2004-11-29 Tomer Levi + + * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed. + (no_op_insn): Initialize array with instructions that have no + operands. + * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping. + +2004-11-29 Richard Earnshaw + + * arm-dis.c: Correct top-level comment. + +2004-11-27 Richard Earnshaw + + * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the + architecuture defining the insn. + (arm_opcodes, thumb_opcodes): Delete. Move to ... + * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre + field. + Also include opcode/arm.h. + * Makefile.am (arm-dis.lo): Update dependency list. + * Makefile.in: Regenerate. + +2004-11-22 Ravi Ramaseshan + + * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to + reflect the change to the short immediate syntax. + +2004-11-19 Alan Modra + + * or32-opc.c (debug): Warning fix. + * po/POTFILES.in: Regenerate. + + * maxq-dis.c: Formatting. + (print_insn): Warning fix. + +2004-11-17 Daniel Jacobowitz + + * arm-dis.c (WORD_ADDRESS): Define. + (print_insn): Use it. Correct big-endian end-of-section handling. + +2004-11-08 Inderpreet Singh + Vineet Sharma + + * maxq-dis.c: New file. + * disassemble.c (ARCH_maxq): Define. + (disassembler): Add 'print_insn_maxq_little' for handling maxq + instructions.. + * configure.in: Add case for bfd_maxq_arch. + * configure: Regenerate. + * Makefile.am: Add support for maxq-dis.c + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + +2004-11-05 Tomer Levi + + * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register + mode. + * crx-dis.c: Likewise. + +2004-11-04 Hans-Peter Nilsson + + Generally, handle CRISv32. + * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case). + (struct cris_disasm_data): New type. + (format_reg, format_hex, cris_constraint, print_flags) + (get_opcode_entry): Add struct cris_disasm_data * parameter. All + callers changed. + (format_sup_reg, print_insn_crisv32_with_register_prefix) + (print_insn_crisv32_without_register_prefix) + (print_insn_crisv10_v32_with_register_prefix) + (print_insn_crisv10_v32_without_register_prefix) + (cris_parse_disassembler_options): New functions. + (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family + parameter. All callers changed. + (get_opcode_entry): Call malloc, not xmalloc. Return NULL on + failure. + (cris_constraint) : New cases. + (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes + for constraint 'n'. + (print_with_operands) : New case. + (print_with_operands) + : New cases. + (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32. + (print_insn_cris_with_register_prefix) + (print_insn_cris_without_register_prefix): Call + cris_parse_disassembler_options. + * cris-opc.c (cris_spec_regs): Mention that this table isn't used + for CRISv32 and the size of immediate operands. New v32-only + entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and + spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change + ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10. + Change brp to be v3..v10. + (cris_support_regs): New vector. + (cris_opcodes): Update head comment. New format characters '[', + ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'. + Add new opcodes for v32 and adjust existing opcodes to accommodate + differences to earlier variants. + (cris_cond15s): New vector. + +2004-11-04 Jan Beulich + + * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define. + (indirEb): Remove. + (Mp): Use f_mode rather than none at all. + (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode + replaces what previously was x_mode; x_mode now means 128-bit SSE + operands. + (dis386): Make far jumps and calls have an 'l' prefix only in AT&T + mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq. + pinsrw's second operand is Edqw. + (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's + operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt, + fldenv, frstor, fsave, fstenv all should also have suffixes in Intel + mode when an operand size override is present or always suffixing. + More instructions will need to be added to this group. + (putop): Handle new macro chars 'C' (short/long suffix selector), + 'I' (Intel mode override for following macro char), and 'J' (for + adding the 'l' prefix to far branches in AT&T mode). When an + alternative was specified in the template, honor macro character when + specified for Intel mode. + (OP_E): Handle new *_mode values. Correct pointer specifications for + memory operands. Consolidate output of index register. + (OP_G): Handle new *_mode values. + (OP_I): Handle const_1_mode. + (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate + respective opcode prefix bits have been consumed. + (OP_EM, OP_EX): Provide some default handling for generating pointer + specifications. + +2004-10-28 Tomer Levi + + * crx-opc.c (REV_COP_INST): New macro, reverse operand order of + COP_INST macro. + +2004-10-27 Tomer Levi + + * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE. + (getregliststring): Support HI/LO and user registers. + * crx-opc.c (crx_instruction): Update data structure according to the + rearrangement done in CRX opcode header file. + (crx_regtab): Likewise. + (crx_optab): Likewise. + (crx_instruction): Reorder load/stor instructions, remove unsupported + formats. + support new Co-Processor instruction 'cpi'. + +2004-10-27 Nick Clifton + + * opcodes/iq2000-asm.c: Regenerate. + * opcodes/iq2000-desc.c: Regenerate. + * opcodes/iq2000-desc.h: Regenerate. + * opcodes/iq2000-dis.c: Regenerate. + * opcodes/iq2000-ibld.c: Regenerate. + * opcodes/iq2000-opc.c: Regenerate. + * opcodes/iq2000-opc.h: Regenerate. + +2004-10-21 Tomer Levi + + * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3, + us4, us5 (respectively). + Remove unsupported 'popa' instruction. + Reverse operands order in store co-processor instructions. + +2004-10-15 Alan Modra + + * Makefile.am: Run "make dep-am" + * Makefile.in: Regenerate. + +2004-10-12 Bob Wilson + + * xtensa-dis.c: Use ISO C90 formatting. + +2004-10-09 Alan Modra + + * ppc-opc.c: Revert 2004-09-09 change. + +2004-10-07 Bob Wilson + + * xtensa-dis.c (state_names): Delete. + (fetch_data): Use xtensa_isa_maxlength. + (print_xtensa_operand): Replace operand parameter with opcode/operand + pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions. + (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot + instruction bundles. Use xmalloc instead of malloc. + +2004-10-07 David Gibson + + * ppc-opc.c: Replace literal "0"s with NULLs in pointer + initializers. + +2004-10-07 Tomer Levi + + * crx-opc.c (crx_instruction): Support Co-processor insns. + * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments. + (getregliststring): Change function to use the above enum. + (print_arg): Handle CO-Processor insns. + (crx_cinvs): Add 'b' option to invalidate the branch-target + cache. + +2004-10-06 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs, + efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt, + efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid, + efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz, + efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs. + +2004-10-01 Bill Farmer + + * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement + rather than add it. + +2004-09-30 Paul Brook + + * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction. + * arm-opc.h: Document %e. Add ARMv6ZK instructions. + +2004-09-17 H.J. Lu + + * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9. + (CONFIG_STATUS_DEPENDENCIES): New. + (Makefile): Removed. + (config.status): Likewise. + * Makefile.in: Regenerated. + +2004-09-17 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2004-09-11 Andreas Schwab + + * configure: Rebuild. + +2004-09-09 Segher Boessenkool + + * ppc-opc.c (L): Make this field not optional. + +2004-09-03 Tomer Levi + + * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'. + Fix parameter to 'm[t|f]csr' insns. + +2004-08-30 Nathanael Nerode + + * configure.in: Autoupdate to autoconf 2.59. + * aclocal.m4: Rebuild with aclocal 1.4p6. + * configure: Rebuild with autoconf 2.59. + * Makefile.in: Rebuild with automake 1.4p6 (picking up + bfd changes for autoconf 2.59 on the way). + * config.in: Rebuild with autoheader 2.59. + +2004-08-27 Richard Sandiford + + * frv-desc.[ch], frv-opc.[ch]: Regenerated. + +2004-07-30 Michal Ludvig + + * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1 + (GRPPADLCK2): New define. + (twobyte_has_modrm): True for 0xA6. + (grps): GRPPADLCK2 for opcode 0xA6. + +2004-07-29 Alexandre Oliva + + Introduce SH2a support. + * sh-opc.h (arch_sh2a_base): Renumber. + (arch_sh2a_nofpu_base): Remove. + (arch_sh_base_mask): Adjust. + (arch_opann_mask): New. + (arch_sh2a, arch_sh2a_nofpu): Adjust. + (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise. + (sh_table): Adjust whitespace. + 2004-02-24 Corinna Vinschen + * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in + instruction list throughout. + (arch_sh2a_up): Redefine to include fpu instruction set. Use instead + of arch_sh2a in instruction list throughout. + (arch_sh2e_up): Accomodate above changes. + (arch_sh2_up): Ditto. + 2004-02-20 Corinna Vinschen + * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up. + 2004-02-18 Corinna Vinschen + * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling. + * sh-opc.h (arch_sh2a_nofpu): New. + (arch_sh2a_up): New, defines sh2a and sh2a_nofpu. + (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU + instruction. + 2004-01-20 DJ Delorie + * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs. + 2003-12-29 DJ Delorie + * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up, + sh_opcode_info, sh_table): Add sh2a support. + (arch_op32): New, to tag 32-bit opcodes. + * sh-dis.c (print_insn_sh): Support sh2a opcodes. + 2003-12-02 Michael Snyder + * sh-opc.h (arch_sh2a): Add. + * sh-dis.c (arch_sh2a): Handle. + * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a. + +2004-07-27 Tomer Levi + + * crx-opc.c: Add popx,pushx insns. Indent code, fix comments. + +2004-07-22 Nick Clifton + + PR/280 + * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the + insns - this is done by objdump itself. + * h8500-dis.c (print_insn_h8500): Likewise. + +2004-07-21 Jan Beulich + + * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode + regardless of address size prefix in effect. + (ptr_reg): Size or address registers does not depend on rex64, but + on the presence of an address size override. + (OP_MMX): Use rex.x only for xmm registers. + (OP_EM): Use rex.z only for xmm registers. + +2004-07-20 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2 + move/branch operations to the bottom so that VR5400 multimedia + instructions take precedence in disassembly. + +2004-07-20 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32 + ISA-specific "break" encoding. + +2004-07-13 Elvis Chiang + + * arm-opc.h: Fix typo in comment. + +2004-07-11 Andreas Schwab + + * m68k-dis.c (m68k_valid_ea): Fix typos in last change. + +2004-07-09 Andreas Schwab + + * m68k-dis.c (m68k_valid_ea): Check validity of all codes. + +2004-07-07 Tomer Levi + + * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c. + (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo. + (crx-dis.lo): New target. + (crx-opc.lo): Likewise. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_crx_arch. + * configure: Regenerate. + * crx-dis.c: New file. + * crx-opc.c: New file. + * disassemble.c (ARCH_crx): Define. + (disassembler): Handle ARCH_crx. + +2004-06-29 James E Wilson + + * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds. + * ia64-asmtab.c: Regnerate. + +2004-06-28 Alan Modra + + * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf. + (extract_fxm): Don't test dialect. + (XFXFXM_MASK): Include the power4 bit. + (XFXM): Add p4 param. + (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr. + +2004-06-27 Alexandre Oliva + + 2003-07-21 Richard Sandiford + * disassemble.c (disassembler): Handle bfd_mach_h8300sxn. + +2004-06-26 Alan Modra + + * ppc-opc.c (BH, XLBH_MASK): Define. + (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl. + +2004-06-24 Alan Modra + + * i386-dis.c (x_mode): Comment. + (two_source_ops): File scope. + (float_mem): Correct fisttpll and fistpll. + (float_mem_mode): New table. + (dofloat): Use it. + (OP_E): Correct intel mode PTR output. + (ptr_reg): Use open_char and close_char. + (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for + operands. Set two_source_ops. + +2004-06-15 Alan Modra + + * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size + instead of _raw_size. + +2004-06-08 Jakub Jelinek + + * ia64-gen.c (in_iclass): Handle more postinc st + and ld variants. + * ia64-asmtab.c: Rebuilt. + +2004-06-01 Martin Schwidefsky + + * s390-opc.txt: Correct architecture mask for some opcodes. + lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available + in the esa mode as well. + +2004-05-28 Andrew Stubbs + + * sh-dis.c (target_arch): Make unsigned. + (print_insn_sh): Replace (most of) switch with a call to + sh_get_arch_from_bfd_mach(). Also use new architecture flags system. + * sh-opc.h: Redefine architecture flags values. + Add sh3-nommu architecture. + Reorganise _up macros so they make more visual sense. + (SH_MERGE_ARCH_SET): Define new macro. + (SH_VALID_BASE_ARCH_SET): Likewise. + (SH_VALID_MMU_ARCH_SET): Likewise. + (SH_VALID_CO_ARCH_SET): Likewise. + (SH_VALID_ARCH_SET): Likewise. + (SH_MERGE_ARCH_SET_VALID): Likewise. + (SH_ARCH_SET_HAS_FPU): Likewise. + (SH_ARCH_SET_HAS_DSP): Likewise. + (SH_ARCH_UNKNOWN_ARCH): Likewise. + (sh_get_arch_from_bfd_mach): Add prototype. + (sh_get_arch_up_from_bfd_mach): Likewise. + (sh_get_bfd_mach_from_arch_set): Likewise. + (sh_merge_bfd_arc): Likewise. + +2004-05-24 Peter Barada + + * m68k-dis.c(print_insn_m68k): Strip body of diassembly out + into new match_insn_m68k function. Loop over canidate + matches and select first that completely matches. + * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit. + * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea + to verify addressing for MAC/EMAC. + * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC + reigster halves since 'fpu' and 'spl' look misleading. + * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases. + * m68k-opc.c: Rearragne mac/emac cases to use longest for + first, tighten up match masks. + * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce + 'size' from special case code in print_insn_m68k to + determine decode size of insns. + +2004-05-19 Alan Modra + + * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as + well as when -mpower4. + +2004-05-13 Nick Clifton + + * po/fr.po: Updated French translation. + +2004-05-05 Peter Barada + + * m68k-dis.c(print_insn_m68k): Add new chips, use core + variants in arch_mask. Only set m68881/68851 for 68k chips. + * m68k-op.c: Switch from ColdFire chips to core variants. + +2004-05-05 Alan Modra + + PR 147. + * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC. + +2004-04-29 Ben Elliston + + * ppc-opc.c (XCMPL): Renmame to XOPL. Update users. + (powerpc_opcodes): Add "dbczl" instruction for PPC970. + +2004-04-22 Kaz Kojima + + * sh-dis.c (print_insn_sh): Print the value in constant pool + as a symbol if it looks like a symbol. + +2004-04-22 Peter Barada + + * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on + appropriate ColdFire architectures. + (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC + mask addressing. + Add EMAC instructions, fix MAC instructions. Remove + macmw/macml/msacmw/msacml instructions since mask addressing now + supported. + +2004-04-20 Jakub Jelinek + + * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define. + (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to + suffix. Use fmov*x macros, create all 3 fpsize variants in one + macro. Adjust all users. + +2004-04-15 Anil Paranjpe + + * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs" + separately. + +2004-03-30 Kazuhiro Inaoka + + * m32r-asm.c: Regenerate. + +2004-03-29 Stan Shebs + + * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer + used. + +2004-03-19 Alan Modra + + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2004-03-16 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle + PPC_OPERANDS_GPR_0. + * ppc-opc.c (RA0): Define. + (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0. + (RAOPT): Rename from RAO. Update all uses. + (powerpc_opcodes): Use RA0 as appropriate. + +2004-03-15 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg. + +2004-03-15 Alan Modra + + * sparc-dis.c (print_insn_sparc): Update getword prototype. + 2004-03-12 Michal Ludvig * i386-dis.c (GRPPLOCK): Delete. - (grps): Detele GRPPLOCK entry. + (grps): Delete GRPPLOCK entry. 2004-03-12 Alan Modra @@ -84,8 +740,8 @@ Adjust the bit patterns in a few comments. 2004-02-25 Aldy Hernandez - - * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst. + + * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst. 2004-02-20 Aldy Hernandez @@ -96,13 +752,13 @@ * ppc-opc.c (powerpc_opcodes): Add m*ivor35. 2004-02-20 Aldy Hernandez - - * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34, - mtivor32, mtivor33, mtivor34. + + * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34, + mtivor32, mtivor33, mtivor34. 2004-02-19 Aldy Hernandez - - * ppc-opc.c (powerpc_opcodes): Add mfmcar. + + * ppc-opc.c (powerpc_opcodes): Add mfmcar. 2004-02-10 Petko Manolov