X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=7c603f16238e392938cfd7ff693694087963d2fd;hb=dec0624dcd4590d55fad203497fcdcef4ce292e3;hp=844d80a5a8424bc7472f35ed6d35894ea746d71e;hpb=8b9a522f5779a9e8640df98c7010f763b008f625;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 844d80a5a8..7c603f1623 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,984 +1,611 @@ -2010-12-09 Mike Frysinger - - * .gitignore: New file. - -2010-11-25 Alan Modra - - * po/es.po: Update. - * po/fr.po: Update. - * po/nl.po: Update. - * po/zh_CN.po: Update. - -2010-11-11 Mingming Sun - - * mips-dis.c (mips_arch_choices): Add loongson3a. - * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A. - (mips_builtin_opcodes): Modify some instructions' membership from - IL2F to IL2F|IL3A. - -2010-11-10 Nick Clifton - - * po/fi.po: Updated Finnish translation. +2011-08-09 Chao-ying Fu + Maciej W. Rozycki + + * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" + and "mips64r2". + (print_insn_args, print_insn_micromips): Handle MCU. + * micromips-opc.c (MC): New macro. + (micromips_opcodes): Add "aclr", "aset" and "iret". + * mips-opc.c (MC): New macro. + (mips_builtin_opcodes): Add "aclr", "aset" and "iret". + +2011-08-09 Maciej W. Rozycki + + * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros. + (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise. + (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise. + (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros. + (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise. + (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise. + (WR_s): Update macro. + (micromips_opcodes): Update register use flags of: "addiu", + "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu", + "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j", + "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li", + "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not", + "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw", + "swm" and "xor" instructions. + +2011-08-05 David S. Miller + + * sparc-dis.c (v9a_ast_reg_names): Add "cps". + (X_RS3): New macro. + (print_insn_sparc): Handle '4', '5', and '(' format codes. + Accept %asr numbers below 28. + * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3 + instructions. -2010-11-05 Tristan Gingold +2011-08-02 Quentin Neill - * po/opcodes.pot: Regenerate + * i386-dis.c (xop_table): Remove spurious bextr insn. -2010-10-28 Maciej W. Rozycki +2011-08-01 H.J. Lu - * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld". + PR ld/13048 + * i386-dis.c (print_insn): Optimize info->mach check. -2010-10-28 Andreas Krebbel +2011-08-01 H.J. Lu - * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5. + PR gas/13046 + * i386-opc.tbl: Add Disp32S to 64bit call. + * i386-tbl.h: Regenerated. -2010-10-25 Chao-ying Fu +2011-07-24 Chao-ying Fu + Maciej W. Rozycki + + * micromips-opc.c: New file. + * mips-dis.c (micromips_to_32_reg_b_map): New array. + (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise. + (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise. + (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise. + (micromips_to_32_reg_q_map): Likewise. + (micromips_imm_b_map, micromips_imm_c_map): Likewise. + (micromips_ase): New variable. + (is_micromips): New function. + (set_default_mips_dis_options): Handle microMIPS ASE. + (print_insn_micromips): New function. + (is_compressed_mode_p): Likewise. + (_print_insn_mips): Handle microMIPS instructions. + * Makefile.am (CFILES): Add micromips-opc.c. + * configure.in (bfd_mips_arch): Add micromips-opc.lo. + * Makefile.in: Regenerate. + * configure: Regenerate. - * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32. + * mips-dis.c (micromips_to_32_reg_h_map): New variable. + (micromips_to_32_reg_i_map): Likewise. + (micromips_to_32_reg_m_map): Likewise. + (micromips_to_32_reg_n_map): New macro. -2010-10-25 Nathan Sidwell +2011-07-24 Maciej W. Rozycki - * tic6x-dis.c: Add attribution. + * mips-opc.c (NODS): New macro. + (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT. + (DSP_VOLA): Likewise. + (mips_builtin_opcodes): Add NODS annotation to "deret" and + "eret". Replace INSN_SYNC with NODS throughout. Use NODS in + place of TRAP for "wait", "waiti" and "yield". + * mips16-opc.c (NODS): New macro. + (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT. + (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc", + "restore" and "save". -2010-10-22 Alan Modra +2011-07-22 H.J. Lu - * Makefile.am (CLEANFILES): Add stamp-lm32. Sort. - * Makefile.in: Regenerate. + * configure.in: Handle bfd_k1om_arch. + * configure: Regenerated. -2010-10-18 Maciej W. Rozycki + * disassemble.c (disassembler): Handle bfd_k1om_arch. - * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB - macros before their corresponding MIPS III hardware instructions. + * i386-dis.c (print_insn): Handle bfd_mach_k1om and + bfd_mach_k1om_intel_syntax. -2010-10-16 H.J. Lu + * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to + ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS. + (cpu_flags): Add CpuK1OM. - * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS. + * i386-opc.h (CpuK1OM): New. + (i386_cpu_flags): Add cpuk1om. * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. -2010-10-15 Mike Frysinger +2011-07-12 Nick Clifton - * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M. + * arm-dis.c (print_insn_arm): Revert previous, undocumented, + accidental change. -2010-10-14 H.J. Lu +2011-07-01 Nick Clifton - * i386-opc.tbl: Remove CheckRegSize from movq. - * i386-tbl.h: Regenerated. + PR binutils/12329 + * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM + insns using post-increment addressing. -2010-10-14 H.J. Lu +2011-06-30 H.J. Lu - * i386-opc.tbl: Remove CheckRegSize from instructions with - 0, 1 or fixed operands. - * i386-tbl.h: Regenerated. - -2010-10-14 H.J. Lu + * i386-dis.c (vex_len_table): Update rorxS. - * i386-gen.c (opcode_modifiers): Add CheckRegSize. +2011-06-30 H.J. Lu - * i386-opc.h (CheckRegSize): New. - (i386_opcode_modifier): Add checkregsize. + AVX Programming Reference (June, 2011) + * i386-dis.c (vex_len_table): Correct rorxS. - * i386-opc.tbl: Add CheckRegSize to instructions which - require register size check. + * i386-opc.tbl: Correct rorx. * i386-tbl.h: Regenerated. -2010-10-12 Andreas Schwab - - * m68k-opc.c (m68k_opcodes): Move fnop before fbf. - -2010-10-11 Andreas Krebbel +2011-06-29 H.J. Lu - * s390-opc.c: Make the instruction masks for the load/store on - condition instructions to cover the condition code mask as well. - * s390-opc.txt: lgoc -> locg and stgoc -> stocg. + * tilegx-opc.c (find_opcode): Replace "index" with "i". + * tilepro-opc.c (find_opcode): Likewise. -2010-10-11 Jan Kratochvil - Jiang Jilin +2011-06-29 Richard Sandiford - * Makefile.am (libopcodes_a_SOURCES): New as empty. - * Makefile.in: Regenerate. - -2010-10-09 Matt Rice - - * fr30-desc.h: Regenerate. - * frv-desc.h: Regenerate. - * ip2k-desc.h: Regenerate. - * iq2000-desc.h: Regenerate. - * lm32-desc.h: Regenerate. - * m32c-desc.h: Regenerate. - * m32r-desc.h: Regenerate. - * mep-desc.h: Regenerate. - * mep-opc.c: Regenerate. - * mt-desc.h: Regenerate. - * openrisc-desc.h: Regenerate. - * xc16x-desc.h: Regenerate. - * xstormy16-desc.h: Regenerate. - -2010-10-08 Pierre Muller - - Fix build with -DDEBUG=7 - * frv-opc.c: Regenerate. - * or32-dis.c (DEBUG): Don't redefine. - (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register): - Adapt DEBUG code to some type changes throughout. - * or32-opc.c (or32_extract): Likewise. + * mips16-opc.c (jalrc, jrc): Move earlier in file. -2010-10-07 Bernd Schmidt +2011-06-21 H.J. Lu - * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field - in SPKERNEL instructions. + * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and + PREFIX_VEX_0F388E. -2010-10-02 H.J. Lu +2011-06-17 Andreas Schwab - PR binutils/12076 - * i386-dis.c (RMAL): Remove duplicate. - -2010-09-30 Pierre Muller - - * s390-mkopc.c (main): Exit with error 1 if sscanf fails - to parse all 6 parameters. + * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ... + (MOSTLYCLEANFILES): ... here. + * Makefile.in: Regenerate. -2010-09-28 Pierre Muller +2011-06-14 Alan Modra - * s390-mkopc.c (main): Change description array size to 80. - Add maximum length of 79 to description parsing. + * Makefile.in: Regenerate. -2010-09-27 Ralf Wildenhues +2011-06-13 Walter Lee + * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c, + tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch. * configure: Regenerate. + * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro. + * po/POTFILES.in: Regenerate. + * tilegx-dis.c: New file. + * tilegx-opc.c: New file. + * tilepro-dis.c: New file. + * tilepro-opc.c: New file. + +2011-06-10 H.J. Lu + + AVX Programming Reference (June, 2011) + * i386-dis.c (XMGatherQ): New. + * i386-dis.c (EXxmm_mb): New. + (EXxmm_mb): Likewise. + (EXxmm_mw): Likewise. + (EXxmm_md): Likewise. + (EXxmm_mq): Likewise. + (EXxmmdw): Likewise. + (EXxmmqd): Likewise. + (VexGatherQ): Likewise. + (MVexVSIBDWpX): Likewise. + (MVexVSIBQWpX): Likewise. + (xmm_mb_mode): Likewise. + (xmm_mw_mode): Likewise. + (xmm_md_mode): Likewise. + (xmm_mq_mode): Likewise. + (xmmdw_mode): Likewise. + (xmmqd_mode): Likewise. + (ymmxmm_mode): Likewise. + (vex_vsib_d_w_dq_mode): Likewise. + (vex_vsib_q_w_dq_mode): Likewise. + (MOD_VEX_0F385A_PREFIX_2): Likewise. + (MOD_VEX_0F388C_PREFIX_2): Likewise. + (MOD_VEX_0F388E_PREFIX_2): Likewise. + (PREFIX_0F3882): Likewise. + (PREFIX_VEX_0F3816): Likewise. + (PREFIX_VEX_0F3836): Likewise. + (PREFIX_VEX_0F3845): Likewise. + (PREFIX_VEX_0F3846): Likewise. + (PREFIX_VEX_0F3847): Likewise. + (PREFIX_VEX_0F3858): Likewise. + (PREFIX_VEX_0F3859): Likewise. + (PREFIX_VEX_0F385A): Likewise. + (PREFIX_VEX_0F3878): Likewise. + (PREFIX_VEX_0F3879): Likewise. + (PREFIX_VEX_0F388C): Likewise. + (PREFIX_VEX_0F388E): Likewise. + (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. + (PREFIX_VEX_0F38F5): Likewise. + (PREFIX_VEX_0F38F6): Likewise. + (PREFIX_VEX_0F3A00): Likewise. + (PREFIX_VEX_0F3A01): Likewise. + (PREFIX_VEX_0F3A02): Likewise. + (PREFIX_VEX_0F3A38): Likewise. + (PREFIX_VEX_0F3A39): Likewise. + (PREFIX_VEX_0F3A46): Likewise. + (PREFIX_VEX_0F3AF0): Likewise. + (VEX_LEN_0F3816_P_2): Likewise. + (VEX_LEN_0F3819_P_2): Likewise. + (VEX_LEN_0F3836_P_2): Likewise. + (VEX_LEN_0F385A_P_2_M_0): Likewise. + (VEX_LEN_0F38F5_P_0): Likewise. + (VEX_LEN_0F38F5_P_1): Likewise. + (VEX_LEN_0F38F5_P_3): Likewise. + (VEX_LEN_0F38F6_P_3): Likewise. + (VEX_LEN_0F38F7_P_1): Likewise. + (VEX_LEN_0F38F7_P_2): Likewise. + (VEX_LEN_0F38F7_P_3): Likewise. + (VEX_LEN_0F3A00_P_2): Likewise. + (VEX_LEN_0F3A01_P_2): Likewise. + (VEX_LEN_0F3A38_P_2): Likewise. + (VEX_LEN_0F3A39_P_2): Likewise. + (VEX_LEN_0F3A46_P_2): Likewise. + (VEX_LEN_0F3AF0_P_3): Likewise. + (VEX_W_0F3816_P_2): Likewise. + (VEX_W_0F3818_P_2): Likewise. + (VEX_W_0F3819_P_2): Likewise. + (VEX_W_0F3836_P_2): Likewise. + (VEX_W_0F3846_P_2): Likewise. + (VEX_W_0F3858_P_2): Likewise. + (VEX_W_0F3859_P_2): Likewise. + (VEX_W_0F385A_P_2_M_0): Likewise. + (VEX_W_0F3878_P_2): Likewise. + (VEX_W_0F3879_P_2): Likewise. + (VEX_W_0F3A00_P_2): Likewise. + (VEX_W_0F3A01_P_2): Likewise. + (VEX_W_0F3A02_P_2): Likewise. + (VEX_W_0F3A38_P_2): Likewise. + (VEX_W_0F3A39_P_2): Likewise. + (VEX_W_0F3A46_P_2): Likewise. + (MOD_VEX_0F3818_PREFIX_2): Removed. + (MOD_VEX_0F3819_PREFIX_2): Likewise. + (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. + (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. + (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. + (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. + (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. + (VEX_LEN_0F3A0E_P_2): Likewise. + (VEX_LEN_0F3A0F_P_2): Likewise. + (VEX_LEN_0F3A42_P_2): Likewise. + (VEX_LEN_0F3A4C_P_2): Likewise. + (VEX_W_0F3818_P_2_M_0): Likewise. + (VEX_W_0F3819_P_2_M_0): Likewise. + (prefix_table): Updated. + (three_byte_table): Likewise. + (vex_table): Likewise. + (vex_len_table): Likewise. + (vex_w_table): Likewise. + (mod_table): Likewise. + (putop): Handle "LW". + (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, + xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, + vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. + (OP_EX): Likewise. + (OP_E_memory): Handle vex_vsib_d_w_dq_mode and + vex_vsib_q_w_dq_mode. + (OP_XMM): Handle vex_vsib_q_w_dq_mode. + (OP_VEX): Likewise. -2010-09-27 Andreas Krebbel - - * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196. - (main): Recognize the new CPU string. - * s390-opc.c: Add new instruction formats and masks. - * s390-opc.txt: Add new z196 instructions. - -2010-09-27 Andreas Krebbel - - * s390-dis.c (print_insn_s390): Pick instruction with most - specific mask. - * s390-opc.c: Add unused bits to the insn mask. - * s390-opc.txt: Reorder some instructions to prefer more recent - versions. + * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS + and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, + CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. + (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. + (opcode_modifiers): Add VecSIB. + + * i386-opc.h (CpuAVX2): New. + (CpuBMI2): Likewise. + (CpuLZCNT): Likewise. + (CpuINVPCID): Likewise. + (VecSIB128): Likewise. + (VecSIB256): Likewise. + (VecSIB): Likewise. + (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. + (i386_opcode_modifier): Add vecsib. + + * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. -2010-09-27 Tejas Belagod +2011-06-03 Quentin Neill - * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment - correction to unaligned PCs while printing comment. + * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS. + * i386-init.h: Regenerated. -2010-09-23 Matthew Gretton-Dann +2011-06-03 Nick Clifton - * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. - (thumb32_opcodes): Likewise. - (banked_regname): New function. - (print_insn_arm): Add Virtualization Extensions support. + PR binutils/12752 + * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for + computing address offsets. + (print_arm_address): Likewise. + (print_insn_arm): Likewise. + (print_insn_thumb16): Likewise. (print_insn_thumb32): Likewise. -2010-09-23 Matthew Gretton-Dann - - * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in - ARM state. - -2010-09-23 Matthew Gretton-Dann - - * arm-dis.c (arm_opcodes): SMC implies Security Extensions. - (thumb32_opcodes): Likewise. - -2010-09-23 Matthew Gretton-Dann - - * arm-dis.c (arm_opcodes): Add support for pldw. - (thumb32_opcodes): Likewise. - -2010-09-22 Robin Getz - - * bfin-dis.c (fmtconst): Cast address to 32bits. - -2010-09-22 Mike Frysinger - - * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks. - -2010-09-22 Robin Getz - - * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns. - Reject P6/P7 to TESTSET. - (decode_PushPopReg_0): Check for parallel insns. Reject pushing - SP onto the stack. - (decode_PushPopMultiple_0): Check for parallel insns. Make sure - P/D fields match all the time. - (decode_CCflag_0): Check for parallel insns. Verify x/y fields - are 0 for accumulator compares. - (decode_CC2stat_0): Check for parallel insns. Reject CCCC. - (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0, - decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0, - decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0, - decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0, - decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel - insns. - (decode_dagMODim_0): Verify br field for IREG ops. - (decode_LDST_0): Reject preg load into same preg. - (_print_insn_bfin): Handle returns for ILLEGAL decodes. - (print_insn_bfin): Likewise. - -2010-09-22 Mike Frysinger - - * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5. - -2010-09-22 Robin Getz +2011-06-02 Jie Zhang + Nathan Sidwell + Maciej Rozycki - * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag. + * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 + as address offset. + (print_arm_address): Likewise. Elide positive #0 appropriately. + (print_insn_arm): Likewise. -2010-09-22 Mike Frysinger +2011-06-02 Nick Clifton - * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits. + PR gas/12752 + * arm-dis.c (print_insn_thumb32): Do not sign extend addresses + passed to print_address_func. -2010-09-22 Robin Getz +2011-06-02 Nick Clifton - * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject - register values greater than 8. - (IS_RESERVEDREG, allreg, mostreg): New helpers. - (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate. - (decode_PushPopReg_0): Call mostreg/allreg as appropriate. - (decode_CC2dreg_0): Check valid CC register number. + * arm-dis.c: Fix spelling mistakes. + * op/opcodes.pot: Regenerate. -2010-09-22 Robin Getz +2011-05-24 Andreas Krebbel - * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG. + * s390-opc.c: Replace S390_OPERAND_REG_EVEN with + S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type. + * s390-opc.txt: Fix cxr instruction type. -2010-09-22 Robin Getz +2011-05-24 Andreas Krebbel - * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD. - (reg_names): Likewise. - (decode_statbits): Likewise; while reformatting to make manageable. + * s390-opc.c: Add new instruction types marking register pair + operands. + * s390-opc.txt: Match instructions having register pair operands + to the new instruction types. -2010-09-22 Mike Frysinger +2011-05-19 Nick Clifton - * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC. - (decode_pseudoOChar_0): New function. - (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0. + * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2 + operands. -2010-09-22 Robin Getz +2011-05-10 Quentin Neill - * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as - LSHIFT instead of SHIFT. - -2010-09-22 Mike Frysinger - - * bfin-dis.c (constant_formats): Constify the whole structure. - (fmtconst): Add const to return value. - (reg_names): Mark const. - (decode_multfunc): Mark s0/s1 as const. - (decode_macfunc): Mark a/sop as const. - -2010-09-17 Tejas Belagod - - * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv. - -2010-09-14 Maciej W. Rozycki - - * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", - "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". - -2010-09-10 Pierre Muller - - * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for - dlx_insn_type array. - -2010-08-31 H.J. Lu - - PR binutils/11960 - * i386-dis.c (sIv): New. - (dis386): Replace Iq with sIv on "pushT". - (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT. - (x86_64_table): Replace {T|}/{P|} with P. - (putop): Add 'w' to 'T'/'P' if needed for Intel syntax. - (OP_sI): Update v_mode. Remove w_mode. - -2010-08-27 Nathan Froyd - - * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate - on E500 and E500MC. - -2010-08-17 H.J. Lu - - * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and - prefetchw. - -2010-08-06 Quentin Neill - - * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add - to processor flags for PENTIUMPRO processors and later. - * i386-opc.h (enum): Add CpuNop. - (i386_cpu_flags): Add cpunop bit. - * i386-opc.tbl: Change nop cpu_flags. + * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. -2010-08-06 Quentin Neill +2011-04-27 Nick Clifton - * i386-opc.h (enum): Fix typos in comments. + * po/da.po: Updated Danish translation. -2010-08-06 Alan Modra +2011-04-26 Anton Blanchard - * disassemble.c: Formatting. - (disassemble_init_for_target ): Comment on endian. + * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7. -2010-08-05 H.J. Lu +2011-04-21 DJ Delorie - * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. - * i386-tbl.h: Regenerated. - -2010-08-05 H.J. Lu - - * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1. - - * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b. - * i386-tbl.h: Regenerated. - -2010-07-29 DJ Delorie - - * rx-decode.opc (SRR): New. - (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov - r0,r0) and NOP3 (max r0,r0) special cases. - * rx-decode.c: Regenerate. - -2010-07-28 H.J. Lu - - * i386-dis.c: Add 0F to VEX opcode enums. - -2010-07-27 DJ Delorie - - * rx-decode.opc (store_flags): Remove, replace with F_* macros. - (rx_decode_opcode): Likewise. + * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs. * rx-decode.c: Regenerate. -2010-07-23 Naveen.H.S - Ina Pandit - - * v850-dis.c (v850_sreg_names): Updated structure for system - registers. - (float_cc_names): new structure for condition codes. - (print_value): Update the function that prints value. - (get_operand_value): New function to get the operand value. - (disassemble): Updated to handle the disassembly of instructions. - (print_insn_v850): Updated function to print instruction for different - families. - * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1, - extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3, - extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6, - insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop, - extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16, - extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22, - extract_d22, insert_d23, extract_d23, insert_i9, extract_i9, - insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New. - (insert_d8_7, insert_d5_4, insert_i5div): Remove. - (v850_operands): Update with the relocation name. Also update - the instructions with specific set of processors. - -2010-07-08 Tejas Belagod - - * arm-dis.c (print_insn_arm): Add cases for printing more - symbolic operands. - (print_insn_thumb32): Likewise. - -2010-07-06 Maciej W. Rozycki - - * mips-dis.c (print_insn_mips): Correct branch instruction type - determination. - -2010-07-06 Maciej W. Rozycki - - * mips-dis.c (print_mips16_insn_arg): Remove branch instruction - type and delay slot determination. - (print_insn_mips16): Extend branch instruction type and delay - slot determination to cover all instructions. - * mips16-opc.c (BR): Remove macro. - (UBR, CBR): New macros. - (mips16_opcodes): Update branch annotation for "b", "beqz", - "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" - and "jrc". - -2010-07-05 H.J. Lu +2011-04-20 H.J. Lu - AVX Programming Reference (June, 2010) - * i386-dis.c (mod_table): Replace rdrnd with rdrand. - * i386-opc.tbl: Likewise. - * i386-tbl.h: Regenerated. - -2010-07-05 H.J. Lu - - * i386-opc.h (CpuFSGSBase): Fix a typo in comments. - -2010-07-03 Andreas Schwab - - * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to - ppc_cpu_t before inverting. - (ppc_parse_cpu): Likewise. - (print_insn_powerpc): Likewise. - -2010-07-03 Alan Modra - - * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags. - * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete. - (PPC64, MFDEC2): Update. - (NON32, NO371): Define. - (powerpc_opcode): Update to not use old opcode flags, and avoid - -m601 duplicates. - -2010-07-03 DJ Delorie - - * m32c-ibld.c: Regenerate. - -2010-07-03 Alan Modra - - * ppc-opc.c (PWR2COM): Define. - (PPCPWR2): Add PPC_OPCODE_COMMON. - (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.", - "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst", - "rac" from -mcom. - -2010-07-01 H.J. Lu - - AVX Programming Reference (June, 2010) - * i386-dis.c (PREFIX_0FAE_REG_0): New. - (PREFIX_0FAE_REG_1): Likewise. - (PREFIX_0FAE_REG_2): Likewise. - (PREFIX_0FAE_REG_3): Likewise. - (PREFIX_VEX_3813): Likewise. - (PREFIX_VEX_3A1D): Likewise. - (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, - PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and - PREFIX_VEX_3A1D. - (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. - (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, - PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. - - * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, - CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. - (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. - - * i386-opc.h (CpuXsaveopt): New. - (CpuFSGSBase): Likewise. - (CpuRdRnd): Likewise. - (CpuF16C): Likewise. - (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and - cpuf16c. - - * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, - wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph. * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. -2010-07-01 Sebastian Andrzej Siewior +2011-04-19 Quentin Neill - * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf - and mtocrf on EFS. + * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits + from bdver1 flags. -2010-06-29 Alan Modra +2011-04-13 Nick Clifton - * maxq-dis.c: Delete file. - * Makefile.am: Remove references to maxq. - * configure.in: Likewise. - * disassemble.c: Likewise. - * Makefile.in: Regenerate. - * configure: Regenerate. - * po/POTFILES.in: Regenerate. + * v850-dis.c (disassemble): Always print a closing square brace if + an opening square brace was printed. -2010-06-29 Alan Modra +2011-04-12 Nick Clifton - * mep-dis.c: Regenerate. + PR binutils/12534 + * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn + patterns. + (print_insn_thumb32): Handle %L. -2010-06-28 Matthew Gretton-Dann +2011-04-11 Julian Brown - * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax. + * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX. + (print_insn_thumb32): Add APSR bitmask support. -2010-06-27 Alan Modra +2011-04-07 Paul Carroll - * arc-dis.c (arc_sprintf): Delete set but unused variables. - (decodeInstr): Likewise. - * dlx-dis.c (print_insn_dlx): Likewise. - * h8300-dis.c (bfd_h8_disassemble_init): Likewise. - * maxq-dis.c (check_move, print_insn): Likewise. - * mep-dis.c (mep_examine_ivc2_insns): Likewise. - * msp430-dis.c (msp430_branchinstr): Likewise. - * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning. - * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise. - * sparc-dis.c (print_insn_sparc): Likewise. - * fr30-asm.c: Regenerate. - * frv-asm.c: Regenerate. - * ip2k-asm.c: Regenerate. - * iq2000-asm.c: Regenerate. - * lm32-asm.c: Regenerate. - * m32c-asm.c: Regenerate. - * m32r-asm.c: Regenerate. - * mep-asm.c: Regenerate. - * mt-asm.c: Regenerate. - * openrisc-asm.c: Regenerate. - * xc16x-asm.c: Regenerate. - * xstormy16-asm.c: Regenerate. + * arm-dis.c (print_insn): init vars moved into private_data structure. -2010-06-16 Vincent Rivière +2011-03-24 Mike Frysinger - PR gas/11673 - * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later. + * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic. -2010-06-16 Vincent Rivière +2011-03-22 Eric B. Weddington - PR binutils/11676 - * m68k-dis.c (print_insn_arg): Prefix float constants with #0e. + * avr-dis.c (avr_operand): Add opcode_str parameter. Check for + post-increment to support LPM Z+ instruction. Add support for 'E' + constraint for DES instruction. + (print_insn_avr): Adjust calls to avr_operand. Rename variable. -2010-06-14 Sebastian Andrzej Siewior +2011-03-14 Richard Sandiford - * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and - e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 - * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which - touch floating point regs and are enabled by COM, PPC or PPCCOM. - Treat sync as msync on e500. Treat eieio as mbar 1 on e500. - Treat lwsync as msync on e500. + * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. -2010-06-07 Matthew Gretton-Dann +2011-03-14 Richard Sandiford - * arm-dis.c (thumb-opcodes): Add disassembly for movs. + * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. + Use branch types instead. + (print_insn): Likewise. -2010-05-28 Matthew Gretton-Dann +2011-02-28 Maciej W. Rozycki - * arm-dis.c (print_insn_neon): Ensure disassembly of Neon - constants is the same on 32-bit and 64-bit hosts. + * mips-opc.c (mips_builtin_opcodes): Correct register use + annotation of "alnv.ps". -2010-05-27 Jason Duerstock +2011-02-28 Maciej W. Rozycki - * m68k-dis.c (print_insn_m68k): Emit undefined instructions as - .short directives so that they can be reassembled. + * mips-opc.c (mips_builtin_opcodes): Add "pref" macro. -2010-05-26 Catherine Moore - David Ung +2011-02-22 Mike Frysinger - * mips-opc.c: Change membership to I1 for instructions ssnop and - ehb. + * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check. -2010-05-26 H.J. Lu +2011-02-22 Mike Frysinger - * i386-dis.c (sib): New. - (get_sib): Likewise. - (print_insn): Call get_sib. - OP_E_memory): Use sib. + * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS. -2010-05-26 Catherine Moore +2011-02-19 Mike Frysinger - * mips-dis.c (mips_arch): Remove INSN_MIPS16. - * mips-opc.c (I16): Remove. - (mips_builtin_op): Reclassify jalx. + * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and + a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1, + av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts, + exception, end_of_registers, msize, memory, bfd_mach. + (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG, + LB0REG, LC1REG, LT1REG, LB1REG): Delete + (AXREG, AWREG, LCREG, LTREG, LBREG): Define. + (get_allreg): Change to new defines. Fallback to abort(). -2010-05-19 Alan Modra +2011-02-14 Mike Frysinger - * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, - divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx. + * bfin-dis.c: Add whitespace/parenthesis where needed. -2010-05-13 Alan Modra +2011-02-14 Mike Frysinger - * ppc-opc.c (powerpc_opcodes): Correct wclr encoding. + * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater + than 7. -2010-05-11 Matthew Gretton-Dann +2011-02-13 Ralf Wildenhues - * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W - format. - (print_insn_thumb16): Add support for new %W format. + * configure: Regenerate. -2010-05-07 Tristan Gingold +2011-02-13 Mike Frysinger - * Makefile.in: Regenerate with automake 1.11.1. - * aclocal.m4: Ditto. + * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg. -2010-05-05 Nick Clifton +2011-02-13 Mike Frysinger - * po/es.po: Updated Spanish translation. + * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output + dregs only when P is set, and dregs_lo otherwise. -2010-04-22 Nick Clifton +2011-02-13 Mike Frysinger - * po/opcodes.pot: Updated by the Translation project. - * po/vi.po: Updated Vietnamese translation. + * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code. -2010-04-16 H.J. Lu +2011-02-12 Mike Frysinger - * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown - bits in opcode. + * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT. -2010-04-09 Nick Clifton +2011-02-12 Mike Frysinger - * i386-dis.c (print_insn): Remove unused variable op. - (OP_sI): Remove unused variable mask. + * bfin-dis.c (machine_registers): Delete REG_GP. + (reg_names): Delete "GP". + (decode_allregs): Change REG_GP to REG_LASTREG. -2010-04-07 Alan Modra +2011-02-12 Mike Frysinger - * configure: Regenerate. + * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, + M_IH, M_IU): Delete. -2010-04-06 Peter Bergner +2011-02-11 Mike Frysinger - * ppc-opc.c (RBOPT): New define. - ("dccci"): Enable for PPCA2. Make operands optional. - ("iccci"): Likewise. Do not deprecate for PPC476. + * bfin-dis.c (reg_names): Add const. + (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte, + decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs, + decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits, + decode_counters, decode_allregs): Likewise. -2010-04-02 Masaki Muranaka +2011-02-09 Michael Snyder - * cr16-opc.c (cr16_instruction): Fix typo in comment. + * i386-dis.c (OP_J): Parenthesize expression to prevent + truncated addresses. + (print_insn): Fix indentation off-by-one. -2010-03-25 Joseph Myers +2011-02-01 Nick Clifton - * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c. - * Makefile.in: Regenerate. - * configure.in (bfd_tic6x_arch): New. - * configure: Regenerate. - * disassemble.c (ARCH_tic6x): Define if ARCH_all. - (disassembler): Handle TI C6X. - * tic6x-dis.c: New. - -2010-03-24 Mike Frysinger + * po/da.po: Updated Danish translation. - * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2. +2011-01-21 Dave Murphy -2010-03-23 Joseph Myers + * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. - * dis-buf.c (buffer_read_memory): Give error for reading just - before the start of memory. +2011-01-18 H.J. Lu -2010-03-22 Sebastian Pop - Quentin Neill + * i386-dis.c (sIbT): New. + (b_T_mode): Likewise. + (dis386): Replace sIb with sIbT on "pushT". + (x86_64_table): Replace sIb with Ib on "aam" and "aad". + (OP_sI): Handle b_T_mode. Properly sign-extend byte. - * i386-dis.c (OP_LWP_I): Removed. - (reg_table): Do not use OP_LWP_I, use Iq. - (OP_LWPCB_E): Remove use of names16. - (OP_LWP_E): Same. - * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns - should not set the Vex.length bit. - * i386-tbl.h: Regenerated. +2011-01-18 Jan Kratochvil -2010-02-25 Edmar Wienskoski - - * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64". - -2010-02-24 Nick Clifton - - PR binutils/6773 - * arm-dis.c (arm_opcodes): Replace addsubx with - asx. Replace subaddx with sax. - (thumb32_opcodes): Likewise. - -2010-02-15 Nick Clifton - - * po/vi.po: Updated Vietnamese translation. - -2010-02-12 Doug Evans - - * lm32-opinst.c: Regenerate. - -2010-02-11 Doug Evans - - * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL. - (print_address): Delete CGEN_PRINT_ADDRESS. - * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c, - * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h, - * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c, - * xc16x-dis.c, * xstormy16-dis.c: Regenerate. - - * fr30-desc.c, * fr30-desc.h, * fr30-opc.c, - * frv-desc.c, * frv-desc.h, * frv-opc.c, - * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c, - * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c, - * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c, - * m32c-desc.c, * m32c-desc.h, * m32c-opc.c, - * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c, - * mep-desc.c, * mep-desc.h, * mep-opc.c, - * mt-desc.c, * mt-desc.h, * mt-opc.c, - * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c, - * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c, - * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate. - -2010-02-11 H.J. Lu - - * i386-dis.c: Update copyright. - * i386-gen.c: Likewise. - * i386-opc.h: Likewise. - * i386-opc.tbl: Likewise. - -2010-02-10 Quentin Neill - Sebastian Pop - - * i386-dis.c (OP_EX_VexImmW): Reintroduced - function to handle 5th imm8 operand. - (PREFIX_VEX_3A48): Added. - (PREFIX_VEX_3A49): Added. - (VEX_W_3A48_P_2): Added. - (VEX_W_3A49_P_2): Added. - (prefix table): Added entries for PREFIX_VEX_3A48 - and PREFIX_VEX_3A49. - (vex table): Added entries for VEX_W_3A48_P_2 and - and VEX_W_3A49_P_2. - * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4 - for Vec_Imm4 operands. - * i386-opc.h (enum): Added Vec_Imm4. - (i386_operand_type): Added vec_imm4. - * i386-opc.tbl: Add entries for vpermilp[ds]. * i386-init.h: Regenerated. - * i386-tbl.h: Regenerated. + * i386-tbl.h: Regenerated -2010-02-10 Richard Sandiford +2011-01-17 Quentin Neill - * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6" - and "pwr7". Move "a2" into alphabetical order. + * i386-dis.c (REG_XOP_TBM_01): New. + (REG_XOP_TBM_02): New. + (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. + (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 + entries, and add bextr instruction. -2010-02-08 Philipp Tomsich + * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. + (cpu_flags): Add CpuTBM. - * ppc-dis.c (ppc_opts): Add titan entry. - * ppc-opc.c (TITAN, MULHW): Define. - (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). + * i386-opc.h (CpuTBM) New. + (i386_cpu_flags): Add bit cputbm. -2010-02-03 Quentin Neill + * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, + blcs, blsfill, blsic, t1mskc, and tzmsk. - * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS - to CPU_BDVER1_FLAGS - * i386-init.h: Regenerated. +2011-01-12 DJ Delorie -2010-02-03 Anthony Green - - * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to - 0x0f, and make 0x00 an illegal instruction. - -2010-01-29 Daniel Jacobowitz - - * opcodes/arm-dis.c (struct arm_private_data): New. - (print_insn_coprocessor, print_insn_arm): Update to use struct - arm_private_data. - (is_mapping_symbol, get_map_sym_type): New functions. - (get_sym_code_type): Check the symbol's section. Do not check - mapping symbols. - (print_insn): Default to disassembling ARM mode code. Check - for mapping symbols separately from other symbols. Use - struct arm_private_data. - -2010-01-28 H.J. Lu - - * i386-dis.c (EXVexWdqScalar): New. - (vex_scalar_w_dq_mode): Likewise. - (prefix_table): Update entries for PREFIX_VEX_3899, - PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F, - PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD, - PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB, - PREFIX_VEX_38BD and PREFIX_VEX_38BF. - (intel_operand_size): Handle vex_scalar_w_dq_mode. - (OP_EX): Likewise. + * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. -2010-01-27 H.J. Lu - - * i386-dis.c (XMScalar): New. - (EXdScalar): Likewise. - (EXqScalar): Likewise. - (EXqScalarS): Likewise. - (VexScalar): Likewise. - (EXdVexScalarS): Likewise. - (EXqVexScalarS): Likewise. - (XMVexScalar): Likewise. - (scalar_mode): Likewise. - (d_scalar_mode): Likewise. - (d_scalar_swap_mode): Likewise. - (q_scalar_mode): Likewise. - (q_scalar_swap_mode): Likewise. - (vex_scalar_mode): Likewise. - (vex_len_table): Duplcate entries for VEX_LEN_10_P_1, - VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1, - VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0, - VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3, - VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3, - VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1, - VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1, - VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2, - VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1, - VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2. - (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3, - VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2, - VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3, - VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3, - VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3, - VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3, - VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3, - VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3, - VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2. - (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode, - q_scalar_mode, q_scalar_swap_mode. - (OP_XMM): Handle scalar_mode. - (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode - and q_scalar_swap_mode. - (OP_VEX): Handle vex_scalar_mode. - -2010-01-24 H.J. Lu - - * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. - -2010-01-24 H.J. Lu - - * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }. - -2010-01-24 H.J. Lu - - * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. - -2010-01-24 H.J. Lu - - * i386-dis.c (Bad_Opcode): New. - (bad_opcode): Likewise. - (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }. - (dis386_twobyte): Likewise. - (reg_table): Likewise. - (prefix_table): Likewise. - (x86_64_table): Likewise. - (vex_len_table): Likewise. - (vex_w_table): Likewise. - (mod_table): Likewise. - (rm_table): Likewise. - (float_reg): Likewise. - (reg_table): Remove trailing "(bad)" entries. - (prefix_table): Likewise. - (x86_64_table): Likewise. - (vex_len_table): Likewise. - (vex_w_table): Likewise. - (mod_table): Likewise. - (rm_table): Likewise. - (get_valid_dis386): Handle bytemode 0. +2011-01-11 Mingjie Xing -2010-01-23 H.J. Lu + * mips-dis.c (print_insn_args): Adjust the value to print the real + offset for "+c" argument. - * i386-opc.h (VEXScalar): New. +2011-01-10 Nick Clifton - * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar - instructions. - * i386-tbl.h: Regenerated. - -2010-01-21 H.J. Lu - - * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. - - * i386-opc.tbl: Add xsave64 and xrstor64. - * i386-tbl.h: Regenerated. + * po/da.po: Updated Danish translation. -2010-01-20 Nick Clifton +2011-01-05 Nathan Sidwell - PR 11170 - * arm-dis.c (print_arm_address): Do not ignore negative bit in PC - based post-indexed addressing. + * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear. -2010-01-15 Sebastian Pop +2011-01-04 H.J. Lu - * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. - * i386-tbl.h: Regenerated. - -2010-01-14 H.J. Lu - - * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in - comments. - -2010-01-14 H.J. Lu - - * i386-dis.c (names_mm): New. - (intel_names_mm): Likewise. - (att_names_mm): Likewise. - (names_xmm): Likewise. - (intel_names_xmm): Likewise. - (att_names_xmm): Likewise. - (names_ymm): Likewise. - (intel_names_ymm): Likewise. - (att_names_ymm): Likewise. - (print_insn): Set names_mm, names_xmm and names_ymm. - (OP_MMX): Use names_mm, names_xmm and names_ymm. - (OP_XMM): Likewise. - (OP_EM): Likewise. - (OP_EMC): Likewise. - (OP_MXC): Likewise. - (OP_EX): Likewise. - (XMM_Fixup): Likewise. - (OP_VEX): Likewise. - (OP_EX_VexReg): Likewise. - (OP_Vex_2src): Likewise. - (OP_Vex_2src_1): Likewise. - (OP_Vex_2src_2): Likewise. - (OP_REG_VexI4): Likewise. + * i386-dis.c (REG_VEX_38F3): New. + (PREFIX_0FBC): Likewise. + (PREFIX_VEX_38F2): Likewise. + (PREFIX_VEX_38F3_REG_1): Likewise. + (PREFIX_VEX_38F3_REG_2): Likewise. + (PREFIX_VEX_38F3_REG_3): Likewise. + (PREFIX_VEX_38F7): Likewise. + (VEX_LEN_38F2_P_0): Likewise. + (VEX_LEN_38F3_R_1_P_0): Likewise. + (VEX_LEN_38F3_R_2_P_0): Likewise. + (VEX_LEN_38F3_R_3_P_0): Likewise. + (VEX_LEN_38F7_P_0): Likewise. + (dis386_twobyte): Use PREFIX_0FBC. + (reg_table): Add REG_VEX_38F3. + (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2, + PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2, + PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7. + (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and + PREFIX_VEX_38F7. + (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0, + VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and + VEX_LEN_38F7_P_0. -2010-01-13 H.J. Lu + * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS. + (cpu_flags): Add CpuBMI. - * i386-dis.c (print_insn): Update comments. + * i386-opc.h (CpuBMI): New. + (i386_cpu_flags): Add cpubmi. -2010-01-12 H.J. Lu - - * i386-dis.c (rex_original): Removed. - (ckprefix): Remove rex_original. - (print_insn): Update comments. - -2010-01-09 Ralf Wildenhues - - * Makefile.in: Regenerate. - * configure: Regenerate. + * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. -2010-01-07 Doug Evans +2011-01-04 H.J. Lu - * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup. - * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, - * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, - * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, - * xstormy16-ibld.c: Regenerate. + * i386-dis.c (VexGdq): New. + (OP_VEX): Handle dq_mode. -2010-01-06 Quentin Neill +2011-01-01 H.J. Lu - * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS. - * i386-init.h: Regenerated. + * i386-gen.c (process_copyright): Update copyright to 2011. -2010-01-06 Daniel Gutson - - * arm-dis.c (print_insn): Fixed search for next symbol and data - dumping condition, and the initial mapping symbol state. - -2010-01-05 Doug Evans - - * cgen-ibld.in: #include "cgen/basic-modes.h". - * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, - * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, - * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, - * xstormy16-ibld.c: Regenerate. - -2010-01-04 Nick Clifton - - PR 11123 - * arm-dis.c (print_insn_coprocessor): Initialise value. - -2010-01-04 Edmar Wienskoski - - * ppc-dis.c (ppc_opts): Add entry for "e500mc64". - -2010-01-02 Doug Evans - - * cgen-asm.in: Update copyright year. - * cgen-dis.in: Update copyright year. - * cgen-ibld.in: Update copyright year. - * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c, - * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c, - * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h, - * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c, - * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c, - * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c, - * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c, - * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h, - * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h, - * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c, - * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c, - * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c, - * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h, - * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c, - * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c, - * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c, - * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c, - * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c, - * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c, - * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c, - * xstormy16-opc.c, * xstormy16-opc.h: Regenerate. - -For older changes see ChangeLog-2009 +For older changes see ChangeLog-2010 Local Variables: mode: change-log