X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=8b10771fbbf32bdd9f46bfe24c0515d0169080e0;hb=e76ff5abe375e1e7535f7827db01bce70bc9710d;hp=f311e1dedfdbbc26136d72ccd989d202f3e33d34;hpb=87a8d6cbe0768ba278220a71b2ecb02e441f7403;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f311e1dedf..8b10771fbb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,300 @@ +2013-07-07 Richard Sandiford + + * micromips-opc.c (WR_mhi): Rename to.. + (WR_mh): ...this. + (micromips_opcodes): Update "movep" entry accordingly. Replace + "mh,mi" with "mh". + * mips-dis.c (micromips_to_32_reg_h_map): Rename to... + (micromips_to_32_reg_h_map1): ...this. + (micromips_to_32_reg_i_map): Rename to... + (micromips_to_32_reg_h_map2): ...this. + (print_micromips_insn): Remove "mi" case. Print both registers + in the pair for "mh". + +2013-07-07 Richard Sandiford + + * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. + * micromips-opc.c (micromips_opcodes): Likewise. + * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" + and "+T" handling. Check for a "0" suffix when deciding whether to + use coprocessor 0 names. In that case, also check for ",H" selectors. + +2013-07-05 Andreas Krebbel + + * s390-opc.c (J12_12, J24_24): New macros. + (INSTR_MII_UPI): Rename to INSTR_MII_UPP. + (MASK_MII_UPI): Rename to MASK_MII_UPP. + * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. + +2013-07-04 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu. + +2013-06-26 Nick Clifton + + * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss + field when checking for type 2 nop. + * rx-decode.c: Regenerate. + +2013-06-25 Maciej W. Rozycki + + * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" + and "movep" macros. + +2013-06-24 Maciej W. Rozycki + + * mips-dis.c (is_mips16_plt_tail): New function. + (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address + word. + (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries. + +2013-06-21 DJ Delorie + + * msp430-decode.opc: New. + * msp430-decode.c: New/generated. + * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c. + (MAINTAINER_CLEANFILES): Likewise. + Add rule to build msp430-decode.c frommsp430decode.opc + using the opc2c program. + * Makefile.in: Regenerate. + * configure.in: Add msp430-decode.lo to msp430 architecture files. + * configure: Regenerate. + +2013-06-20 Yufeng Zhang + + * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it. + (SYMTAB_AVAILABLE): Removed. + (#include "elf/aarch64.h): Ditto. + +2013-06-17 Catherine Moore + Maciej W. Rozycki + Chao-Ying Fu + + * micromips-opc.c (EVA): Define. + (TLBINV): Define. + (micromips_opcodes): Add EVA opcodes. + * mips-dis.c (mips_arch_choices): Update for ASE_EVA. + (print_insn_args): Handle EVA offsets. + (print_insn_micromips): Likewise. + * mips-opc.c (EVA): Define. + (TLBINV): Define. + (mips_builtin_opcodes): Add EVA opcodes. + +2013-06-17 Alan Modra + + * Makefile.am (mips-opc.lo): Add rules to create automatic + dependency files. Pass archdefs. + (micromips-opc.lo, mips16-opc.lo): Likewise. + * Makefile.in: Regenerate. + +2013-06-14 DJ Delorie + + * rx-decode.opc (rx_decode_opcode): Bit operations on + registers are 32-bit operations, not 8-bit operations. + * rx-decode.c: Regenerate. + +2013-06-13 Chao-ying Fu + + * micromips-opc.c (IVIRT): New define. + (IVIRT64): New define. + (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, + tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions. + + * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0, + dmtgc0 to print cp0 names. + +2013-06-09 Sandra Loosemore + + * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b" + argument. + +2013-06-08 Catherine Moore + Richard Sandiford + + * micromips-opc.c (D32, D33, MC): Update definitions. + (micromips_opcodes): Initialize ase field. + * mips-dis.c (mips_arch_choice): Add ase field. + (mips_arch_choices): Initialize ase field. + (set_default_mips_dis_options): Declare and setup mips_ase. + * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, + MT32, MC): Update definitions. + (mips_builtin_opcodes): Initialize ase field. + +2013-05-24 Richard Sandiford + + * s390-opc.txt (flogr): Require a register pair destination. + +2013-05-23 Andreas Krebbel + + * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU + instruction format. + +2013-05-22 Jürgen Urban + + * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. + +2013-05-20 Peter Bergner + + * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8. + * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK, + XLS_MASK, PPCVSX2): New defines. + (powerpc_opcodes) : New instructions. + : New extended mnemonics. + +2013-05-17 Alan Modra + + * ia64-raw.tbl: Replace non-ASCII char. + * ia64-waw.tbl: Likewise. + * ia64-asmtab.c: Regenerate. + +2013-05-15 Saravanan Ekanathan + + * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS. + * i386-init.h: Regenerated. + +2013-05-13 Yufeng Zhang + + * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion. + * aarch64-opc.c (operand_general_constraint_met_p): Relax the range + check from [0, 255] to [-128, 255]. + +2013-05-09 Andrew Pinski + + * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2. + Add INSN_VIRT and INSN_VIRT64 to mips64r2. + (parse_mips_dis_option): Handle the virt option. + (print_insn_args): Handle "+J". + (print_mips_disassembler_options): Print out message about virt64. + * mips-opc.c (IVIRT): New define. + (IVIRT64): New define. + (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, + tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. + Move rfe to the bottom as it conflicts with tlbgp. + +2013-05-09 Alan Modra + + * ppc-opc.c (extract_vlesi): Properly sign extend. + (extract_vlensi): Likewise. Comment reason for setting invalid. + +2013-05-02 Nick Clifton + + * msp430-dis.c: Add support for MSP430X instructions. + +2013-04-24 Sandra Loosemore + + * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register + to "eccinj". + +2013-04-17 Wei-chen Wang + + PR binutils/15369 + * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead + of CGEN_CPU_ENDIAN. + (hash_insns_list): Likewise. + +2013-04-10 Jan Kratochvil + + * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false + warning workaround. + +2013-04-08 Jan Beulich + + * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries. + * i386-tbl.h: Re-generate. + +2013-04-06 David S. Miller + + * sparc-dis.c (compare_opcodes): When encountering multiple aliases + of an opcode, prefer the one with F_PREFERRED set. + * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, + lzcnt, flush with '[address]' syntax, and missing cbcond pseudo + ops. Make 64-bit VIS logical ops have "d" suffix in their names, + mark existing mnenomics as aliases. Add "cc" suffix to edge + instructions generating condition codes, mark existing mnenomics + as aliases. Add "fp" prefix to VIS compare instructions, mark + existing mnenomics as aliases. + +2013-04-03 Nick Clifton + + * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the + destination address by subtracting the operand from the current + address. + * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store + a positive value in the insn. + (extract_u16_loop): Do not negate the returned value. + (D16_LOOP): Add V850_INVERSE_PCREL flag. + + (ceilf.sw): Remove duplicate entry. + (cvtf.hs): New entry. + (cvtf.sh): Likewise. + (fmaf.s): Likewise. + (fmsf.s): Likewise. + (fnmaf.s): Likewise. + (fnmsf.s): Likewise. + (maddf.s): Restrict to E3V5 architectures. + (msubf.s): Likewise. + (nmaddf.s): Likewise. + (nmsubf.s): Likewise. + +2013-03-27 H.J. Lu + + * i386-dis.c (get_sib): Add the sizeflag argument. Properly + check address mode. + (print_insn): Pass sizeflag to get_sib. + +2013-03-27 Alexis Deruelle + + PR binutils/15068 + * tic6x-dis.c: Add support for displaying 16-bit insns. + +2013-03-20 Alexis Deruelle + + PR gas/15095 + * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have + individual msb and lsb halves in src1 & src2 fields. Discard the + src1 (lsb) value and only use src2 (msb), discarding bit 0, to + follow what Ti SDK does in that case as any value in the src1 + field yields the same output with SDK disassembler. + +2013-03-12 Michael Eager + + * opcodes/mips-dis.c (print_insn_args): Modify def of reg. + +2013-03-11 Sebastian Huber + + * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs. + +2013-03-11 Sebastian Huber + + * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs. + +2013-03-11 Sebastian Huber + + * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register. + +2013-03-11 Kyrylo Tkachov + + * arm-dis.c (arm_opcodes): Add entries for CRC instructions. + (thumb32_opcodes): Likewise. + (print_insn_thumb32): Handle 'S' control char. + 2013-03-08 Yann Sionneau * lm32-desc.c: Regenerate.