X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=9399da71f8e72a89fb7686e8fd753322f02219bf;hb=9f6a6cc022e1be500d3e49da1ad8bb2463b6da1b;hp=85512d72331d4fe3824a9dfd53f5934b161b3288;hpb=9bf29d72d48ef0ad6966bcb23ab3fdc5cc3c22fa;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 85512d7233..9399da71f8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,649 +1,644 @@ -2011-09-08 Mark Fortescue - - The changes below bring 'mov' and 'ticc' instructions into line - with the V8 SPARC Architecture Manual. - * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'. - * sparc-opc.c (sparc_opcodes): Add alias entries for - 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs'; - 'mov regrs2,%wim' and 'mov regrs2,%tbr'. - * sparc-opc.c (sparc_opcodes): Move/Change entries for - 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim' - and 'mov imm,%tbr'. - * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above - mov aliases. - -2011-09-08 David S. Miller - - * sparc-opc.c (pdistn): Destination is integer not float register. - -2011-09-07 Andreas Schwab - - * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a. - -2011-08-26 Nick Clifton - - * po/es.po: Updated Spanish translation. - -2011-08-22 Nick Clifton - - * Makefile.am (CPUDIR): Redfine to point to top level cpu - directory. - (stamp-frv): Use CPUDIR. - (stamp-iq2000): Likewise. - (stamp-lm32): Likewise. - (stamp-m32c): Likewise. - (stamp-mt): Likewise. - (stamp-xc16x): Likewise. - * Makefile.in: Regenerate. - -2011-08-09 Chao-ying Fu - Maciej W. Rozycki - - * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" - and "mips64r2". - (print_insn_args, print_insn_micromips): Handle MCU. - * micromips-opc.c (MC): New macro. - (micromips_opcodes): Add "aclr", "aset" and "iret". - * mips-opc.c (MC): New macro. - (mips_builtin_opcodes): Add "aclr", "aset" and "iret". - -2011-08-09 Maciej W. Rozycki - - * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros. - (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise. - (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise. - (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros. - (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise. - (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise. - (WR_s): Update macro. - (micromips_opcodes): Update register use flags of: "addiu", - "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu", - "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j", - "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li", - "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not", - "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw", - "swm" and "xor" instructions. - -2011-08-05 David S. Miller - - * sparc-dis.c (v9a_ast_reg_names): Add "cps". - (X_RS3): New macro. - (print_insn_sparc): Handle '4', '5', and '(' format codes. - Accept %asr numbers below 28. - * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3 - instructions. - -2011-08-02 Quentin Neill - - * i386-dis.c (xop_table): Remove spurious bextr insn. - -2011-08-01 H.J. Lu - - PR ld/13048 - * i386-dis.c (print_insn): Optimize info->mach check. - -2011-08-01 H.J. Lu - - PR gas/13046 - * i386-opc.tbl: Add Disp32S to 64bit call. - * i386-tbl.h: Regenerated. - -2011-07-24 Chao-ying Fu - Maciej W. Rozycki - - * micromips-opc.c: New file. - * mips-dis.c (micromips_to_32_reg_b_map): New array. - (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise. - (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise. - (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise. - (micromips_to_32_reg_q_map): Likewise. - (micromips_imm_b_map, micromips_imm_c_map): Likewise. - (micromips_ase): New variable. - (is_micromips): New function. - (set_default_mips_dis_options): Handle microMIPS ASE. - (print_insn_micromips): New function. - (is_compressed_mode_p): Likewise. - (_print_insn_mips): Handle microMIPS instructions. - * Makefile.am (CFILES): Add micromips-opc.c. - * configure.in (bfd_mips_arch): Add micromips-opc.lo. +2012-08-15 Peter Bergner + + * ppc-opc.c : New extended mnemonics. + +2012-08-14 Maciej W. Rozycki + + * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local + macros, use local variables for info struct member accesses, + update the type of the variable used to hold the instruction + word. + (print_insn_mips, print_mips16_insn_arg): Likewise. + (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use + local variables for info struct member accesses. + (print_insn_micromips): Add GET_OP_S local macro. + (_print_insn_mips): Update the type of the variable used to hold + the instruction word. + +2012-08-13 Ian Bolton + Laurent Desnogues + Jim MacArthur + Marcus Shawcroft + Nigel Stephens + Ramana Radhakrishnan + Richard Earnshaw + Sofiane Naci + Tejas Belagod + Yufeng Zhang + + * Makefile.am: Add AArch64. * Makefile.in: Regenerate. + * aarch64-asm.c: New file. + * aarch64-asm.h: New file. + * aarch64-dis.c: New file. + * aarch64-dis.h: New file. + * aarch64-gen.c: New file. + * aarch64-opc.c: New file. + * aarch64-opc.h: New file. + * aarch64-tbl.h: New file. + * configure.in: Add AArch64. * configure: Regenerate. + * disassemble.c: Add AArch64. + * aarch64-asm-2.c: New file (automatically generated). + * aarch64-dis-2.c: New file (automatically generated). + * aarch64-opc-2.c: New file (automatically generated). + * po/POTFILES.in: Regenerate. - * mips-dis.c (micromips_to_32_reg_h_map): New variable. - (micromips_to_32_reg_i_map): Likewise. - (micromips_to_32_reg_m_map): Likewise. - (micromips_to_32_reg_n_map): New macro. - -2011-07-24 Maciej W. Rozycki - - * mips-opc.c (NODS): New macro. - (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT. - (DSP_VOLA): Likewise. - (mips_builtin_opcodes): Add NODS annotation to "deret" and - "eret". Replace INSN_SYNC with NODS throughout. Use NODS in - place of TRAP for "wait", "waiti" and "yield". - * mips16-opc.c (NODS): New macro. - (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT. - (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc", - "restore" and "save". - -2011-07-22 H.J. Lu - - * configure.in: Handle bfd_k1om_arch. - * configure: Regenerated. - - * disassemble.c (disassembler): Handle bfd_k1om_arch. - - * i386-dis.c (print_insn): Handle bfd_mach_k1om and - bfd_mach_k1om_intel_syntax. - - * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to - ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS. - (cpu_flags): Add CpuK1OM. +2012-08-13 Maciej W. Rozycki + + * micromips-opc.c (micromips_opcodes): Update comment. + * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor + instructions for IOCT as appropriate. + * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with + opcode_is_member. + * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with + the result of a check for the -Wno-missing-field-initializers + GCC option. + * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. + (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to + compilation. + (mips16-opc.lo): Likewise. + (micromips-opc.lo): Likewise. + * aclocal.m4: Regenerate. + * configure: Regenerate. + * Makefile.in: Regenerate. - * i386-opc.h (CpuK1OM): New. - (i386_cpu_flags): Add cpuk1om. +2012-08-11 Saravanan Ekanathan + PR gas/14423 + * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS. * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2011-07-12 Nick Clifton - - * arm-dis.c (print_insn_arm): Revert previous, undocumented, - accidental change. - -2011-07-01 Nick Clifton - - PR binutils/12329 - * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM - insns using post-increment addressing. -2011-06-30 H.J. Lu +2012-08-09 Nick Clifton - * i386-dis.c (vex_len_table): Update rorxS. + * po/vi.po: Updated Vietnamese translation. -2011-06-30 H.J. Lu +2012-08-07 Roland McGrath - AVX Programming Reference (June, 2011) - * i386-dis.c (vex_len_table): Correct rorxS. + * i386-dis.c (reg_table): Fill out REG_0F0D table with + AMD-reserved cases as "prefetch". + (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants. + (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise. + (reg_table): Use those under REG_0F18. + (mod_table): Add those cases as "nop/reserved". - * i386-opc.tbl: Correct rorx. - * i386-tbl.h: Regenerated. +2012-08-07 Jan Beulich -2011-06-29 H.J. Lu + * i386-opc.tbl: Remove "FIXME" comments from SVME instructions. - * tilegx-opc.c (find_opcode): Replace "index" with "i". - * tilepro-opc.c (find_opcode): Likewise. +2012-08-06 Roland McGrath -2011-06-29 Richard Sandiford + * i386-dis.c (print_insn): Print spaces between multiple excess + prefixes. Return actual number of excess prefixes consumed, + not always one. - * mips16-opc.c (jalrc, jrc): Move earlier in file. + * i386-dis.c (OP_REG): Ignore REX_B for segment register cases. -2011-06-21 H.J. Lu +2012-08-06 Roland McGrath + Victor Khimenko + H.J. Lu - * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and - PREFIX_VEX_0F388E. + * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG. + (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG. + (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG. + (OP_E_register): Likewise. + (OP_REG): For low 8 whole registers, treat REX_W like DFLAG. -2011-06-17 Andreas Schwab +2012-08-02 Jan-Benedict Glaw - * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ... - (MOSTLYCLEANFILES): ... here. - * Makefile.in: Regenerate. - -2011-06-14 Alan Modra - - * Makefile.in: Regenerate. + * configure.in: Formatting. + * configure: Regenerate. -2011-06-13 Walter Lee +2012-08-01 Alan Modra - * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c, - tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c. - * Makefile.in: Regenerate. - * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch. + * h8300-dis.c: Fix printf arg warnings. + * i960-dis.c: Likewise. + * mips-dis.c: Likewise. + * pdp11-dis.c: Likewise. + * sh-dis.c: Likewise. + * v850-dis.c: Likewise. + * configure.in: Formatting. * configure: Regenerate. - * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro. + * rl78-decode.c: Regenerate. * po/POTFILES.in: Regenerate. - * tilegx-dis.c: New file. - * tilegx-opc.c: New file. - * tilepro-dis.c: New file. - * tilepro-opc.c: New file. - -2011-06-10 H.J. Lu - - AVX Programming Reference (June, 2011) - * i386-dis.c (XMGatherQ): New. - * i386-dis.c (EXxmm_mb): New. - (EXxmm_mb): Likewise. - (EXxmm_mw): Likewise. - (EXxmm_md): Likewise. - (EXxmm_mq): Likewise. - (EXxmmdw): Likewise. - (EXxmmqd): Likewise. - (VexGatherQ): Likewise. - (MVexVSIBDWpX): Likewise. - (MVexVSIBQWpX): Likewise. - (xmm_mb_mode): Likewise. - (xmm_mw_mode): Likewise. - (xmm_md_mode): Likewise. - (xmm_mq_mode): Likewise. - (xmmdw_mode): Likewise. - (xmmqd_mode): Likewise. - (ymmxmm_mode): Likewise. - (vex_vsib_d_w_dq_mode): Likewise. - (vex_vsib_q_w_dq_mode): Likewise. - (MOD_VEX_0F385A_PREFIX_2): Likewise. - (MOD_VEX_0F388C_PREFIX_2): Likewise. - (MOD_VEX_0F388E_PREFIX_2): Likewise. - (PREFIX_0F3882): Likewise. - (PREFIX_VEX_0F3816): Likewise. - (PREFIX_VEX_0F3836): Likewise. - (PREFIX_VEX_0F3845): Likewise. - (PREFIX_VEX_0F3846): Likewise. - (PREFIX_VEX_0F3847): Likewise. - (PREFIX_VEX_0F3858): Likewise. - (PREFIX_VEX_0F3859): Likewise. - (PREFIX_VEX_0F385A): Likewise. - (PREFIX_VEX_0F3878): Likewise. - (PREFIX_VEX_0F3879): Likewise. - (PREFIX_VEX_0F388C): Likewise. - (PREFIX_VEX_0F388E): Likewise. - (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. - (PREFIX_VEX_0F38F5): Likewise. - (PREFIX_VEX_0F38F6): Likewise. - (PREFIX_VEX_0F3A00): Likewise. - (PREFIX_VEX_0F3A01): Likewise. - (PREFIX_VEX_0F3A02): Likewise. - (PREFIX_VEX_0F3A38): Likewise. - (PREFIX_VEX_0F3A39): Likewise. - (PREFIX_VEX_0F3A46): Likewise. - (PREFIX_VEX_0F3AF0): Likewise. - (VEX_LEN_0F3816_P_2): Likewise. - (VEX_LEN_0F3819_P_2): Likewise. - (VEX_LEN_0F3836_P_2): Likewise. - (VEX_LEN_0F385A_P_2_M_0): Likewise. - (VEX_LEN_0F38F5_P_0): Likewise. - (VEX_LEN_0F38F5_P_1): Likewise. - (VEX_LEN_0F38F5_P_3): Likewise. - (VEX_LEN_0F38F6_P_3): Likewise. - (VEX_LEN_0F38F7_P_1): Likewise. - (VEX_LEN_0F38F7_P_2): Likewise. - (VEX_LEN_0F38F7_P_3): Likewise. - (VEX_LEN_0F3A00_P_2): Likewise. - (VEX_LEN_0F3A01_P_2): Likewise. - (VEX_LEN_0F3A38_P_2): Likewise. - (VEX_LEN_0F3A39_P_2): Likewise. - (VEX_LEN_0F3A46_P_2): Likewise. - (VEX_LEN_0F3AF0_P_3): Likewise. - (VEX_W_0F3816_P_2): Likewise. - (VEX_W_0F3818_P_2): Likewise. - (VEX_W_0F3819_P_2): Likewise. - (VEX_W_0F3836_P_2): Likewise. - (VEX_W_0F3846_P_2): Likewise. - (VEX_W_0F3858_P_2): Likewise. - (VEX_W_0F3859_P_2): Likewise. - (VEX_W_0F385A_P_2_M_0): Likewise. - (VEX_W_0F3878_P_2): Likewise. - (VEX_W_0F3879_P_2): Likewise. - (VEX_W_0F3A00_P_2): Likewise. - (VEX_W_0F3A01_P_2): Likewise. - (VEX_W_0F3A02_P_2): Likewise. - (VEX_W_0F3A38_P_2): Likewise. - (VEX_W_0F3A39_P_2): Likewise. - (VEX_W_0F3A46_P_2): Likewise. - (MOD_VEX_0F3818_PREFIX_2): Removed. - (MOD_VEX_0F3819_PREFIX_2): Likewise. - (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. - (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. - (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. - (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. - (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. - (VEX_LEN_0F3A0E_P_2): Likewise. - (VEX_LEN_0F3A0F_P_2): Likewise. - (VEX_LEN_0F3A42_P_2): Likewise. - (VEX_LEN_0F3A4C_P_2): Likewise. - (VEX_W_0F3818_P_2_M_0): Likewise. - (VEX_W_0F3819_P_2_M_0): Likewise. - (prefix_table): Updated. - (three_byte_table): Likewise. - (vex_table): Likewise. - (vex_len_table): Likewise. - (vex_w_table): Likewise. - (mod_table): Likewise. - (putop): Handle "LW". - (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, - xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, - vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. - (OP_EX): Likewise. - (OP_E_memory): Handle vex_vsib_d_w_dq_mode and - vex_vsib_q_w_dq_mode. - (OP_XMM): Handle vex_vsib_q_w_dq_mode. - (OP_VEX): Likewise. - - * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS - and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, - CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. - (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. - (opcode_modifiers): Add VecSIB. - - * i386-opc.h (CpuAVX2): New. - (CpuBMI2): Likewise. - (CpuLZCNT): Likewise. - (CpuINVPCID): Likewise. - (VecSIB128): Likewise. - (VecSIB256): Likewise. - (VecSIB): Likewise. - (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. - (i386_opcode_modifier): Add vecsib. - - * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2011-06-03 Quentin Neill - - * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS. - * i386-init.h: Regenerated. - -2011-06-03 Nick Clifton - - PR binutils/12752 - * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for - computing address offsets. - (print_arm_address): Likewise. - (print_insn_arm): Likewise. - (print_insn_thumb16): Likewise. - (print_insn_thumb32): Likewise. - -2011-06-02 Jie Zhang - Nathan Sidwell - Maciej Rozycki - * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 - as address offset. - (print_arm_address): Likewise. Elide positive #0 appropriately. - (print_insn_arm): Likewise. - -2011-06-02 Nick Clifton - - PR gas/12752 - * arm-dis.c (print_insn_thumb32): Do not sign extend addresses - passed to print_address_func. - -2011-06-02 Nick Clifton - - * arm-dis.c: Fix spelling mistakes. - * op/opcodes.pot: Regenerate. - -2011-05-24 Andreas Krebbel - - * s390-opc.c: Replace S390_OPERAND_REG_EVEN with - S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type. - * s390-opc.txt: Fix cxr instruction type. - -2011-05-24 Andreas Krebbel - - * s390-opc.c: Add new instruction types marking register pair - operands. - * s390-opc.txt: Match instructions having register pair operands - to the new instruction types. +2012-07-31 Chao-Ying Fu + Catherine Moore + Maciej W. Rozycki -2011-05-19 Nick Clifton + * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. + (DSP_VOLA): Likewise. + (D32, D33): Likewise. + (micromips_opcodes): Add DSP ASE instructions. + * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases. + <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise. - * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2 - operands. +2012-07-31 Jan Beulich -2011-05-10 Quentin Neill + * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2 + instruction group. Mark as requiring AVX2. + * i386-tbl.h: Re-generate. - * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. - * i386-init.h: Regenerated. +2012-07-30 Nick Clifton -2011-04-27 Nick Clifton + * po/opcodes.pot: Updated template. + * po/es.po: Updated Spanish translation. + * po/fi.po: Updated Finnish translation. - * po/da.po: Updated Danish translation. +2012-07-27 Mike Frysinger -2011-04-26 Anton Blanchard + * configure.in (BFD_VERSION): Run bfd/configure --version and + parse the output of that. + * configure: Regenerate. - * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7. +2012-07-25 James Lemke -2011-04-21 DJ Delorie + * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns. - * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs. +2012-07-24 Stephan McCamant + Dr David Alan Gilbert + + PR binutils/13135 + * arm-dis.c: Add necessary casts for printing integer values. + Use %s when printing string values. + * hppa-dis.c: Likewise. + * m68k-dis.c: Likewise. + * microblaze-dis.c: Likewise. + * mips-dis.c: Likewise. + * sparc-dis.c: Likewise. + +2012-07-19 Michael Zolotukhin + + PR binutils/14355 + * i386-dis.c (VEX_LEN_0FXOP_08_CC): New. + (VEX_LEN_0FXOP_08_CD): Likewise. + (VEX_LEN_0FXOP_08_CE): Likewise. + (VEX_LEN_0FXOP_08_CF): Likewise. + (VEX_LEN_0FXOP_08_EC): Likewise. + (VEX_LEN_0FXOP_08_ED): Likewise. + (VEX_LEN_0FXOP_08_EE): Likewise. + (VEX_LEN_0FXOP_08_EF): Likewise. + (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq, + vpcomub, vpcomuw, vpcomud, vpcomuq. + (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC, + VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF, + VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE, + VEX_LEN_0FXOP_08_EF. + +2012-07-16 Michael Zolotukhin + + * i386-dis.c (PREFIX_0F38F6): New. + (prefix_table): Add adcx, adox instructions. + (three_byte_table): Use PREFIX_0F38F6. + (mod_table): Add rdseed instruction. + * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW. + (cpu_flags): Likewise. + * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW. + (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw. + * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend + prefetchw. + * i386-tbl.h: Regenerate. + * i386-init.h: Likewise. + +2012-07-05 Thomas Schwinge + + * mips-dis.c: Remove gratuitous newline. + +2012-07-05 Sean Keys + + * xgate-dis.c: Removed an IF statement that will + always be false due to overlapping operand masks. + * xgate-opc.c: Corrected 'com' opcode entry and + fixed spacing. + +2012-07-02 Roland McGrath + + * i386-opc.tbl: Add RepPrefixOk to nop. + * i386-tbl.h: Regenerate. + +2012-06-28 Nick Clifton + + * po/vi.po: Updated Vietnamese translation. + +2012-06-22 Roland McGrath + + * i386-opc.tbl: Add RepPrefixOk to ret. + * i386-tbl.h: Regenerate. + + * i386-opc.h (RepPrefixOk): New enum constant. + (i386_opcode_modifier): New bitfield 'repprefixok'. + * i386-gen.c (opcode_modifiers): Add RepPrefixOk. + * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all + instructions that have IsString. + * i386-tbl.h: Regenerate. + +2012-06-11 Andreas Schwab + + * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx) + (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx) + (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls) + (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst) + (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep) + (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls) + (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x) + (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx) + (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0. + +2012-05-19 Alan Modra + + * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h. + (get_powerpc_dialect): Detect VLE sections from ELF sh_flags. + +2012-05-18 Alan Modra + + * ia64-opc.c: Remove #include "ansidecl.h". + * z8kgen.c: Include sysdep.h first. + + * arc-dis.c: Include sysdep.h first, remove some redundant includes. + * bfin-dis.c: Likewise. + * i860-dis.c: Likewise. + * ia64-dis.c: Likewise. + * ia64-gen.c: Likewise. + * m68hc11-dis.c: Likewise. + * mmix-dis.c: Likewise. + * msp430-dis.c: Likewise. + * or32-dis.c: Likewise. + * rl78-dis.c: Likewise. + * rx-dis.c: Likewise. + * tic4x-dis.c: Likewise. + * tilegx-opc.c: Likewise. + * tilepro-opc.c: Likewise. * rx-decode.c: Regenerate. -2011-04-20 H.J. Lu - - * i386-init.h: Regenerated. - -2011-04-19 Quentin Neill - - * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits - from bdver1 flags. - -2011-04-13 Nick Clifton - - * v850-dis.c (disassemble): Always print a closing square brace if - an opening square brace was printed. - -2011-04-12 Nick Clifton - - PR binutils/12534 - * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn - patterns. - (print_insn_thumb32): Handle %L. - -2011-04-11 Julian Brown - - * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX. - (print_insn_thumb32): Add APSR bitmask support. - -2011-04-07 Paul Carroll - - * arm-dis.c (print_insn): init vars moved into private_data structure. - -2011-03-24 Mike Frysinger - - * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic. - -2011-03-22 Eric B. Weddington +2012-05-17 James Lemke - * avr-dis.c (avr_operand): Add opcode_str parameter. Check for - post-increment to support LPM Z+ instruction. Add support for 'E' - constraint for DES instruction. - (print_insn_avr): Adjust calls to avr_operand. Rename variable. + * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi. -2011-03-14 Richard Sandiford +2012-05-17 James Lemke - * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. + * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE. -2011-03-14 Richard Sandiford +2012-05-17 Daniel Richard G. + Nick Clifton - * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. - Use branch types instead. - (print_insn): Likewise. - -2011-02-28 Maciej W. Rozycki - - * mips-opc.c (mips_builtin_opcodes): Correct register use - annotation of "alnv.ps". - -2011-02-28 Maciej W. Rozycki - - * mips-opc.c (mips_builtin_opcodes): Add "pref" macro. - -2011-02-22 Mike Frysinger - - * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check. - -2011-02-22 Mike Frysinger - - * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS. - -2011-02-19 Mike Frysinger - - * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and - a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1, - av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts, - exception, end_of_registers, msize, memory, bfd_mach. - (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG, - LB0REG, LC1REG, LT1REG, LB1REG): Delete - (AXREG, AWREG, LCREG, LTREG, LBREG): Define. - (get_allreg): Change to new defines. Fallback to abort(). + PR 14072 + * configure.in: Add check that sysdep.h has been included before + any system header files. + * configure: Regenerate. + * config.in: Regenerate. + * sysdep.h: Generate an error if included before config.h. + * alpha-opc.c: Include sysdep.h before any other header file. + * alpha-dis.c: Likewise. + * avr-dis.c: Likewise. + * cgen-opc.c: Likewise. + * cr16-dis.c: Likewise. + * cris-dis.c: Likewise. + * crx-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d10v-opc.c: Likewise. + * d30v-dis.c: Likewise. + * d30v-opc.c: Likewise. + * h8500-dis.c: Likewise. + * i370-dis.c: Likewise. + * i370-opc.c: Likewise. + * m10200-dis.c: Likewise. + * m10300-dis.c: Likewise. + * micromips-opc.c: Likewise. + * mips-opc.c: Likewise. + * mips61-opc.c: Likewise. + * moxie-dis.c: Likewise. + * or32-opc.c: Likewise. + * pj-dis.c: Likewise. + * ppc-dis.c: Likewise. + * ppc-opc.c: Likewise. + * s390-dis.c: Likewise. + * sh-dis.c: Likewise. + * sh64-dis.c: Likewise. + * sparc-dis.c: Likewise. + * sparc-opc.c: Likewise. + * spu-dis.c: Likewise. + * tic30-dis.c: Likewise. + * tic54x-dis.c: Likewise. + * tic80-dis.c: Likewise. + * tic80-opc.c: Likewise. + * tilegx-dis.c: Likewise. + * tilepro-dis.c: Likewise. + * v850-dis.c: Likewise. + * v850-opc.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * xgate-dis.c: Likewise. + * xtensa-dis.c: Likewise. + * rl78-decode.opc: Likewise. + * rl78-decode.c: Regenerate. + * rx-decode.opc: Likewise. + * rx-decode.c: Regenerate. -2011-02-14 Mike Frysinger +2012-05-17 Alan Modra - * bfin-dis.c: Add whitespace/parenthesis where needed. + * ppc_dis.c: Don't include elf/ppc.h. -2011-02-14 Mike Frysinger +2012-05-16 Meador Inge - * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater - than 7. + * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg} + to PUSH/POP {reg}. -2011-02-13 Ralf Wildenhues +2012-05-15 James Murray + Stephane Carrez + * configure.in: Add S12X and XGATE co-processor support to m68hc11 + target. + * disassemble.c: Likewise. * configure: Regenerate. + * m68hc11-dis.c: Make objdump output more consistent, use hex + instead of decimal and use 0x prefix for hex. + * m68hc11-opc.c: Add S12X and XGATE opcodes. + +2012-05-14 James Lemke + + * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle. + (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines. + (vle_opcd_indices): New array. + (lookup_vle): New function. + (disassemble_init_powerpc): Revise for second (VLE) opcode table. + (print_insn_powerpc): Likewise. + * ppc-opc.c: Likewise. + +2012-05-14 Catherine Moore + Maciej W. Rozycki + Rhonda Wittels + Nathan Froyd + + * ppc-opc.c (insert_arx, extract_arx): New functions. + (insert_ary, extract_ary): New functions. + (insert_li20, extract_li20): New functions. + (insert_rx, extract_rx): New functions. + (insert_ry, extract_ry): New functions. + (insert_sci8, extract_sci8): New functions. + (insert_sci8n, extract_sci8n): New functions. + (insert_sd4h, extract_sd4h): New functions. + (insert_sd4w, extract_sd4w): New functions. + (insert_vlesi, extract_vlesi): New functions. + (insert_vlensi, extract_vlensi): New functions. + (insert_vleui, extract_vleui): New functions. + (insert_vleil, extract_vleil): New functions. + (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT. + (BI16, BI32, BO32, B8): New. + (B15, B24, CRD32, CRS): New. + (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG. + (DB, IMM20, RD, Rx, ARX, RY, RZ): New. + (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New. + (SH6_MASK): Use PPC_OPSHIFT_INV. + (SI8, UI5, OIMM5, UI7, BO16): New. + (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New. + (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV. + (ALLOW8_SPRG): New. + (insert_sprg, extract_sprg): Check ALLOW8_SPRG. + (OPVUP, OPVUP_MASK OPVUP): New + (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New. + (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New. + (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New. + (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New. + (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New. + (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New. + (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New. + (SE_IM5, SE_IM5_MASK): New. + (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New. + (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New. + (BO32DNZ, BO32DZ): New. + (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE. + (PPCVLE): New. + (powerpc_opcodes): Add new VLE instructions. Update existing + instruction to include PPCVLE if supported. + * ppc-dis.c (ppc_opts): Add vle entry. + (get_powerpc_dialect): New function. + (powerpc_init_dialect): VLE support. + (print_insn_big_powerpc): Call get_powerpc_dialect. + (print_insn_little_powerpc): Likewise. + (operand_value_powerpc): Handle negative shift counts. + (print_insn_powerpc): Handle 2-byte instruction lengths. + +2012-05-11 Daniel Richard G. + + PR binutils/14028 + * configure.in: Invoke ACX_HEADER_STRING. + * configure: Regenerate. + * config.in: Regenerate. + * sysdep.h: If STRINGS_WITH_STRING is defined then include both + string.h and strings.h. -2011-02-13 Mike Frysinger - - * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg. - -2011-02-13 Mike Frysinger +2012-05-11 Nick Clifton - * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output - dregs only when P is set, and dregs_lo otherwise. + PR binutils/14006 + * arm-dis.c (print_insn): Fix detection of instruction mode in + files containing multiple executable sections. -2011-02-13 Mike Frysinger +2012-05-03 Sean Keys - * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code. + * Makefile.in, configure: regenerate + * disassemble.c (disassembler): Recognize ARCH_XGATE. + * xgate-dis.c (read_memory, print_insn, print_insn_xgate): + New functions. + * configure.in: Recognize xgate. + * xgate-dis.c, xgate-opc.c: New files for support of xgate + * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly + and opcode generation for xgate. -2011-02-12 Mike Frysinger +2012-04-30 DJ Delorie - * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT. + * rx-decode.opc (MOV): Do not sign-extend immediates which are + already the maximum bit size. + * rx-decode.c: Regenerate. -2011-02-12 Mike Frysinger +2012-04-27 David S. Miller - * bfin-dis.c (machine_registers): Delete REG_GP. - (reg_names): Delete "GP". - (decode_allregs): Change REG_GP to REG_LASTREG. + * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'. + * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr. -2011-02-12 Mike Frysinger + * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'. + * sparc-dis.c (v9a_asr_reg_names): Add 'pause'. - * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, - M_IH, M_IU): Delete. + * sparc-opc.c (CBCOND): New define. + (CBCOND_XCC): Likewise. + (cbcond): New helper macro. + (sparc_opcodes): Add compare-and-branch instructions. -2011-02-11 Mike Frysinger + * sparc-dis.c (print_insn_sparc): Handle ')'. + * sparc-opc.c (sparc_opcodes): Add crypto instructions. - * bfin-dis.c (reg_names): Add const. - (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte, - decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs, - decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits, - decode_counters, decode_allregs): Likewise. + * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values + into new struct sparc_opcode 'hwcaps' field instead of 'flags'. -2011-02-09 Michael Snyder +2012-04-12 David S. Miller - * i386-dis.c (OP_J): Parenthesize expression to prevent - truncated addresses. - (print_insn): Fix indentation off-by-one. + * sparc-dis.c (X_DISP10): Define. + (print_insn_sparc): Handle '='. -2011-02-01 Nick Clifton +2012-04-01 Mike Frysinger - * po/da.po: Updated Danish translation. + * bfin-dis.c (fmtconst): Replace decimal handling with a single + sprintf call and the '*' field width. -2011-01-21 Dave Murphy +2012-03-23 Maxim Kuvyrkov - * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. + * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP. -2011-01-18 H.J. Lu +2012-03-16 Alan Modra - * i386-dis.c (sIbT): New. - (b_T_mode): Likewise. - (dis386): Replace sIb with sIbT on "pushT". - (x86_64_table): Replace sIb with Ib on "aam" and "aad". - (OP_sI): Handle b_T_mode. Properly sign-extend byte. + * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete. + (powerpc_opcd_indices): Bump array size. + (disassemble_init_powerpc): Set powerpc_opcd_indices entries + corresponding to unused opcodes to following entry. + (lookup_powerpc): New function, extracted and optimised from.. + (print_insn_powerpc): ..here. -2011-01-18 Jan Kratochvil +2012-03-15 Alan Modra + James Lemke + * disassemble.c (disassemble_init_for_target): Handle ppc init. + * ppc-dis.c (private): New var. + (powerpc_init_dialect): Don't return calloc failure, instead use + private. + (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define. + (powerpc_opcd_indices): New array. + (disassemble_init_powerpc): New function. + (print_insn_big_powerpc): Don't init dialect here. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Start search using powerpc_opcd_indices. + +2012-03-10 Edmar Wienskoski + + * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". + * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. + (PPCVEC2, PPCTMR, E6500): New short names. + (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, + mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, + lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, + lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, + lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC + optional operands on sync instruction for E6500 target. + +2012-03-08 Andreas Krebbel + + * s390-opc.txt: Set instruction type of pku to SS_L2RDRD. + +2012-02-27 Alan Modra + + * mt-dis.c: Regenerate. + +2012-02-27 Alan Modra + + * v850-opc.c (extract_v8): Rearrange to make it obvious this + is the inverse of corresponding insert function. + (extract_d22, extract_u9, extract_r4): Likewise. + (extract_d9): Correct sign extension. + (extract_d16_15): Don't assume "long" is 32 bits, and don't + rely on implementation defined behaviour for shift right of + signed types. + (extract_d16_16, extract_d17_16, extract_i9): Likewise. + (extract_d23): Likewise, and correct mask. + +2012-02-27 Alan Modra + + * crx-dis.c (print_arg): Mask constant to 32 bits. + * crx-opc.c (cst4_map): Use int array. + +2012-02-27 Alan Modra + + * arc-dis.c (BITS): Don't use shifts to mask off bits. + (FIELDD): Sign extend with xor,sub. + +2012-02-25 Walter Lee + + * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS. + * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and + TILEPRO_OPC_LW_TLS_SN. + +2012-02-21 H.J. Lu + + * i386-opc.h (HLEPrefixNone): New. + (HLEPrefixLock): Likewise. + (HLEPrefixAny): Likewise. + (HLEPrefixRelease): Likewise. + +2012-02-08 H.J. Lu + + * i386-dis.c (HLE_Fixup1): New. + (HLE_Fixup2): Likewise. + (HLE_Fixup3): Likewise. + (Ebh1): Likewise. + (Evh1): Likewise. + (Ebh2): Likewise. + (Evh2): Likewise. + (Ebh3): Likewise. + (Evh3): Likewise. + (MOD_C6_REG_7): Likewise. + (MOD_C7_REG_7): Likewise. + (RM_C6_REG_7): Likewise. + (RM_C7_REG_7): Likewise. + (XACQUIRE_PREFIX): Likewise. + (XRELEASE_PREFIX): Likewise. + (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, + cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use + Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. + (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, + not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use + MOD_C6_REG_7 and MOD_C7_REG_7. + (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. + (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and + xtest. + (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. + (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. + + * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and + CPU_RTM_FLAGS. + (cpu_flags): Add CpuHLE and CpuRTM. + (opcode_modifiers): Add HLEPrefixOk. + + * i386-opc.h (CpuHLE): New. + (CpuRTM): Likewise. + (HLEPrefixOk): Likewise. + (i386_cpu_flags): Add cpuhle and cpurtm. + (i386_opcode_modifier): Add hleprefixok. + + * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to + add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, + sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory + operand. Add xacquire, xrelease, xabort, xbegin, xend and + xtest. * i386-init.h: Regenerated. - * i386-tbl.h: Regenerated - -2011-01-17 Quentin Neill - - * i386-dis.c (REG_XOP_TBM_01): New. - (REG_XOP_TBM_02): New. - (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. - (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 - entries, and add bextr instruction. - - * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. - (cpu_flags): Add CpuTBM. - - * i386-opc.h (CpuTBM) New. - (i386_cpu_flags): Add bit cputbm. - - * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, - blcs, blsfill, blsic, t1mskc, and tzmsk. - -2011-01-12 DJ Delorie - - * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. + * i386-tbl.h: Likewise. -2011-01-11 Mingjie Xing +2012-01-24 DJ Delorie - * mips-dis.c (print_insn_args): Adjust the value to print the real - offset for "+c" argument. + * rl78-decode.opc (rl78_decode_opcode): Add NOT1. + * rl78-decode.c: Regenerate. -2011-01-10 Nick Clifton +2012-01-17 James Murray - * po/da.po: Updated Danish translation. + PR binutils/10173 + * cr16-dis.c (print_arg): Test symtab_size not num_symbols. -2011-01-05 Nathan Sidwell +2012-01-17 Andreas Schwab - * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear. + * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx + register and move them after pmove with PSR/PCSR register. -2011-01-04 H.J. Lu +2012-01-13 H.J. Lu - * i386-dis.c (REG_VEX_38F3): New. - (PREFIX_0FBC): Likewise. - (PREFIX_VEX_38F2): Likewise. - (PREFIX_VEX_38F3_REG_1): Likewise. - (PREFIX_VEX_38F3_REG_2): Likewise. - (PREFIX_VEX_38F3_REG_3): Likewise. - (PREFIX_VEX_38F7): Likewise. - (VEX_LEN_38F2_P_0): Likewise. - (VEX_LEN_38F3_R_1_P_0): Likewise. - (VEX_LEN_38F3_R_2_P_0): Likewise. - (VEX_LEN_38F3_R_3_P_0): Likewise. - (VEX_LEN_38F7_P_0): Likewise. - (dis386_twobyte): Use PREFIX_0FBC. - (reg_table): Add REG_VEX_38F3. - (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2, - PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2, - PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7. - (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and - PREFIX_VEX_38F7. - (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0, - VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and - VEX_LEN_38F7_P_0. + * i386-dis.c (mod_table): Add vmfunc. - * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS. - (cpu_flags): Add CpuBMI. + * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS. + (cpu_flags): CpuVMFUNC. - * i386-opc.h (CpuBMI): New. - (i386_cpu_flags): Add cpubmi. + * i386-opc.h (CpuVMFUNC): New. + (i386_cpu_flags): Add cpuvmfunc. - * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt. + * i386-opc.tbl: Add vmfunc. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. -2011-01-04 H.J. Lu - - * i386-dis.c (VexGdq): New. - (OP_VEX): Handle dq_mode. - -2011-01-01 H.J. Lu - - * i386-gen.c (process_copyright): Update copyright to 2011. - -For older changes see ChangeLog-2010 +For older changes see ChangeLog-2011 Local Variables: mode: change-log