X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=939f4f6c75c0febb7a4453cc119226c2064c3d8c;hb=df18fdba5dc9243d657c6e26a3a4e2c65e62b8bd;hp=840948fd2ed5c5c81959d466f216fe9fbf079c37;hpb=c1c69e839e3fa7b92b8c9b2d5a8a06d4f24db47a;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 840948fd2e..939f4f6c75 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,254 @@ +2014-05-09 H.J. Lu + + * i386-dis.c (ADDR16_PREFIX): Removed. + (ADDR32_PREFIX): Likewise. + (DATA16_PREFIX): Likewise. + (DATA32_PREFIX): Likewise. + (prefix_name): Updated. + (print_insn): Simplify data and address size prefixes processing. + +2014-05-08 Stefan Kristiansson + + * or1k-desc.c: Regenerated. + * or1k-desc.h: Likewise. + * or1k-opc.c: Likewise. + * or1k-opc.h: Likewise. + * or1k-opinst.c: Likewise. + +2014-05-07 Andrew Bennett + + * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction. + (I34): New define. + (I36): New define. + (I66): New define. + (I68): New define. + * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and + mips64r5. + (parse_mips_dis_option): Update MSA and virtualization support to + allow mips64r3 and mips64r5. + +2014-05-07 Andrew Bennett + + * mips-opc.c (G3): Remove I4. + +2014-05-05 H.J. Lu + + PR binutils/16893 + * i386-dis.c (twobyte_has_mandatory_prefix): New variable. + (end_codep): Likewise. + (mandatory_prefix): Likewise. + (active_seg_prefix): Likewise. + (ckprefix): Set active_seg_prefix to the active segment register + prefix. + (seg_prefix): Removed. + (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ + for prefix index. Ignore the index if it is invalid and the + mandatory prefix isn't required. + (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is + mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits + in used_prefixes here. Don't print unused prefixes. Check + active_seg_prefix for the active segment register prefix. + Restore the DFLAG bit in sizeflag if the data size prefix is + unused. Check the unused mandatory PREFIX_XXX prefixes + (append_seg): Only print the segment register which gets used. + (OP_E_memory): Check active_seg_prefix for the segment register + prefix. + (OP_OFF): Likewise. + (OP_OFF64): Likewise. + (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset. + +2014-05-02 H.J. Lu + + PR binutils/16886 + * config.in: Regenerated. + * configure: Likewise. + * configure.in: Check if sigsetjmp is available. + * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF. + (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP. + (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP. + * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF. + (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP. + (print_insn): Replace setjmp with OPCODES_SIGSETJMP. + * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF. + (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP. + (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP. + * sysdep.h (OPCODES_SIGJMP_BUF): New macro. + (OPCODES_SIGSETJMP): Likewise. + (OPCODES_SIGLONGJMP): Likewise. + * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF. + (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP. + (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP. + * xtensa-dis.c (dis_private): Replace jmp_buf with + OPCODES_SIGJMP_BUF. + (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP. + (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP. + * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF. + (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP. + (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP. + +2014-05-01 H.J. Lu + + PR binutils/16891 + * i386-dis.c (print_insn): Handle prefixes before fwait. + +2014-04-26 Alan Modra + + * po/POTFILES.in: Regenerate. + +2014-04-23 Andrew Bennett + + * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2 + to allow the MIPS XPA ASE. + (parse_mips_dis_option): Process the -Mxpa option. + * mips-opc.c (XPA): New define. + (mips_builtin_opcodes): Add MIPS XPA instructions and move the + locations of the ctc0 and cfc0 instructions. + +2014-04-22 Christian Svensson + + * Makefile.am: Remove openrisc and or32 support. Add support for or1k. + * configure.in: Likewise. + * disassemble.c: Likewise. + * or1k-asm.c: New file. + * or1k-desc.c: New file. + * or1k-desc.h: New file. + * or1k-dis.c: New file. + * or1k-ibld.c: New file. + * or1k-opc.c: New file. + * or1k-opc.h: New file. + * or1k-opinst.c: New file. + * Makefile.in: Regenerate. + * configure: Regenerate. + * openrisc-asm.c: Delete. + * openrisc-desc.c: Delete. + * openrisc-desc.h: Delete. + * openrisc-dis.c: Delete. + * openrisc-ibld.c: Delete. + * openrisc-opc.c: Delete. + * openrisc-opc.h: Delete. + * or32-dis.c: Delete. + * or32-opc.c: Delete. + +2014-04-04 Ilya Tocar + + * i386-dis.c (rm_table): Add encls, enclu. + * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS, + (cpu_flags): Add CpuSE1. + * i386-opc.h (enum): Add CpuSE1. + (i386_cpu_flags): Add cpuse1. + * i386-opc.tbl: Add encls, enclu. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2014-04-02 Anthony Green + + * moxie-opc.c (moxie_form1_opc_info): Add sign-extension + instructions, sex.b and sex.s. + +2014-03-26 Jiong Wang + + * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined + instructions. + +2014-03-20 Ilya Tocar + + * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps, + vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd, + vscatterqps. + * i386-tbl.h: Regenerate. + +2014-03-19 Jose E. Marchesi + + * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and + %hstick_enable added. + +2014-03-19 Nick Clifton + + * rx-decode.opc (bwl): Allow for bogus instructions with a size + field of 3. + (sbwl, ubwl, SCALE): Likewise. + * rx-decode.c: Regenerate. + +2014-03-12 Alan Modra + + * Makefile.in: Regenerate. + +2014-03-05 Alan Modra + + Update copyright years. + +2014-03-04 Heiher + + * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A. + +2014-03-04 Richard Sandiford + + * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions + so that they come after the Loongson extensions. + +2014-03-03 Alan Modra + + * i386-gen.c (process_copyright): Emit copyright notice on one line. + +2014-02-28 Alan Modra + + * msp430-decode.c: Regenerate. + +2014-02-27 Jiong Wang + + * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with + FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle. + +2014-02-27 Yufeng Zhang + + * aarch64-opc.c (print_register_offset_address): Call + get_int_reg_name to prepare the register name. + +2014-02-25 Ilya Tocar + + * i386-opc.tbl: Remove wrong variant of vcvtps2ph + * i386-tbl.h: Regenerate. + +2014-02-20 Ilya Tocar + + * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/ + (cpu_flags): Add CpuPREFETCHWT1. + * i386-init.h: Regenerate. + * i386-opc.h (CpuPREFETCHWT1): New. + (i386_cpu_flags): Add cpuprefetchwt1. + * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1. + * i386-tbl.h: Regenerate. + +2014-02-20 Ilya Tocar + + * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD, + to CpuAVX512F. + * i386-tbl.h: Regenerate. + +2014-02-19 H.J. Lu + + * i386-gen.c (output_cpu_flags): Don't output trailing space. + (output_opcode_modifier): Likewise. + (output_operand_type): Likewise. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2014-02-12 Ilya Tocar + + * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4, + MOD_0FC7_REG_5. + (PREFIX enum): Add PREFIX_0FAE_REG_7. + (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5. + (prefix_table): Add clflusopt. + (mod_table): Add xrstors, xsavec, xsaves. + * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS, + CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS. + (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC. + * i386-init.h: Regenerate. + * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves, + xsaves64, xsavec, xsavec64. + * i386-tbl.h: Regenerate. + 2014-02-10 Alan Modra * po/POTFILES.in: Regenerate.