X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=a855cc542a392ae8e5d488074074abe43086a278;hb=0b476c533b5e82f281e8438396c20fbad1e1daaa;hp=a50505bdf9174091be83883543ea264ff831258a;hpb=832969900575ca4d0f2f55f3915420c457dab8bc;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a50505bdf9..a855cc542a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,302 @@ +Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative + branchs relaxable. + +Tue Jan 28 15:57:34 1997 Ian Lance Taylor + + * mips-dis.c (print_insn_mips16): Set insn_info information. + (print_mips16_insn_arg): Likewise. + + * mips-dis.c (print_insn_mips16): Better handling of an extend + opcode followed by an instruction which can not be extended. + +Fri Jan 24 12:08:21 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Changed operand specifier for the + coldfire moveb instruction to not allow an address register as + destination. Although the documentation does not indicate that + this is invalid, experiments uncovered unexpected behavior. + Added a comment explaining the situation. Thanks to Andreas + Schwab for pointing this out to me. + +start-sanitize-tic80 +Wed Jan 22 20:13:51 1997 Fred Fish + + * tic80-opc.c (tic80_opcodes): Expand comment to note that the + entries are presorted so that entries with the same mnemonic are + adjacent to each other in the table. Sort the entries for each + instruction so that this is true. + +end-sanitize-tic80 +Mon Jan 20 12:48:57 1997 Andreas Schwab + + * m68k-dis.c: Include . + (print_insn_m68k): Sort the opcode table on the most significant + nibble of the opcode. + +start-sanitize-tic80 +Sat Jan 18 15:15:05 1997 Fred Fish + + * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", + "vsub", "vst", "xnor", and "xor" instructions. + (V_a1): Renamed from V_a, msb of accumulator reg number. + (V_a0): Add macro, lsb of accumulator reg number. + +Fri Jan 17 18:24:31 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Broke excessively long + function up into several smaller ones and arranged for + the instruction printing function to be callable recursively + to print vector instructions that have both a load and a + math instruction packed into a single opcode. + * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode + to explain why it comes after the other vector opcodes. + +end-sanitize-tic80 +Fri Jan 17 16:19:15 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire + move insns to handle immediate operands. + +Thu Jan 17 16:19:00 1997 Andreas Schwab + + * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". + fix operand mask in the "moveml" entries for the coldfire. + +start-sanitize-tic80 +Thu Jan 16 20:54:40 1997 Fred Fish + + * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): + New macros for building vector instruction opcodes. + (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and + FMT_LI, which were unused. The field is now a flags field. + Remove some opcodes that are possible, but illegal, such + as long immediate instructions with doubles for immediate + values. Add "vadd" and "vld" instructions. + +Wed Jan 15 18:59:51 1997 Fred Fish + + * tic80-opc.c (tic80_operands): Reorder some table entries to make + the order more logical. Move the shift alias instructions ("rotl", + "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be + interspersed with the regular sr.x and sl.x instructions. Add + and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", + "sub", "subu", "swcr", and "trap". + +Tue Jan 14 19:42:50 1997 Fred Fish + + * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS. + (OFF_SL_PC): Renamed from OFF_SL. + (OFF_SS_BR): New operand type for base relative operand. + (OFF_SL_BR): New operand type for base relative operand. + (REG_BASE): New operand type for base register operand. + (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp", + "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr", + "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr" + instructions. + * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width + 10 char field, padded with spaces on rhs, rather than a string + followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather + than old TIC80_OPERAND_RELATIVE. Add support for new + TIC80_OPERAND_BASEREL flag bit. + +Mon Jan 13 15:58:56 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Print floating point operands + as floats. + * tic80-opc.c (SPFI): Add single precision floating point + immediate operand type. + (ROTATE): Add rotate operand type for shifts. + (ENDMASK): Add for shifts. + (n): Macro for the 'n' bit. + (i): Macro for the 'i' bit. + (PD): Macro for the 'PD' field. + (P2): Macro for the 'P2' field. + (P1): Macro for the 'P1' field. + (tic80_opcodes): Add entries for "exts", "extu", "fadd", + "fcmp", and "fdiv". + +end-sanitize-tic80 +Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c (disassemble): Mask off unwanted bits after + adding in current address for pc-relative operands. + +start-sanitize-tic80 +Mon Jan 6 10:56:25 1997 Fred Fish + + * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. + (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. + * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names + changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. + (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, + REG_BASE_M_SI, REG_BASE_M_LI respectively. + (REG_SCALED, LSI_SCALED): New operand types. + (E): New macro for 'E' bit at bit 27. + (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap + opcodes, including the various size flavors (b,h,w,d) for + the direct load and store instructions. + +Sun Jan 5 12:18:14 1997 Fred Fish + + * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit + in an instruction. + * tic80-dis.c (print_insn_tic80): Change comma and paren handling. + Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. + * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. + (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. + (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode + masks with "MASK_* & ~M_*" to get the M bit reset. + (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. + +Sat Jan 4 19:05:05 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE + correctly. Add support for printing TIC80_OPERAND_BITNUM and + TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic + form. + * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, + CC, SICR, and LICR table entries. + (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", + "bcnd", and "brcr" opcodes. + +end-sanitize-tic80 +Fri Jan 3 18:32:11 1997 Fred Fish + + * ppc-opc.c (powerpc_operands): Make comment match the + actual fields (no shift field). + * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". +start-sanitize-tic80 + * tic80-dis.c (print_insn_tic80): Replace abort stub with a + partial implementation, work in progress. + * tic80-opc.c (tic80_operands): Begin construction operands table. + (tic80_opcodes): Continue populating opcodes table and start + filling in the operand indices. + (tic80_num_opcodes): Add this. +end-sanitize-tic80 + +Fri Jan 3 12:13:52 1997 Ian Lance Taylor + + * m68k-opc.c: Add #B case for moveq. + +Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Make sure all variables are initialized + before they are used. + +start-sanitize-v850 +Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Put curly-braces around operands + for "breakpoint" instruction. + +end-sanitize-v850 +Tue Dec 31 15:38:13 1996 Ian Lance Taylor + + * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. + (dep): Use ALL_CFLAGS rather than CFLAGS. + +start-sanitize-v850 +Tue Dec 31 15:09:16 1996 Michael Meissner + + * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY + flag. + +end-sanitize-v850 +Mon Dec 30 17:02:11 1996 Fred Fish + + * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. +start-sanitize-tic80 + (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. +end-sanitize-tic80 + +Mon Dec 30 11:38:01 1996 Ian Lance Taylor + + * mips16-opc.c: Add "abs". + +start-sanitize-tic80 +Sun Dec 29 10:58:22 1996 Fred Fish + + * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. + * disassemble.c (ARCH_tic80): Define if ARCH_all is defined. + (disassembler): Add bfd_arch_tic80 support to set disassemble + to print_insn_tic80. + * tic80-dis.c (print_insn_tic80): Add stub. + +Fri Dec 27 22:30:57 1996 Fred Fish + + * configure.in (arch in $selarchs): Add bfd_tic80_arch entry. + * configure: Regenerate with autoconf. + * tic80-dis.c: Add file. + * tic80-opc.c: Add file. + +end-sanitize-tic80 +start-sanitize-d10v +Fri Dec 20 14:30:19 1996 Martin M. Hunt + + * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link. + +end-sanitize-d10v +Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Add SIMM16N. + (mn10200_opcodes): Use it for some logicals and btst insns. + Add "break" and "trap" instructions. + + * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. + + * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". + +Sat Dec 14 22:36:20 1996 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): The base address of a PC + relative load or add now depends upon whether the instruction is + in a delay slot. + +Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c: Finish writing disassembler. + * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". + Fix mask for "jmp (an)". + + * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently + handle endianness issues for mn10300. + + * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". + +Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 + instruction. Fix opcode field for "movb (imm24),dn". + + * mn10200-opc.c (mn10200_operands): Fix insertion position + for DI operand. + +Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c: Create mn10200 opcode table. + * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, + but moving along nicely. + +Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Makefile.in (ALL_MACHINES): Add mips16-opc.o. + +Fri Dec 6 16:47:40 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Revert change to use < and > + specifiers for fmovem* instructions. + +Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Remove '$' register prefixing. + +Fri Dec 6 17:34:39 1996 Ian Lance Taylor + + * mips16-opc.c: Change opcode for entry/exit to avoid conflicting + with dsrl. + Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c: Add some comments explaining the various