X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=ac0e8914ffb0b6ca04692ed674fcb94bc4f2f8dd;hb=b79f7053dd3e33f7b5e61bac1f94be303b14fe77;hp=4c8ad0161e2f09479a85375c4f9c7ae890c09590;hpb=42164a7195927ffea7ad125ae132226c2fdec512;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4c8ad0161e..ac0e8914ff 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,635 @@ +2012-08-24 Matthew Gretton-Dann + + * arm-dis.c (thumb32_opcodes): Add DCPS instruction. + +2012-08-24 Matthew Gretton-Dann + + * arm-dis.c (arm_opcodes): Add SEVL. + (thumb_opcodes): Likewise. + (thumb32_opcodes): Likewise. + +2012-08-24 Matthew Gretton-Dann + + * arm-dis.c (data_barrier_option): New function. + (print_insn_arm): Use data_barrier_option. + (print_insn_thumb32): Use data_barrier_option. + +2012-08-24 Matthew Gretton-Dann + + * sparc-opc.c (4-argument crypto instructions): Fix encoding using + F3F4 macro. + +2012-08-20 Edmar Wienskoski + + * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub, + vabsduh, vabsduw, mviwsplt. + +2012-08-17 Nagajyothi Eggone + + * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and + CPU_BTVER2_FLAGS. + + * i386-opc.h: Update CpuPRFCHW comment. + + * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2012-08-17 Nick Clifton + + * po/uk.po: New Ukranian translation. + * configure.in (ALL_LINGUAS): Add uk. + * configure: Regenerate. + +2012-08-16 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and + RBX for the third operand. + <"lswi">: Use RAX for second and NBI for the third operand. + +2012-08-15 DJ Delorie + + * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01] + operands, so that data addresses can be corrected when not + ES-overridden. + * rl78-decode.c: Regenerate. + * rl78-dis.c (print_insn_rl78): Make order of modifiers + irrelevent. When the 'e' specifier is used on an operand and no + ES prefix is provided, adjust address to make it absolute. + +2012-08-15 Peter Bergner + + * ppc-opc.c : Use PPC_OPERAND_GPR. + +2012-08-15 Peter Bergner + + * ppc-opc.c : New extended mnemonics. + +2012-08-14 Maciej W. Rozycki + + * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local + macros, use local variables for info struct member accesses, + update the type of the variable used to hold the instruction + word. + (print_insn_mips, print_mips16_insn_arg): Likewise. + (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use + local variables for info struct member accesses. + (print_insn_micromips): Add GET_OP_S local macro. + (_print_insn_mips): Update the type of the variable used to hold + the instruction word. + +2012-08-13 Ian Bolton + Laurent Desnogues + Jim MacArthur + Marcus Shawcroft + Nigel Stephens + Ramana Radhakrishnan + Richard Earnshaw + Sofiane Naci + Tejas Belagod + Yufeng Zhang + + * Makefile.am: Add AArch64. + * Makefile.in: Regenerate. + * aarch64-asm.c: New file. + * aarch64-asm.h: New file. + * aarch64-dis.c: New file. + * aarch64-dis.h: New file. + * aarch64-gen.c: New file. + * aarch64-opc.c: New file. + * aarch64-opc.h: New file. + * aarch64-tbl.h: New file. + * configure.in: Add AArch64. + * configure: Regenerate. + * disassemble.c: Add AArch64. + * aarch64-asm-2.c: New file (automatically generated). + * aarch64-dis-2.c: New file (automatically generated). + * aarch64-opc-2.c: New file (automatically generated). + * po/POTFILES.in: Regenerate. + +2012-08-13 Maciej W. Rozycki + + * micromips-opc.c (micromips_opcodes): Update comment. + * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor + instructions for IOCT as appropriate. + * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with + opcode_is_member. + * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with + the result of a check for the -Wno-missing-field-initializers + GCC option. + * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. + (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to + compilation. + (mips16-opc.lo): Likewise. + (micromips-opc.lo): Likewise. + * aclocal.m4: Regenerate. + * configure: Regenerate. + * Makefile.in: Regenerate. + +2012-08-11 Saravanan Ekanathan + + PR gas/14423 + * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS. + * i386-init.h: Regenerated. + +2012-08-09 Nick Clifton + + * po/vi.po: Updated Vietnamese translation. + +2012-08-07 Roland McGrath + + * i386-dis.c (reg_table): Fill out REG_0F0D table with + AMD-reserved cases as "prefetch". + (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants. + (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise. + (reg_table): Use those under REG_0F18. + (mod_table): Add those cases as "nop/reserved". + +2012-08-07 Jan Beulich + + * i386-opc.tbl: Remove "FIXME" comments from SVME instructions. + +2012-08-06 Roland McGrath + + * i386-dis.c (print_insn): Print spaces between multiple excess + prefixes. Return actual number of excess prefixes consumed, + not always one. + + * i386-dis.c (OP_REG): Ignore REX_B for segment register cases. + +2012-08-06 Roland McGrath + Victor Khimenko + H.J. Lu + + * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG. + (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG. + (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG. + (OP_E_register): Likewise. + (OP_REG): For low 8 whole registers, treat REX_W like DFLAG. + +2012-08-02 Jan-Benedict Glaw + + * configure.in: Formatting. + * configure: Regenerate. + +2012-08-01 Alan Modra + + * h8300-dis.c: Fix printf arg warnings. + * i960-dis.c: Likewise. + * mips-dis.c: Likewise. + * pdp11-dis.c: Likewise. + * sh-dis.c: Likewise. + * v850-dis.c: Likewise. + * configure.in: Formatting. + * configure: Regenerate. + * rl78-decode.c: Regenerate. + * po/POTFILES.in: Regenerate. + +2012-07-31 Chao-Ying Fu + Catherine Moore + Maciej W. Rozycki + + * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. + (DSP_VOLA): Likewise. + (D32, D33): Likewise. + (micromips_opcodes): Add DSP ASE instructions. + * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases. + <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise. + +2012-07-31 Jan Beulich + + * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2 + instruction group. Mark as requiring AVX2. + * i386-tbl.h: Re-generate. + +2012-07-30 Nick Clifton + + * po/opcodes.pot: Updated template. + * po/es.po: Updated Spanish translation. + * po/fi.po: Updated Finnish translation. + +2012-07-27 Mike Frysinger + + * configure.in (BFD_VERSION): Run bfd/configure --version and + parse the output of that. + * configure: Regenerate. + +2012-07-25 James Lemke + + * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns. + +2012-07-24 Stephan McCamant + Dr David Alan Gilbert + + PR binutils/13135 + * arm-dis.c: Add necessary casts for printing integer values. + Use %s when printing string values. + * hppa-dis.c: Likewise. + * m68k-dis.c: Likewise. + * microblaze-dis.c: Likewise. + * mips-dis.c: Likewise. + * sparc-dis.c: Likewise. + +2012-07-19 Michael Zolotukhin + + PR binutils/14355 + * i386-dis.c (VEX_LEN_0FXOP_08_CC): New. + (VEX_LEN_0FXOP_08_CD): Likewise. + (VEX_LEN_0FXOP_08_CE): Likewise. + (VEX_LEN_0FXOP_08_CF): Likewise. + (VEX_LEN_0FXOP_08_EC): Likewise. + (VEX_LEN_0FXOP_08_ED): Likewise. + (VEX_LEN_0FXOP_08_EE): Likewise. + (VEX_LEN_0FXOP_08_EF): Likewise. + (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq, + vpcomub, vpcomuw, vpcomud, vpcomuq. + (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC, + VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF, + VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE, + VEX_LEN_0FXOP_08_EF. + +2012-07-16 Michael Zolotukhin + + * i386-dis.c (PREFIX_0F38F6): New. + (prefix_table): Add adcx, adox instructions. + (three_byte_table): Use PREFIX_0F38F6. + (mod_table): Add rdseed instruction. + * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW. + (cpu_flags): Likewise. + * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW. + (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw. + * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend + prefetchw. + * i386-tbl.h: Regenerate. + * i386-init.h: Likewise. + +2012-07-05 Thomas Schwinge + + * mips-dis.c: Remove gratuitous newline. + +2012-07-05 Sean Keys + + * xgate-dis.c: Removed an IF statement that will + always be false due to overlapping operand masks. + * xgate-opc.c: Corrected 'com' opcode entry and + fixed spacing. + +2012-07-02 Roland McGrath + + * i386-opc.tbl: Add RepPrefixOk to nop. + * i386-tbl.h: Regenerate. + +2012-06-28 Nick Clifton + + * po/vi.po: Updated Vietnamese translation. + +2012-06-22 Roland McGrath + + * i386-opc.tbl: Add RepPrefixOk to ret. + * i386-tbl.h: Regenerate. + + * i386-opc.h (RepPrefixOk): New enum constant. + (i386_opcode_modifier): New bitfield 'repprefixok'. + * i386-gen.c (opcode_modifiers): Add RepPrefixOk. + * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all + instructions that have IsString. + * i386-tbl.h: Regenerate. + +2012-06-11 Andreas Schwab + + * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx) + (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx) + (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls) + (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst) + (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep) + (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls) + (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x) + (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx) + (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0. + +2012-05-19 Alan Modra + + * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h. + (get_powerpc_dialect): Detect VLE sections from ELF sh_flags. + +2012-05-18 Alan Modra + + * ia64-opc.c: Remove #include "ansidecl.h". + * z8kgen.c: Include sysdep.h first. + + * arc-dis.c: Include sysdep.h first, remove some redundant includes. + * bfin-dis.c: Likewise. + * i860-dis.c: Likewise. + * ia64-dis.c: Likewise. + * ia64-gen.c: Likewise. + * m68hc11-dis.c: Likewise. + * mmix-dis.c: Likewise. + * msp430-dis.c: Likewise. + * or32-dis.c: Likewise. + * rl78-dis.c: Likewise. + * rx-dis.c: Likewise. + * tic4x-dis.c: Likewise. + * tilegx-opc.c: Likewise. + * tilepro-opc.c: Likewise. + * rx-decode.c: Regenerate. + +2012-05-17 James Lemke + + * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi. + +2012-05-17 James Lemke + + * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE. + +2012-05-17 Daniel Richard G. + Nick Clifton + + PR 14072 + * configure.in: Add check that sysdep.h has been included before + any system header files. + * configure: Regenerate. + * config.in: Regenerate. + * sysdep.h: Generate an error if included before config.h. + * alpha-opc.c: Include sysdep.h before any other header file. + * alpha-dis.c: Likewise. + * avr-dis.c: Likewise. + * cgen-opc.c: Likewise. + * cr16-dis.c: Likewise. + * cris-dis.c: Likewise. + * crx-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d10v-opc.c: Likewise. + * d30v-dis.c: Likewise. + * d30v-opc.c: Likewise. + * h8500-dis.c: Likewise. + * i370-dis.c: Likewise. + * i370-opc.c: Likewise. + * m10200-dis.c: Likewise. + * m10300-dis.c: Likewise. + * micromips-opc.c: Likewise. + * mips-opc.c: Likewise. + * mips61-opc.c: Likewise. + * moxie-dis.c: Likewise. + * or32-opc.c: Likewise. + * pj-dis.c: Likewise. + * ppc-dis.c: Likewise. + * ppc-opc.c: Likewise. + * s390-dis.c: Likewise. + * sh-dis.c: Likewise. + * sh64-dis.c: Likewise. + * sparc-dis.c: Likewise. + * sparc-opc.c: Likewise. + * spu-dis.c: Likewise. + * tic30-dis.c: Likewise. + * tic54x-dis.c: Likewise. + * tic80-dis.c: Likewise. + * tic80-opc.c: Likewise. + * tilegx-dis.c: Likewise. + * tilepro-dis.c: Likewise. + * v850-dis.c: Likewise. + * v850-opc.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * xgate-dis.c: Likewise. + * xtensa-dis.c: Likewise. + * rl78-decode.opc: Likewise. + * rl78-decode.c: Regenerate. + * rx-decode.opc: Likewise. + * rx-decode.c: Regenerate. + +2012-05-17 Alan Modra + + * ppc_dis.c: Don't include elf/ppc.h. + +2012-05-16 Meador Inge + + * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg} + to PUSH/POP {reg}. + +2012-05-15 James Murray + Stephane Carrez + + * configure.in: Add S12X and XGATE co-processor support to m68hc11 + target. + * disassemble.c: Likewise. + * configure: Regenerate. + * m68hc11-dis.c: Make objdump output more consistent, use hex + instead of decimal and use 0x prefix for hex. + * m68hc11-opc.c: Add S12X and XGATE opcodes. + +2012-05-14 James Lemke + + * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle. + (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines. + (vle_opcd_indices): New array. + (lookup_vle): New function. + (disassemble_init_powerpc): Revise for second (VLE) opcode table. + (print_insn_powerpc): Likewise. + * ppc-opc.c: Likewise. + +2012-05-14 Catherine Moore + Maciej W. Rozycki + Rhonda Wittels + Nathan Froyd + + * ppc-opc.c (insert_arx, extract_arx): New functions. + (insert_ary, extract_ary): New functions. + (insert_li20, extract_li20): New functions. + (insert_rx, extract_rx): New functions. + (insert_ry, extract_ry): New functions. + (insert_sci8, extract_sci8): New functions. + (insert_sci8n, extract_sci8n): New functions. + (insert_sd4h, extract_sd4h): New functions. + (insert_sd4w, extract_sd4w): New functions. + (insert_vlesi, extract_vlesi): New functions. + (insert_vlensi, extract_vlensi): New functions. + (insert_vleui, extract_vleui): New functions. + (insert_vleil, extract_vleil): New functions. + (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT. + (BI16, BI32, BO32, B8): New. + (B15, B24, CRD32, CRS): New. + (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG. + (DB, IMM20, RD, Rx, ARX, RY, RZ): New. + (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New. + (SH6_MASK): Use PPC_OPSHIFT_INV. + (SI8, UI5, OIMM5, UI7, BO16): New. + (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New. + (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV. + (ALLOW8_SPRG): New. + (insert_sprg, extract_sprg): Check ALLOW8_SPRG. + (OPVUP, OPVUP_MASK OPVUP): New + (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New. + (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New. + (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New. + (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New. + (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New. + (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New. + (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New. + (SE_IM5, SE_IM5_MASK): New. + (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New. + (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New. + (BO32DNZ, BO32DZ): New. + (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE. + (PPCVLE): New. + (powerpc_opcodes): Add new VLE instructions. Update existing + instruction to include PPCVLE if supported. + * ppc-dis.c (ppc_opts): Add vle entry. + (get_powerpc_dialect): New function. + (powerpc_init_dialect): VLE support. + (print_insn_big_powerpc): Call get_powerpc_dialect. + (print_insn_little_powerpc): Likewise. + (operand_value_powerpc): Handle negative shift counts. + (print_insn_powerpc): Handle 2-byte instruction lengths. + +2012-05-11 Daniel Richard G. + + PR binutils/14028 + * configure.in: Invoke ACX_HEADER_STRING. + * configure: Regenerate. + * config.in: Regenerate. + * sysdep.h: If STRINGS_WITH_STRING is defined then include both + string.h and strings.h. + +2012-05-11 Nick Clifton + + PR binutils/14006 + * arm-dis.c (print_insn): Fix detection of instruction mode in + files containing multiple executable sections. + +2012-05-03 Sean Keys + + * Makefile.in, configure: regenerate + * disassemble.c (disassembler): Recognize ARCH_XGATE. + * xgate-dis.c (read_memory, print_insn, print_insn_xgate): + New functions. + * configure.in: Recognize xgate. + * xgate-dis.c, xgate-opc.c: New files for support of xgate + * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly + and opcode generation for xgate. + +2012-04-30 DJ Delorie + + * rx-decode.opc (MOV): Do not sign-extend immediates which are + already the maximum bit size. + * rx-decode.c: Regenerate. + +2012-04-27 David S. Miller + + * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'. + * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr. + + * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'. + * sparc-dis.c (v9a_asr_reg_names): Add 'pause'. + + * sparc-opc.c (CBCOND): New define. + (CBCOND_XCC): Likewise. + (cbcond): New helper macro. + (sparc_opcodes): Add compare-and-branch instructions. + + * sparc-dis.c (print_insn_sparc): Handle ')'. + * sparc-opc.c (sparc_opcodes): Add crypto instructions. + + * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values + into new struct sparc_opcode 'hwcaps' field instead of 'flags'. + +2012-04-12 David S. Miller + + * sparc-dis.c (X_DISP10): Define. + (print_insn_sparc): Handle '='. + +2012-04-01 Mike Frysinger + + * bfin-dis.c (fmtconst): Replace decimal handling with a single + sprintf call and the '*' field width. + +2012-03-23 Maxim Kuvyrkov + + * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP. + +2012-03-16 Alan Modra + + * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete. + (powerpc_opcd_indices): Bump array size. + (disassemble_init_powerpc): Set powerpc_opcd_indices entries + corresponding to unused opcodes to following entry. + (lookup_powerpc): New function, extracted and optimised from.. + (print_insn_powerpc): ..here. + +2012-03-15 Alan Modra + James Lemke + + * disassemble.c (disassemble_init_for_target): Handle ppc init. + * ppc-dis.c (private): New var. + (powerpc_init_dialect): Don't return calloc failure, instead use + private. + (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define. + (powerpc_opcd_indices): New array. + (disassemble_init_powerpc): New function. + (print_insn_big_powerpc): Don't init dialect here. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Start search using powerpc_opcd_indices. + +2012-03-10 Edmar Wienskoski + + * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". + * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. + (PPCVEC2, PPCTMR, E6500): New short names. + (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, + mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, + lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, + lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, + lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC + optional operands on sync instruction for E6500 target. + +2012-03-08 Andreas Krebbel + + * s390-opc.txt: Set instruction type of pku to SS_L2RDRD. + +2012-02-27 Alan Modra + + * mt-dis.c: Regenerate. + +2012-02-27 Alan Modra + + * v850-opc.c (extract_v8): Rearrange to make it obvious this + is the inverse of corresponding insert function. + (extract_d22, extract_u9, extract_r4): Likewise. + (extract_d9): Correct sign extension. + (extract_d16_15): Don't assume "long" is 32 bits, and don't + rely on implementation defined behaviour for shift right of + signed types. + (extract_d16_16, extract_d17_16, extract_i9): Likewise. + (extract_d23): Likewise, and correct mask. + +2012-02-27 Alan Modra + + * crx-dis.c (print_arg): Mask constant to 32 bits. + * crx-opc.c (cst4_map): Use int array. + +2012-02-27 Alan Modra + + * arc-dis.c (BITS): Don't use shifts to mask off bits. + (FIELDD): Sign extend with xor,sub. + +2012-02-25 Walter Lee + + * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS. + * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and + TILEPRO_OPC_LW_TLS_SN. + +2012-02-21 H.J. Lu + + * i386-opc.h (HLEPrefixNone): New. + (HLEPrefixLock): Likewise. + (HLEPrefixAny): Likewise. + (HLEPrefixRelease): Likewise. + 2012-02-08 H.J. Lu * i386-dis.c (HLE_Fixup1): New.