X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=b14b2bfba2448c250f3500a73f761344814e9d5a;hb=78c8d46ca4fdaf8cacbc622095eace3467f38356;hp=29b93910b5ec569dfc183c59b9833b0bde6418ef;hpb=9eb6c0f132631312886f7084d96448e46a053fb8;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 29b93910b5..b14b2bfba2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,725 +1,116 @@ -2012-08-24 Matthew Gretton-Dann +2013-01-24 Nick Clifton - * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions. - (thumb32_opcodes): Likewise. - (print_arm_insn): Add support for %<>T formatter. - -2012-08-24 Matthew Gretton-Dann - - * arm-dis.c (arm_opcodes): Add HLT. - (thumb_opcodes): Likewise. - -2012-08-24 Matthew Gretton-Dann - - * arm-dis.c (thumb32_opcodes): Add DCPS instruction. - -2012-08-24 Matthew Gretton-Dann - - * arm-dis.c (arm_opcodes): Add SEVL. - (thumb_opcodes): Likewise. - (thumb32_opcodes): Likewise. - -2012-08-24 Matthew Gretton-Dann - - * arm-dis.c (data_barrier_option): New function. - (print_insn_arm): Use data_barrier_option. - (print_insn_thumb32): Use data_barrier_option. - -2012-08-24 Matthew Gretton-Dann - - * sparc-opc.c (4-argument crypto instructions): Fix encoding using - F3F4 macro. - -2012-08-20 Edmar Wienskoski + * v850-dis.c: Add support for e3v5 architecture. + * v850-opc.c: Likewise. - * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub, - vabsduh, vabsduw, mviwsplt. +2013-01-17 Yufeng Zhang -2012-08-17 Nagajyothi Eggone + * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. + * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. + * aarch64-opc.c (operand_general_constraint_met_p): For + AARCH64_MOD_LSL, move the range check on the shift amount before the + alignment check; change to call set_sft_amount_out_of_range_error + instead of set_imm_out_of_range_error. + * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. + (aarch64_opcode_table): Remove the OP enumerator from the asimdimm + 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to + SIMD_IMM_SFT. - * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and - CPU_BTVER2_FLAGS. +2013-01-16 H.J. Lu - * i386-opc.h: Update CpuPRFCHW comment. + * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. - * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. -2012-08-17 Nick Clifton - - * po/uk.po: New Ukranian translation. - * configure.in (ALL_LINGUAS): Add uk. - * configure: Regenerate. - -2012-08-16 Peter Bergner - - * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and - RBX for the third operand. - <"lswi">: Use RAX for second and NBI for the third operand. - -2012-08-15 DJ Delorie +2013-01-15 Nick Clifton - * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01] - operands, so that data addresses can be corrected when not - ES-overridden. - * rl78-decode.c: Regenerate. - * rl78-dis.c (print_insn_rl78): Make order of modifiers - irrelevent. When the 'e' specifier is used on an operand and no - ES prefix is provided, adjust address to make it absolute. + * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE + values. + * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute. -2012-08-15 Peter Bergner +2013-01-14 Will Newton - * ppc-opc.c : Use PPC_OPERAND_GPR. + * metag-dis.c (REG_WIDTH): Increase to 64. -2012-08-15 Peter Bergner +2013-01-10 Peter Bergner - * ppc-opc.c : New extended mnemonics. + * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. + * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, + XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. + (SH6): Update. + <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", + "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", + "treclaim.", "tsr.">: Add POWER8 HTM opcodes. + <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. -2012-08-14 Maciej W. Rozycki +2013-01-10 Will Newton - * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local - macros, use local variables for info struct member accesses, - update the type of the variable used to hold the instruction - word. - (print_insn_mips, print_mips16_insn_arg): Likewise. - (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use - local variables for info struct member accesses. - (print_insn_micromips): Add GET_OP_S local macro. - (_print_insn_mips): Update the type of the variable used to hold - the instruction word. - -2012-08-13 Ian Bolton - Laurent Desnogues - Jim MacArthur - Marcus Shawcroft - Nigel Stephens - Ramana Radhakrishnan - Richard Earnshaw - Sofiane Naci - Tejas Belagod - Yufeng Zhang - - * Makefile.am: Add AArch64. + * Makefile.am: Add Meta. + * configure.in: Add Meta. + * disassemble.c: Add Meta support. + * metag-dis.c: New file. * Makefile.in: Regenerate. - * aarch64-asm.c: New file. - * aarch64-asm.h: New file. - * aarch64-dis.c: New file. - * aarch64-dis.h: New file. - * aarch64-gen.c: New file. - * aarch64-opc.c: New file. - * aarch64-opc.h: New file. - * aarch64-tbl.h: New file. - * configure.in: Add AArch64. - * configure: Regenerate. - * disassemble.c: Add AArch64. - * aarch64-asm-2.c: New file (automatically generated). - * aarch64-dis-2.c: New file (automatically generated). - * aarch64-opc-2.c: New file (automatically generated). - * po/POTFILES.in: Regenerate. - -2012-08-13 Maciej W. Rozycki - - * micromips-opc.c (micromips_opcodes): Update comment. - * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor - instructions for IOCT as appropriate. - * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with - opcode_is_member. - * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with - the result of a check for the -Wno-missing-field-initializers - GCC option. - * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. - (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to - compilation. - (mips16-opc.lo): Likewise. - (micromips-opc.lo): Likewise. - * aclocal.m4: Regenerate. - * configure: Regenerate. - * Makefile.in: Regenerate. - -2012-08-11 Saravanan Ekanathan - - PR gas/14423 - * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS. - * i386-init.h: Regenerated. - -2012-08-09 Nick Clifton - - * po/vi.po: Updated Vietnamese translation. - -2012-08-07 Roland McGrath - - * i386-dis.c (reg_table): Fill out REG_0F0D table with - AMD-reserved cases as "prefetch". - (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants. - (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise. - (reg_table): Use those under REG_0F18. - (mod_table): Add those cases as "nop/reserved". - -2012-08-07 Jan Beulich - - * i386-opc.tbl: Remove "FIXME" comments from SVME instructions. - -2012-08-06 Roland McGrath - - * i386-dis.c (print_insn): Print spaces between multiple excess - prefixes. Return actual number of excess prefixes consumed, - not always one. - - * i386-dis.c (OP_REG): Ignore REX_B for segment register cases. - -2012-08-06 Roland McGrath - Victor Khimenko - H.J. Lu - - * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG. - (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG. - (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG. - (OP_E_register): Likewise. - (OP_REG): For low 8 whole registers, treat REX_W like DFLAG. - -2012-08-02 Jan-Benedict Glaw - - * configure.in: Formatting. - * configure: Regenerate. - -2012-08-01 Alan Modra - - * h8300-dis.c: Fix printf arg warnings. - * i960-dis.c: Likewise. - * mips-dis.c: Likewise. - * pdp11-dis.c: Likewise. - * sh-dis.c: Likewise. - * v850-dis.c: Likewise. - * configure.in: Formatting. - * configure: Regenerate. - * rl78-decode.c: Regenerate. - * po/POTFILES.in: Regenerate. - -2012-07-31 Chao-Ying Fu - Catherine Moore - Maciej W. Rozycki - - * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. - (DSP_VOLA): Likewise. - (D32, D33): Likewise. - (micromips_opcodes): Add DSP ASE instructions. - * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases. - <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise. - -2012-07-31 Jan Beulich - - * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2 - instruction group. Mark as requiring AVX2. - * i386-tbl.h: Re-generate. - -2012-07-30 Nick Clifton - - * po/opcodes.pot: Updated template. - * po/es.po: Updated Spanish translation. - * po/fi.po: Updated Finnish translation. - -2012-07-27 Mike Frysinger - - * configure.in (BFD_VERSION): Run bfd/configure --version and - parse the output of that. - * configure: Regenerate. - -2012-07-25 James Lemke - - * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns. - -2012-07-24 Stephan McCamant - Dr David Alan Gilbert - - PR binutils/13135 - * arm-dis.c: Add necessary casts for printing integer values. - Use %s when printing string values. - * hppa-dis.c: Likewise. - * m68k-dis.c: Likewise. - * microblaze-dis.c: Likewise. - * mips-dis.c: Likewise. - * sparc-dis.c: Likewise. - -2012-07-19 Michael Zolotukhin - - PR binutils/14355 - * i386-dis.c (VEX_LEN_0FXOP_08_CC): New. - (VEX_LEN_0FXOP_08_CD): Likewise. - (VEX_LEN_0FXOP_08_CE): Likewise. - (VEX_LEN_0FXOP_08_CF): Likewise. - (VEX_LEN_0FXOP_08_EC): Likewise. - (VEX_LEN_0FXOP_08_ED): Likewise. - (VEX_LEN_0FXOP_08_EE): Likewise. - (VEX_LEN_0FXOP_08_EF): Likewise. - (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq, - vpcomub, vpcomuw, vpcomud, vpcomuq. - (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC, - VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF, - VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE, - VEX_LEN_0FXOP_08_EF. - -2012-07-16 Michael Zolotukhin - - * i386-dis.c (PREFIX_0F38F6): New. - (prefix_table): Add adcx, adox instructions. - (three_byte_table): Use PREFIX_0F38F6. - (mod_table): Add rdseed instruction. - * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW. - (cpu_flags): Likewise. - * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW. - (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw. - * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend - prefetchw. - * i386-tbl.h: Regenerate. - * i386-init.h: Likewise. - -2012-07-05 Thomas Schwinge - - * mips-dis.c: Remove gratuitous newline. - -2012-07-05 Sean Keys - - * xgate-dis.c: Removed an IF statement that will - always be false due to overlapping operand masks. - * xgate-opc.c: Corrected 'com' opcode entry and - fixed spacing. - -2012-07-02 Roland McGrath - - * i386-opc.tbl: Add RepPrefixOk to nop. - * i386-tbl.h: Regenerate. - -2012-06-28 Nick Clifton - - * po/vi.po: Updated Vietnamese translation. - -2012-06-22 Roland McGrath - - * i386-opc.tbl: Add RepPrefixOk to ret. - * i386-tbl.h: Regenerate. - - * i386-opc.h (RepPrefixOk): New enum constant. - (i386_opcode_modifier): New bitfield 'repprefixok'. - * i386-gen.c (opcode_modifiers): Add RepPrefixOk. - * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all - instructions that have IsString. - * i386-tbl.h: Regenerate. - -2012-06-11 Andreas Schwab - - * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx) - (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx) - (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls) - (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst) - (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep) - (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls) - (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x) - (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx) - (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0. - -2012-05-19 Alan Modra - - * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h. - (get_powerpc_dialect): Detect VLE sections from ELF sh_flags. - -2012-05-18 Alan Modra - - * ia64-opc.c: Remove #include "ansidecl.h". - * z8kgen.c: Include sysdep.h first. - - * arc-dis.c: Include sysdep.h first, remove some redundant includes. - * bfin-dis.c: Likewise. - * i860-dis.c: Likewise. - * ia64-dis.c: Likewise. - * ia64-gen.c: Likewise. - * m68hc11-dis.c: Likewise. - * mmix-dis.c: Likewise. - * msp430-dis.c: Likewise. - * or32-dis.c: Likewise. - * rl78-dis.c: Likewise. - * rx-dis.c: Likewise. - * tic4x-dis.c: Likewise. - * tilegx-opc.c: Likewise. - * tilepro-opc.c: Likewise. - * rx-decode.c: Regenerate. - -2012-05-17 James Lemke - - * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi. - -2012-05-17 James Lemke - - * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE. - -2012-05-17 Daniel Richard G. - Nick Clifton - - PR 14072 - * configure.in: Add check that sysdep.h has been included before - any system header files. * configure: Regenerate. - * config.in: Regenerate. - * sysdep.h: Generate an error if included before config.h. - * alpha-opc.c: Include sysdep.h before any other header file. - * alpha-dis.c: Likewise. - * avr-dis.c: Likewise. - * cgen-opc.c: Likewise. - * cr16-dis.c: Likewise. - * cris-dis.c: Likewise. - * crx-dis.c: Likewise. - * d10v-dis.c: Likewise. - * d10v-opc.c: Likewise. - * d30v-dis.c: Likewise. - * d30v-opc.c: Likewise. - * h8500-dis.c: Likewise. - * i370-dis.c: Likewise. - * i370-opc.c: Likewise. - * m10200-dis.c: Likewise. - * m10300-dis.c: Likewise. - * micromips-opc.c: Likewise. - * mips-opc.c: Likewise. - * mips61-opc.c: Likewise. - * moxie-dis.c: Likewise. - * or32-opc.c: Likewise. - * pj-dis.c: Likewise. - * ppc-dis.c: Likewise. - * ppc-opc.c: Likewise. - * s390-dis.c: Likewise. - * sh-dis.c: Likewise. - * sh64-dis.c: Likewise. - * sparc-dis.c: Likewise. - * sparc-opc.c: Likewise. - * spu-dis.c: Likewise. - * tic30-dis.c: Likewise. - * tic54x-dis.c: Likewise. - * tic80-dis.c: Likewise. - * tic80-opc.c: Likewise. - * tilegx-dis.c: Likewise. - * tilepro-dis.c: Likewise. - * v850-dis.c: Likewise. - * v850-opc.c: Likewise. - * vax-dis.c: Likewise. - * w65-dis.c: Likewise. - * xgate-dis.c: Likewise. - * xtensa-dis.c: Likewise. - * rl78-decode.opc: Likewise. - * rl78-decode.c: Regenerate. - * rx-decode.opc: Likewise. - * rx-decode.c: Regenerate. - -2012-05-17 Alan Modra - - * ppc_dis.c: Don't include elf/ppc.h. - -2012-05-16 Meador Inge - - * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg} - to PUSH/POP {reg}. - -2012-05-15 James Murray - Stephane Carrez - - * configure.in: Add S12X and XGATE co-processor support to m68hc11 - target. - * disassemble.c: Likewise. - * configure: Regenerate. - * m68hc11-dis.c: Make objdump output more consistent, use hex - instead of decimal and use 0x prefix for hex. - * m68hc11-opc.c: Add S12X and XGATE opcodes. - -2012-05-14 James Lemke - - * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle. - (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines. - (vle_opcd_indices): New array. - (lookup_vle): New function. - (disassemble_init_powerpc): Revise for second (VLE) opcode table. - (print_insn_powerpc): Likewise. - * ppc-opc.c: Likewise. - -2012-05-14 Catherine Moore - Maciej W. Rozycki - Rhonda Wittels - Nathan Froyd - - * ppc-opc.c (insert_arx, extract_arx): New functions. - (insert_ary, extract_ary): New functions. - (insert_li20, extract_li20): New functions. - (insert_rx, extract_rx): New functions. - (insert_ry, extract_ry): New functions. - (insert_sci8, extract_sci8): New functions. - (insert_sci8n, extract_sci8n): New functions. - (insert_sd4h, extract_sd4h): New functions. - (insert_sd4w, extract_sd4w): New functions. - (insert_vlesi, extract_vlesi): New functions. - (insert_vlensi, extract_vlensi): New functions. - (insert_vleui, extract_vleui): New functions. - (insert_vleil, extract_vleil): New functions. - (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT. - (BI16, BI32, BO32, B8): New. - (B15, B24, CRD32, CRS): New. - (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG. - (DB, IMM20, RD, Rx, ARX, RY, RZ): New. - (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New. - (SH6_MASK): Use PPC_OPSHIFT_INV. - (SI8, UI5, OIMM5, UI7, BO16): New. - (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New. - (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV. - (ALLOW8_SPRG): New. - (insert_sprg, extract_sprg): Check ALLOW8_SPRG. - (OPVUP, OPVUP_MASK OPVUP): New - (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New. - (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New. - (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New. - (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New. - (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New. - (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New. - (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New. - (SE_IM5, SE_IM5_MASK): New. - (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New. - (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New. - (BO32DNZ, BO32DZ): New. - (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE. - (PPCVLE): New. - (powerpc_opcodes): Add new VLE instructions. Update existing - instruction to include PPCVLE if supported. - * ppc-dis.c (ppc_opts): Add vle entry. - (get_powerpc_dialect): New function. - (powerpc_init_dialect): VLE support. - (print_insn_big_powerpc): Call get_powerpc_dialect. - (print_insn_little_powerpc): Likewise. - (operand_value_powerpc): Handle negative shift counts. - (print_insn_powerpc): Handle 2-byte instruction lengths. - -2012-05-11 Daniel Richard G. - - PR binutils/14028 - * configure.in: Invoke ACX_HEADER_STRING. - * configure: Regenerate. - * config.in: Regenerate. - * sysdep.h: If STRINGS_WITH_STRING is defined then include both - string.h and strings.h. - -2012-05-11 Nick Clifton - - PR binutils/14006 - * arm-dis.c (print_insn): Fix detection of instruction mode in - files containing multiple executable sections. - -2012-05-03 Sean Keys - - * Makefile.in, configure: regenerate - * disassemble.c (disassembler): Recognize ARCH_XGATE. - * xgate-dis.c (read_memory, print_insn, print_insn_xgate): - New functions. - * configure.in: Recognize xgate. - * xgate-dis.c, xgate-opc.c: New files for support of xgate - * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly - and opcode generation for xgate. - -2012-04-30 DJ Delorie - - * rx-decode.opc (MOV): Do not sign-extend immediates which are - already the maximum bit size. - * rx-decode.c: Regenerate. - -2012-04-27 David S. Miller - - * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'. - * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr. - - * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'. - * sparc-dis.c (v9a_asr_reg_names): Add 'pause'. - * sparc-opc.c (CBCOND): New define. - (CBCOND_XCC): Likewise. - (cbcond): New helper macro. - (sparc_opcodes): Add compare-and-branch instructions. +2013-01-07 Kaushik Phatak - * sparc-dis.c (print_insn_sparc): Handle ')'. - * sparc-opc.c (sparc_opcodes): Add crypto instructions. + * cr16-dis.c (make_instruction): Rename to cr16_make_instruction. + (match_opcode): Rename to cr16_match_opcode. - * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values - into new struct sparc_opcode 'hwcaps' field instead of 'flags'. +2013-01-04 Juergen Urban -2012-04-12 David S. Miller + * mips-dis.c: Add names for CP0 registers of r5900. + * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for + instructions sq and lq. + Add support for MIPS r5900 CPU. + Add support for 128 bit MMI (Multimedia Instructions). + Add support for EE instructions (Emotion Engine). + Disable unsupported floating point instructions (64 bit and + undefined compare operations). + Enable instructions of MIPS ISA IV which are supported by r5900. + Disable 64 bit co processor instructions. + Disable 64 bit multiplication and division instructions. + Disable instructions for co-processor 2 and 3, because these are + not supported (preparation for later VU0 support (Vector Unit)). + Disable cvt.w.s because this behaves like trunc.w.s and the + correct execution can't be ensured on r5900. + Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This + will confuse less developers and compilers. - * sparc-dis.c (X_DISP10): Define. - (print_insn_sparc): Handle '='. +2013-01-04 Yufeng Zhang -2012-04-01 Mike Frysinger + * aarch64-opc.c (aarch64_print_operand): Change to print + AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal + in comment. + * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag + from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and + OP_MOV_IMM_WIDE. - * bfin-dis.c (fmtconst): Replace decimal handling with a single - sprintf call and the '*' field width. +2013-01-04 Yufeng Zhang -2012-03-23 Maxim Kuvyrkov + * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, + PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. - * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP. +2013-01-02 H.J. Lu -2012-03-16 Alan Modra + * i386-gen.c (process_copyright): Update copyright year to 2013. - * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete. - (powerpc_opcd_indices): Bump array size. - (disassemble_init_powerpc): Set powerpc_opcd_indices entries - corresponding to unused opcodes to following entry. - (lookup_powerpc): New function, extracted and optimised from.. - (print_insn_powerpc): ..here. +2013-01-02 Kaushik Phatak -2012-03-15 Alan Modra - James Lemke + * cr16-dis.c (match_opcode,make_instruction): Remove static + declaration. + (dwordU,wordU): Moved typedefs to opcode/cr16.h + (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'. - * disassemble.c (disassemble_init_for_target): Handle ppc init. - * ppc-dis.c (private): New var. - (powerpc_init_dialect): Don't return calloc failure, instead use - private. - (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define. - (powerpc_opcd_indices): New array. - (disassemble_init_powerpc): New function. - (print_insn_big_powerpc): Don't init dialect here. - (print_insn_little_powerpc): Likewise. - (print_insn_powerpc): Start search using powerpc_opcd_indices. - -2012-03-10 Edmar Wienskoski - - * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". - * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. - (PPCVEC2, PPCTMR, E6500): New short names. - (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, - mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, - lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, - lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, - lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC - optional operands on sync instruction for E6500 target. - -2012-03-08 Andreas Krebbel - - * s390-opc.txt: Set instruction type of pku to SS_L2RDRD. - -2012-02-27 Alan Modra - - * mt-dis.c: Regenerate. - -2012-02-27 Alan Modra - - * v850-opc.c (extract_v8): Rearrange to make it obvious this - is the inverse of corresponding insert function. - (extract_d22, extract_u9, extract_r4): Likewise. - (extract_d9): Correct sign extension. - (extract_d16_15): Don't assume "long" is 32 bits, and don't - rely on implementation defined behaviour for shift right of - signed types. - (extract_d16_16, extract_d17_16, extract_i9): Likewise. - (extract_d23): Likewise, and correct mask. - -2012-02-27 Alan Modra - - * crx-dis.c (print_arg): Mask constant to 32 bits. - * crx-opc.c (cst4_map): Use int array. - -2012-02-27 Alan Modra - - * arc-dis.c (BITS): Don't use shifts to mask off bits. - (FIELDD): Sign extend with xor,sub. - -2012-02-25 Walter Lee - - * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS. - * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and - TILEPRO_OPC_LW_TLS_SN. - -2012-02-21 H.J. Lu - - * i386-opc.h (HLEPrefixNone): New. - (HLEPrefixLock): Likewise. - (HLEPrefixAny): Likewise. - (HLEPrefixRelease): Likewise. - -2012-02-08 H.J. Lu - - * i386-dis.c (HLE_Fixup1): New. - (HLE_Fixup2): Likewise. - (HLE_Fixup3): Likewise. - (Ebh1): Likewise. - (Evh1): Likewise. - (Ebh2): Likewise. - (Evh2): Likewise. - (Ebh3): Likewise. - (Evh3): Likewise. - (MOD_C6_REG_7): Likewise. - (MOD_C7_REG_7): Likewise. - (RM_C6_REG_7): Likewise. - (RM_C7_REG_7): Likewise. - (XACQUIRE_PREFIX): Likewise. - (XRELEASE_PREFIX): Likewise. - (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, - cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use - Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. - (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, - not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use - MOD_C6_REG_7 and MOD_C7_REG_7. - (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. - (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and - xtest. - (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. - (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. - - * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and - CPU_RTM_FLAGS. - (cpu_flags): Add CpuHLE and CpuRTM. - (opcode_modifiers): Add HLEPrefixOk. - - * i386-opc.h (CpuHLE): New. - (CpuRTM): Likewise. - (HLEPrefixOk): Likewise. - (i386_cpu_flags): Add cpuhle and cpurtm. - (i386_opcode_modifier): Add hleprefixok. - - * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to - add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, - sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory - operand. Add xacquire, xrelease, xabort, xbegin, xend and - xtest. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2012-01-24 DJ Delorie - - * rl78-decode.opc (rl78_decode_opcode): Add NOT1. - * rl78-decode.c: Regenerate. - -2012-01-17 James Murray - - PR binutils/10173 - * cr16-dis.c (print_arg): Test symtab_size not num_symbols. - -2012-01-17 Andreas Schwab - - * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx - register and move them after pmove with PSR/PCSR register. - -2012-01-13 H.J. Lu - - * i386-dis.c (mod_table): Add vmfunc. - - * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS. - (cpu_flags): CpuVMFUNC. - - * i386-opc.h (CpuVMFUNC): New. - (i386_cpu_flags): Add cpuvmfunc. +For older changes see ChangeLog-2012 + +Copyright (C) 2013 Free Software Foundation, Inc. - * i386-opc.tbl: Add vmfunc. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. -For older changes see ChangeLog-2011 - Local Variables: mode: change-log left-margin: 8