X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=c13838539e25e89321599902d1f21b61dcbd2495;hb=8282b7ad0dfaffce380cb668dc2a8ca473758760;hp=ca692484022cdb9fdf54caf0570d075e44c2b0b1;hpb=a79eaed6a5075ca062d6d8ff3d7a5ccce5d1908f;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ca69248402..c13838539e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,79 @@
+2018-07-19  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Fold AVX512BW templates into their respective
+	AVX512VL counterparts where possible, using Disp8ShiftVL and
+	CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+	IgnoreSize) as appropriate.
+	* i386-tbl.h: Re-generate.
+
+2018-07-19  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Fold AVX512CD templates into their respective
+	AVX512VL counterparts where possible, using Disp8ShiftVL and
+	CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+	IgnoreSize) as appropriate.
+	* i386-tbl.h: Re-generate.
+
+2018-07-19  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.h (DISP8_SHIFT_VL): New.
+	* i386-opc.tbl (Disp8ShiftVL):  Define.
+	(various): Fold AVX512VL templates into their respective
+	AVX512F counterparts where possible, using Disp8ShiftVL and
+	CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+	IgnoreSize) as appropriate.
+	* i386-tbl.h: Re-generate.
+
+2018-07-19  Jan Beulich  <jbeulich@suse.com>
+
+	* Makefile.am: Change dependencies and rule for
+	$(srcdir)/i386-init.h.
+	* Makefile.in: Re-generate.
+	* i386-gen.c (process_i386_opcodes): New local variable
+	"marker". Drop opening of input file. Recognize marker and line
+	number directives.
+	* i386-opc.tbl (OPCODE_I386_H): Define.
+	(i386-opc.h): Include it.
+	(None): Undefine.
+
+2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/23418
+	* i386-opc.h (Byte): Update comments.
+	(Word): Likewise.
+	(Dword): Likewise.
+	(Fword): Likewise.
+	(Qword): Likewise.
+	(Tbyte): Likewise.
+	(Xmmword): Likewise.
+	(Ymmword): Likewise.
+	(Zmmword): Likewise.
+	* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
+	vcvttps2uqq.
+	* i386-tbl.h: Regenerated.
+
+2018-07-12  Sudakshina Das  <sudi.das@arm.com>
+
+	* aarch64-tbl.h (aarch64_opcode_table): Add entry for
+	ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
+	* aarch64-asm-2.c: Regenerate.
+	* aarch64-dis-2.c: Regenerate.
+	* aarch64-opc-2.c: Regenerate.
+
+2018-07-12  Tamar Christina  <tamar.christina@arm.com>
+
+	PR binutils/23192
+	* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
+	mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
+	umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
+	sqdmulh, sqrdmulh): Use Em16.
+
+2018-07-11  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
+	csdb together with them.
+	(thumb32_opcodes): Likewise.
+
 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-opc.tbl (monitor, monitorx): Add 64-bit template