X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=cb239a5546dcbf754583997d88eb3a6823b0a36c;hb=c500c07496c29071b32f68e015b12dd7c7c969fc;hp=67548405b944f50d49c0813692b6054f3648dd92;hpb=09478dc331acb6e6819be2c9fda492f47a62c6e3;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 67548405b9..cb239a5546 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,4 +1,175 @@ start-sanitize-v850 +Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (D9_RELAX): Renamed from D9, all references + changed. + (v850_operands): Make sure D22 immediately follows D9_RELAX. + +end-sanitize-v850 +Fri Oct 25 12:12:53 1996 Ian Lance Taylor + + * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5. + +start-sanitize-v850 +Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w + and sst.w instructions. + + * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for + "bCC"instructions). + +end-sanitize-v850 +Thu Oct 24 17:21:20 1996 Ian Lance Taylor + + * mips-dis.c (_print_insn_mips): Use a tab between the instruction + and the arguments. + +Tue Oct 22 23:32:56 1996 Ian Lance Taylor + + * ppc-opc.c (PPCPWR2): Define. + (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating + it. + +Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode + field for movhu instruction. +start-sanitize-v850 + + * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, + cast value to "long" not "signed long" to keep hpux10 + compiler quiet. +end-sanitize-v850 + +Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field + for mov (abs16),DN. + + * mn10300-opc.c (FMT*): Remove definitions. + + * mn10300-opc.c (mn10300_opcodes): Fix destination register + for shift-by-register opcodes. + + * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM + into [AD][MN][01] for encoding the position of the register + in the opcode. + +Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, + "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". + +Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. + Fix various typos. Add "PAREN" operand. + (MEM, MEM2): Define. + (mn10300_opcodes): Surround all memory addresses with "PAREN" + operands. Fix several typos. + + * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's + changes. + +Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (FMT_XX): Renumber starting at one. + (mn10300_operands): Rough cut. Enough to parse "mov" instructions + at this time. + (mn10300_opcodes): Break opcode format out into its own field. + Update many operand fields to deal with signed vs unsigned + issues. Fix one or two typos in the "mov" instruction + opcode, mask and/or operand fields. + +Mon Oct 7 11:39:49 1996 Andreas Schwab + + * m68k-opc.c (plusha): Prefer encoding for m68040up, in case + m68851 wasn't reset. + +Thu Oct 3 17:17:02 1996 Ian Lance Taylor + + * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for + all opcodes. Very rough cut at operands for all opcodes. + + * mn10300-opc.c (mn10300_opcodes): Start fleshing out the + opcode table. + +Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c, mn10300-opc.c: New files. + * mn10200-dis.c, mn10300-dis.c: New files. + * mn10x00-opc.c, mn10x00-dis.c: Deleted. + * disassemble.c: Break mn10x00 support into 10200 and 10300 + support. + * configure.in: Likewise. + * configure: Rebuilt. + +Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. + +Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita + MN10x00 processors. + * disassemble (ARCH_mn10x00): Define. + (disassembler): Handle bfd_arch_mn10x00. + * configure.in: Recognize bfd_mn10x00_arch. + * configure: Rebuilt. + +Tue Oct 1 10:49:11 1996 Ian Lance Taylor + + * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses + accordingly. Don't declare functions using op_rtn. + +start-sanitize-v850 +Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com) + + * v850-dis.c (disassemble): Add memaddr argument. Re-arrange + params to be more standard. + * (disassemble): Print absolute addresses and symbolic names for + branch and jump targets. + * v850-opc.c (v850_operand): Add displacement flag to 9 and 22 + bit operands. + * (v850_opcodes): Add breakpoint insn. + +end-sanitize-v850 +Mon Sep 23 12:32:26 1996 Ian Lance Taylor + + * m68k-opc.c: Move the fmovemx data register cases before the + other cases, so that they get recognized before the data register + does gets treated as a degenerate register list. + +Tue Sep 17 12:06:51 1996 Ian Lance Taylor + + * mips-opc.c: Add a case for "div" and "divu" with two registers + and a destination of $0. + +Tue Sep 10 16:12:39 1996 Fred Fish + + * mips-dis.c (print_insn_arg): Add prototype. + (_print_insn_mips): Ditto. + +Mon Sep 9 14:26:26 1996 Ian Lance Taylor + + * mips-dis.c (print_insn_arg): Print condition code registers as + $fccN. + +Tue Sep 3 12:09:46 1996 Doug Evans + + * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. + +start-sanitize-v850 +Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com) + + * v850-dis.c (disassemble): Make static. Provide prototype. + +Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d9, insert_d22): Fix boundary case + in range checks. + Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com) * v850-dis.c (disassemble): Handle insertion of ',', '[' and