X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=ce56ec023129cf3ba594d3b532283b79328edd16;hb=65fca0597f3a5f76f6d7d79bc3a922c160254e0a;hp=67bc754be56dcb1bef48ba6593c2ff7339fcbfc6;hpb=60391a255b720e37ab1efbb7e83bf7dfa270a0fe;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 67bc754be5..a53d646e42 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,1471 +1,452 @@ -2019-09-09 Phil Blundell +2020-02-14 Jan Beulich - binutils 2.33 branch created. - -2019-09-03 Nick Clifton - - PR 24961 - * tic30-dis.c (get_indirect_operand): Check for bufcnt being - greater than zero before indexing via (bufcnt -1). - -2019-09-03 Nick Clifton - - PR 24958 - * mmix-dis.c (MAX_REG_NAME_LEN): Define. - (MAX_SPEC_REG_NAME_LEN): Define. - (struct mmix_dis_info): Use defined constants for array lengths. - (get_reg_name): New function. - (get_sprec_reg_name): New function. - (print_insn_mmix): Use new functions. - -2019-08-27 Srinath Parvathaneni - - * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. - (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. - (print_insn_mve): Add condition to check Qm==Qn of VORR instruction. - -2019-08-22 Kyrylo Tkachov - - * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, - tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. - (aarch64_sys_reg_supported_p): Update checks for the above. - -2019-08-12 Srinath Parvathaneni - - * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for - cases MVE_SQRSHRL and MVE_UQRSHLL. - (print_insn_mve): Add case for specifier 'k' to check - specific bit of the instruction. - -2019-08-07 Phillipe Antoine - - PR 24854 - * arc-dis.c (arc_insn_length): Return 0 rather than aborting when - encountering an unknown machine type. - (print_insn_arc): Handle arc_insn_length returning 0. In error - cases return -1 rather than calling abort. - -2019-08-07 Jan Beulich - - * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms. - (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by - IgnoreSize. + PR gas/25438 + * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as + destination for Cpu64-only variant. + (movzx): Fold patterns. * i386-tbl.h: Re-generate. -2019-08-05 Barnaby Wilks - - * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH - instructions. - -2019-07-30 Mel Chen - - * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, - fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. +2020-02-13 Jan Beulich - * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, - fscsr. - -2019-07-24 Claudiu Zissulescu - - * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, - and MPY class instructions. - (parse_option): Add nps400 option. - (print_arc_disassembler_options): Add nps400 info. - -2019-07-24 Claudiu Zissulescu - - * arc-ext-tbl.h (bspeek): Remove it, added to main table. - (bspop): Likewise. - (modapp): Likewise. - * arc-opc.c (RAD_CHK): Add. - * arc-tbl.h: Regenerate. - -2019-07-23 Kyrylo Tkachov - - * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry. - (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding. + * i386-gen.c (cpu_flag_init): Move CpuSSE4a from + CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add + CPU_ANY_SSE4_FLAGS entry. + * i386-init.h: Re-generate. -2019-07-22 Barnaby Wilks +2020-02-12 Jan Beulich - * arm-dis.c (is_mve_unpredictable): Stop marking some MVE - instructions as UNPREDICTABLE. + * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form + with Unspecified, making the present one AT&T syntax only. + * i386-tbl.h: Re-generate. -2019-07-19 Jose E. Marchesi +2020-02-12 Jan Beulich - * bpf-desc.c: Regenerated. + * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. + * i386-tbl.h: Re-generate. -2019-07-17 Jan Beulich +2020-02-12 Jan Beulich - * i386-gen.c (static_assert): Define. - (main): Use it. - * i386-opc.h (Opcode_Modifier_Max): Rename to ... - (Opcode_Modifier_Num): ... this. - (Mem): Delete. + PR gas/24546 + * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. + * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into + Amd64 and Intel64 templates. + (call, jmp): Likewise for far indirect variants. Dro + Unspecified. + * i386-tbl.h: Re-generate. -2019-07-16 Jan Beulich +2020-02-11 Jan Beulich - * i386-gen.c (operand_types): Move RegMem ... - (opcode_modifiers): ... here. - * i386-opc.h (RegMem): Move to opcode modifer enum. - (union i386_operand_type): Move regmem field ... - (struct i386_opcode_modifier): ... here. - * i386-opc.tbl (RegMem): Define. - (mov, movq): Move RegMem on segment, control, debug, and test - register flavors. - (pextrb): Move RegMem on register only flavors. Add IgnoreSize - to non-SSE2AVX flavor. - (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw): - Move RegMem on register only flavors. Drop IgnoreSize from - legacy encoding flavors. - (movss, movsd, vmovss, vmovsd): Drop RegMem from register only - flavors. - (vpinsrb, vpinsrw): Drop IgnoreSize where still present on - register only flavors. - (vmovd): Move RegMem and drop IgnoreSize on register only - flavor. Change opcode and operand order to store form. - * opcodes/i386-init.h, i386-tbl.h: Re-generate. + * i386-gen.c (opcode_modifiers): Remove ShortForm entry. + * i386-opc.h (ShortForm): Delete. + (struct i386_opcode_modifier): Remove shortform field. + * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, + fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, + fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, + ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): + Drop ShortForm. + * i386-tbl.h: Re-generate. -2019-07-16 Jan Beulich +2020-02-11 Jan Beulich - * i386-gen.c (operand_type_init, operand_types): Replace SReg - entries. - * i386-opc.h (SReg2, SReg3): Replace by ... - (SReg): ... this. - (union i386_operand_type): Replace sreg fields. - * i386-opc.tbl (mov, ): Use SReg. - (push, pop): Likewies. Drop i386 and x86-64 specific segment - register flavors. - * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg. - * opcodes/i386-init.h, i386-tbl.h: Re-generate. + * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, + fucompi): Drop ShortForm from operand-less templates. + * i386-tbl.h: Re-generate. -2019-07-15 Jose E. Marchesi +2020-02-11 Alan Modra + + * cgen-ibld.in (extract_normal): Set *valuep on all return paths. + * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, + * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, + * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, + * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. + +2020-02-10 Matthew Malcomson + + * arm-dis.c (print_insn_cde): Define 'V' parse character. + (cde_opcodes): Add VCX* instructions. + +2020-02-10 Stam Markianos-Wright + Matthew Malcomson + + * arm-dis.c (struct cdeopcode32): New. + (CDE_OPCODE): New macro. + (cde_opcodes): New disassembly table. + (regnames): New option to table. + (cde_coprocs): New global variable. + (print_insn_cde): New + (print_insn_thumb32): Use print_insn_cde. + (parse_arm_disassembler_options): Parse coprocN args. + +2020-02-10 H.J. Lu + + PR gas/25516 + * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 + with ISA64. + * i386-opc.h (AMD64): Removed. + (Intel64): Likewose. + (AMD64): New. + (INTEL64): Likewise. + (INTEL64ONLY): Likewise. + (i386_opcode_modifier): Replace amd64 and intel64 with isa64. + * i386-opc.tbl (Amd64): New. + (Intel64): Likewise. + (Intel64Only): Likewise. + Replace AMD64 with Amd64. Update sysenter/sysenter with + Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. + * i386-tbl.h: Regenerated. - * bpf-desc.c: Regenerate. - * bpf-opc.c: Likewise. - * bpf-opc.h: Likewise. +2020-02-07 Sergey Belyashov -2019-07-14 Jose E. Marchesi + PR 25469 + * z80-dis.c: Add support for GBZ80 opcodes. - * bpf-desc.c: Regenerate. - * bpf-opc.c: Likewise. +2020-02-04 Alan Modra -2019-07-10 Hans-Peter Nilsson + * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. - * arm-dis.c (print_insn_coprocessor): Rename index to - index_operand. +2020-02-03 Alan Modra -2019-07-05 Kito Cheng + * m32c-ibld.c: Regenerate. - * riscv-opc.c (riscv_insn_types): Add r4 type. +2020-02-01 Alan Modra - * riscv-opc.c (riscv_insn_types): Add b and j type. + * frv-ibld.c: Regenerate. - * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect - format for sb type and correct s type. +2020-01-31 Jan Beulich -2019-07-02 Richard Sandiford + * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. + (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. + (OP_E_memory): Replace xmm_mdq_mode case label by + vex_scalar_w_dq_mode one. + * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. - * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the - SVE FMOV alias of FCPY. +2020-01-31 Jan Beulich -2019-07-02 Richard Sandiford + * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. + (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, + vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. + (intel_operand_size): Drop vex_w_dq_mode case label. - * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags - to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries. +2020-01-31 Richard Sandiford -2019-07-02 Richard Sandiford + * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. + Remove C_SCAN_MOVPRFX for SVE bfcvtnt. - * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the - registers in an instruction prefixed by MOVPRFX. +2020-01-30 Alan Modra -2019-07-01 Matthew Malcomson + * m32c-ibld.c: Regenerate. - * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new - sve_size_13 icode to account for variant behaviour of - pmull{t,b}. - * aarch64-dis-2.c: Regenerate. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new - sve_size_13 icode to account for variant behaviour of - pmull{t,b}. - * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. - (OP_SVE_VVV_Q_D): Add new qualifier. - (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. - (struct aarch64_opcode): Split pmull{t,b} into those requiring - AES and those not. - -2019-07-01 Jan Beulich - - * opcodes/i386-gen.c (operand_type_init): Remove - OPERAND_TYPE_VEC_IMM4 entry. - (operand_types): Remove Vec_Imm4. - * opcodes/i386-opc.h (Vec_Imm4): Delete. - (union i386_operand_type): Remove vec_imm4. - * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4. - * opcodes/i386-init.h, i386-tbl.h: Re-generate. - -2019-07-01 Jan Beulich - - * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall, - vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs, - rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun, - vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb, - xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac, - monitorx, mwaitx): Drop ImmExt from operand-less forms. - * i386-tbl.h: Re-generate. +2020-01-30 Jose E. Marchesi -2019-07-01 Jan Beulich + * bpf-opc.c: Regenerate. - * i386-opc.tbl (and, or): Add Optimize to forms allowing two - register operands. - * i386-tbl.h: Re-generate. +2020-01-30 Jan Beulich -2019-07-01 Jan Beulich - - * i386-opc.tbl (C): New. - (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw, - pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw, - por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss, - cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw, - pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd, - cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd, - cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd, - vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps, - vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd, - vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd, - vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd, - vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd, - vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd, - vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd, - vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss, - vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss, - vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps, - vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps, - vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps, - vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps, - vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss, - vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw, - vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand, - vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd, - vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw, - vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded - flavors. + * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. + (dis386): Use them to replace C2/C3 table entries. + (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. + * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 + ones. Use Size64 instead of DefaultSize on Intel64 ones. * i386-tbl.h: Re-generate. -2019-07-01 Jan Beulich +2020-01-30 Jan Beulich - * i386-opc.tbl (and, or): Add Optimize to forms allowing two - register operands. + * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword + forms. + (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop + DefaultSize. * i386-tbl.h: Re-generate. -2019-07-01 Jan Beulich +2020-01-30 Alan Modra - * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq. - * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq, - vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors. - * i386-tbl.h: Re-generate. + * tic4x-dis.c (tic4x_dp): Make unsigned. -2019-07-01 Jan Beulich +2020-01-27 H.J. Lu + Jan Beulich - * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove - Disp8MemShift from register only templates. - * i386-tbl.h: Re-generate. - -2019-07-01 Jan Beulich - - * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1, - MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, - MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0, - EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, - EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0, - EVEX_W_0F11_P_3_M_1): Delete. - (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1, - EVEX_W_0F11_P_3): New. - * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1, - MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and - MOD_EVEX_0F11_PREFIX_3 table entries. - * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and - PREFIX_EVEX_0F11 table entries. - * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1}, - EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and - EVEX_W_0F11_P_3_M_{0,1} table entries. - -2019-07-01 Jan Beulich - - * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex): - Delete. - -2019-06-27 H.J. Lu - - PR binutils/24719 - * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, - EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, - EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, - EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, - EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, - EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and - EVEX_LEN_0F38C7_R_6_P_2_W_1. - * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, - PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and - PREFIX_EVEX_0F38C6_REG_6 entries. - * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, - EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and - EVEX_W_0F38C7_R_6_P_2 entries. - * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, - EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, - EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, - EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, - EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, - EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and - EVEX_LEN_0F38C7_R_6_P_2_W_1 enums. - -2019-06-27 Jan Beulich - - * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3, - VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1, - VEX_LEN_0F2D_P_3): Delete. - (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si, - vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ... - (prefix_table): ... here. - -2019-06-27 Jan Beulich - - * i386-dis.c (Iq): Delete. - (Id): New. - (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for - TBM insns. - (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for - vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si. - (OP_E_memory): Also honor needindex when deciding whether an - address size prefix needs printing. - (OP_I): Remove handling of q_mode. Add handling of d_mode. - -2019-06-26 Jim Wilson - - PR binutils/24739 - * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code. - Set info->display_endian to info->endian_code. - -2019-06-25 Jan Beulich - - * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG - entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and - OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and - OPERAND_TYPE_ACC64 entries. - * i386-init.h: Re-generate. - -2019-06-25 Jan Beulich - - * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1): - Delete. - (intel_operand_size, OP_E_register, OP_E_memory): Drop handling - of dqa_mode. - * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf - entries here. - * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1 - entries. Use Edq for vcvtsi2sd and vcvtusi2sd. + PR binutils/25445 + * i386-dis.c (MOVSXD_Fixup): New function. + (movsxd_mode): New enum. + (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. + (intel_operand_size): Handle movsxd_mode. + (OP_E_register): Likewise. + (OP_G): Likewise. + * i386-opc.tbl: Remove Rex64 and allow 32-bit destination + register on movsxd. Add movsxd with 16-bit destination register + for AMD64 and Intel64 ISAs. + * i386-tbl.h: Regenerated. -2019-06-25 Jan Beulich +2020-01-27 Tamar Christina - * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local - variables. + PR 25403 + * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. + * aarch64-asm-2.c: Regenerate + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. -2019-06-25 Jan Beulich +2020-01-21 Jan Beulich - * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd. - Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and - movnti. - * i386-opc.tbl (movnti): Add IgnoreSize. + * i386-opc.tbl (sysret): Drop DefaultSize. * i386-tbl.h: Re-generate. -2019-06-25 Jan Beulich +2020-01-21 Jan Beulich - * i386-opc.tbl (and): Mark Imm8S form for optimization. + * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and + Dword. + (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. * i386-tbl.h: Re-generate. -2019-06-21 H.J. Lu - - * i386-dis-evex.h: Break into ... - * i386-dis-evex-len.h: New file. - * i386-dis-evex-mod.h: Likewise. - * i386-dis-evex-prefix.h: Likewise. - * i386-dis-evex-reg.h: Likewise. - * i386-dis-evex-w.h: Likewise. - * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, - i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and - i386-dis-evex-mod.h. - -2019-06-19 H.J. Lu - - PR binutils/24700 - * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, - EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and - EVEX_W_0F385B_P_2. - (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, - EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, - EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, - EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, - EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and - EVEX_LEN_0F385B_P_2_W_1. - * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. - (EVEX_LEN_0F3819_P_2_W_1): Likewise. - (EVEX_LEN_0F381A_P_2_W_0): Likewise. - (EVEX_LEN_0F381A_P_2_W_1): Likewise. - (EVEX_LEN_0F381B_P_2_W_0): Likewise. - (EVEX_LEN_0F381B_P_2_W_1): Likewise. - (EVEX_LEN_0F385A_P_2_W_0): Likewise. - (EVEX_LEN_0F385A_P_2_W_1): Likewise. - (EVEX_LEN_0F385B_P_2_W_0): Likewise. - (EVEX_LEN_0F385B_P_2_W_1): Likewise. - -2019-06-17 H.J. Lu - - PR binutils/24691 - * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, - EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, - EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. - (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, - EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, - EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, - EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, - EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, - EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and - EVEX_LEN_0F3A43_P_2_W_1. - * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. - (EVEX_LEN_0F3A23_P_2_W_1): Likewise. - (EVEX_LEN_0F3A38_P_2_W_0): Likewise. - (EVEX_LEN_0F3A38_P_2_W_1): Likewise. - (EVEX_LEN_0F3A39_P_2_W_0): Likewise. - (EVEX_LEN_0F3A39_P_2_W_1): Likewise. - (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. - (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. - (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. - (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. - (EVEX_LEN_0F3A43_P_2_W_0): Likewise. - (EVEX_LEN_0F3A43_P_2_W_1): Likewise. - -2019-06-14 Nick Clifton - - * po/fr.po; Updated French translation. - -2019-06-13 Stafford Horne - - * or1k-asm.c: Regenerated. - * or1k-desc.c: Regenerated. - * or1k-desc.h: Regenerated. - * or1k-dis.c: Regenerated. - * or1k-ibld.c: Regenerated. - * or1k-opc.c: Regenerated. - * or1k-opc.h: Regenerated. - * or1k-opinst.c: Regenerated. - -2019-06-12 Peter Bergner - - * ppc-opc.c (powerpc_opcodes) : Delete mnemonic. - -2019-06-05 H.J. Lu - - PR binutils/24633 - * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, - EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. - (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, - EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, - EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, - EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, - EVEX_LEN_0F3A1B_P_2_W_1. - * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. - (EVEX_LEN_0F3A18_P_2_W_1): Likewise. - (EVEX_LEN_0F3A19_P_2_W_0): Likewise. - (EVEX_LEN_0F3A19_P_2_W_1): Likewise. - (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. - (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. - (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. - (EVEX_LEN_0F3A1B_P_2_W_1): Likewise. - -2019-06-04 H.J. Lu - - PR binutils/24626 - * i386-dis.c (print_insn): Check for unused VEX.vvvv and - EVEX.vvvv when disassembling VEX and EVEX instructions. - (OP_VEX): Set vex.register_specifier to 0 after readding - vex.register_specifier. - (OP_Vex_2src_1): Likewise. - (OP_Vex_2src_2): Likewise. - (OP_LWP_E): Likewise. - (OP_EX_Vex): Don't check vex.register_specifier. - (OP_XMM_Vex): Likewise. - -2019-06-04 Igor Tsimbalist - Lili Cui - - * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. - * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT - instructions. - * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, - CPU_ANY_AVX512_VP2INTERSECT_FLAGS. - (cpu_flags): Add CpuAVX512_VP2INTERSECT. - * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. - (i386_cpu_flags): Add cpuavx512_vp2intersect. - * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2019-06-04 Xuepeng Guo - Lili Cui - - * doc/c-i386.texi: Document enqcmd. - * testsuite/gas/i386/enqcmd-intel.d: New file. - * testsuite/gas/i386/enqcmd-inval.l: Likewise. - * testsuite/gas/i386/enqcmd-inval.s: Likewise. - * testsuite/gas/i386/enqcmd.d: Likewise. - * testsuite/gas/i386/enqcmd.s: Likewise. - * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. - * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. - * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. - * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. - * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. - * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, - enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, - and x86-64-enqcmd. - -2019-06-04 Alan Hayward - - * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis. - -2019-06-03 Alan Modra - - * ppc-dis.c (prefix_opcd_indices): Correct size. - -2019-05-28 H.J. Lu - - PR gas/24625 - * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with - Disp8ShiftVL. - * i386-tbl.h: Regenerated. +2020-01-20 Nick Clifton + + * po/de.po: Updated German translation. + * po/pt_BR.po: Updated Brazilian Portuguese translation. + * po/uk.po: Updated Ukranian translation. -2019-05-24 Alan Modra - - * po/POTFILES.in: Regenerate. - -2019-05-24 Peter Bergner - Alan Modra - - * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), - (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. - (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. - (powerpc_operands ): Define and add entries. - (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. - (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, - pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, - plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. - -2019-05-24 Peter Bergner - Alan Modra - - * ppc-dis.c (ppc_opts): Add "future" entry. - (PREFIX_OPCD_SEGS): Define. - (prefix_opcd_indices): New array. - (disassemble_init_powerpc): Initialize prefix_opcd_indices. - (lookup_prefix): New function. - (print_insn_powerpc): Handle 64-bit prefix instructions. - * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), - (PMRR, POWERXX): Define. - (prefix_opcodes): New instruction table. - (prefix_num_opcodes): New constant. - -2019-05-23 Jose E. Marchesi - - * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch. - * configure: Regenerated. - * Makefile.am: Add rules for the files generated from cpu/bpf.cpu - and cpu/bpf.opc. - (HFILES): Add bpf-desc.h and bpf-opc.h. - (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c, - bpf-ibld.c and bpf-opc.c. - (BPF_DEPS): Define. - * Makefile.in: Regenerated. - * disassemble.c (ARCH_bpf): Define. - (disassembler): Add case for bfd_arch_bpf. - (disassemble_init_for_target): Likewise. - (enum epbf_isa_attr): Define. - * disassemble.h: extern print_insn_bpf. - * bpf-asm.c: Generated. - * bpf-opc.h: Likewise. - * bpf-opc.c: Likewise. - * bpf-ibld.c: Likewise. - * bpf-dis.c: Likewise. - * bpf-desc.h: Likewise. - * bpf-desc.c: Likewise. - -2019-05-21 Sudakshina Das - - * arm-dis.c (coprocessor_opcodes): New instructions for VMRS - and VMSR with the new operands. - -2019-05-21 Sudakshina Das - - * arm-dis.c (enum mve_instructions): New enum - for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv - and cneg. - (mve_opcodes): New instructions as above. - (is_mve_encoding_conflict): Add cases for csinc, csinv, - csneg and csel. - (print_insn_mve): Accept new %c and %C. - -2019-05-21 Sudakshina Das - - * arm-dis.c (emun mve_instructions): Updated for new instructions. - (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, - sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, - uqshl, urshrl and urshr. - (is_mve_okay_in_it): Add new instructions to TRUE list. - (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. - (print_insn_mve): Updated to accept new %j, - %m and %n patterns. - -2019-05-21 Faraz Shahbazker - - * mips-opc.c (mips_builtin_opcodes): Change source register - constraint for DAUI. - -2019-05-20 Nick Clifton - - * po/fr.po: Updated French translation. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (thumb32_opcodes): Add new instructions. - (enum mve_instructions): Likewise. - (enum mve_undefined): Add new reasons. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_undefined): Likewise. - (print_mve_size): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (thumb32_opcodes): Add new instructions. - (enum mve_instructions): Likewise. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (thumb32_opcodes): Add new instructions. - (enum mve_instructions): Likewise. - (is_mve_encoding_conflict): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (thumb32_opcodes): Add new instructions. - (enum mve_instructions): Likewise. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (thumb32_opcodes): Add new instructions. - (enum mve_instructions): Likewise. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (thumb32_opcodes): Add new instructions. - (print_insn_thumb32): Handle new instructions. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_undefined): Add new reasons. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_undefined): Likewise. - (print_mve_size): Likewise. - (print_mve_shift_n): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_unpredictable): Likewise. - (print_mve_rotate): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_undefined): Add new reasons. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_undefined): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_unpredictable): Add new reasons. - (enum mve_undefined): Likewise. - (is_mve_okay_in_it): Handle new isntructions. - (is_mve_encoding_conflict): Likewise. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_vmov_index): Likewise. - (print_simd_imm8): Likewise. - (print_mve_undefined): Likewise. - (print_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_unpredictable): Add new reasons. - (enum mve_undefined): Likewise. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_undefined): Likewise. - (print_mve_unpredictable): Likewise. - (print_mve_rounding_mode): Likewise. - (print_mve_vcvt_size): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_unpredictable): Add new reasons. - (enum mve_undefined): Likewise. - (is_mve_undefined): Handle new instructions. - (is_mve_unpredictable): Likewise. - (print_mve_undefined): Likewise. - (print_mve_unpredictable): Likewise. - (print_mve_size): Likewise. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_undefined): Add new reasons. - (insns): Add new instructions. - (is_mve_encoding_conflict): - (print_mve_vld_str_addr): New print function. - (is_mve_undefined): Handle new instructions. - (is_mve_unpredictable): Likewise. - (print_mve_undefined): Likewise. - (print_mve_size): Likewise. - (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. - (print_insn_mve): Handle new operands. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_unpredictable): Add new reasons. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_unpredictable): Likewise. - (mve_opcodes): Add new instructions. - (print_mve_unpredictable): Handle new reasons. - (print_mve_register_blocks): New print function. - (print_mve_size): Handle new instructions. - (print_insn_mve): Likewise. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_unpredictable): Add new reasons. - (enum mve_undefined): Likewise. - (is_mve_encoding_conflict): Handle new instructions. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (coprocessor_opcodes): Move NEON VDUP from here... - (neon_opcodes): ... to here. - (mve_opcodes): Add new instructions. - (print_mve_undefined): Handle new reasons. - (print_mve_unpredictable): Likewise. - (print_mve_size): Handle new instructions. - (print_insn_neon): Handle vdup. - (print_insn_mve): Handle new operands. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): Add new instructions. - (enum mve_unpredictable): Add new values. - (mve_opcodes): Add new instructions. - (vec_condnames): New array with vector conditions. - (mve_predicatenames): New array with predicate suffixes. - (mve_vec_sizename): New array with vector sizes. - (enum vpt_pred_state): New enum with vector predication states. - (struct vpt_block): New struct type for vpt blocks. - (vpt_block_state): Global struct to keep track of state. - (mve_extract_pred_mask): New helper function. - (num_instructions_vpt_block): Likewise. - (mark_outside_vpt_block): Likewise. - (mark_inside_vpt_block): Likewise. - (invert_next_predicate_state): Likewise. - (update_next_predicate_state): Likewise. - (update_vpt_block_state): Likewise. - (is_vpt_instruction): Likewise. - (is_mve_encoding_conflict): Add entries for new instructions. - (is_mve_unpredictable): Likewise. - (print_mve_unpredictable): Handle new cases. - (print_instruction_predicate): Likewise. - (print_mve_size): New function. - (print_vec_condition): New function. - (print_insn_mve): Handle vpt blocks and new print operands. - -2019-05-16 Andre Vieira - - * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors - 8, 14 and 15 for Armv8.1-M Mainline. - -2019-05-16 Andre Vieira - Michael Collison - - * arm-dis.c (enum mve_instructions): New enum. - (enum mve_unpredictable): Likewise. - (enum mve_undefined): Likewise. - (struct mopcode32): New struct. - (is_mve_okay_in_it): New function. - (is_mve_architecture): Likewise. - (arm_decode_field): Likewise. - (arm_decode_field_multiple): Likewise. - (is_mve_encoding_conflict): Likewise. - (is_mve_undefined): Likewise. - (is_mve_unpredictable): Likewise. - (print_mve_undefined): Likewise. - (print_mve_unpredictable): Likewise. - (print_insn_coprocessor_1): Use arm_decode_field_multiple. - (print_insn_mve): New function. - (print_insn_thumb32): Handle MVE architecture. - (select_arm_features): Force thumb for Armv8.1-m Mainline. - -2019-05-10 Nick Clifton - - PR 24538 - * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the - end of the table prematurely. - -2019-05-10 Faraz Shahbazker - - * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB - macros for R6. - -2019-05-11 Alan Modra - - * ppc-dis.c (print_insn_powerpc) Don't skip optional operands - when -Mraw is in effect. - -2019-05-09 Matthew Malcomson - - * aarch64-dis-2.c: Regenerate. - * aarch64-tbl.h (OP_SVE_BBU): New variant set. - (OP_SVE_BBB): New variant set. - (OP_SVE_DDDD): New variant set. - (OP_SVE_HHH): New variant set. - (OP_SVE_HHHU): New variant set. - (OP_SVE_SSS): New variant set. - (OP_SVE_SSSU): New variant set. - (OP_SVE_SHH): New variant set. - (OP_SVE_SBBU): New variant set. - (OP_SVE_DSS): New variant set. - (OP_SVE_DHHU): New variant set. - (OP_SVE_VMV_HSD_BHS): New variant set. - (OP_SVE_VVU_HSD_BHS): New variant set. - (OP_SVE_VVVU_SD_BH): New variant set. - (OP_SVE_VVVU_BHSD): New variant set. - (OP_SVE_VVV_QHD_DBS): New variant set. - (OP_SVE_VVV_HSD_BHS): New variant set. - (OP_SVE_VVV_HSD_BHS2): New variant set. - (OP_SVE_VVV_BHS_HSD): New variant set. - (OP_SVE_VV_BHS_HSD): New variant set. - (OP_SVE_VVV_SD): New variant set. - (OP_SVE_VVU_BHS_HSD): New variant set. - (OP_SVE_VZVV_SD): New variant set. - (OP_SVE_VZVV_BH): New variant set. - (OP_SVE_VZV_SD): New variant set. - (aarch64_opcode_table): Add sve2 instructions. - -2019-05-09 Matthew Malcomson - - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking - for SVE_SHLIMM_UNPRED_22. - (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. - * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 - operand. - -2019-05-09 Matthew Malcomson - - * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle - sve_size_tsz_bhs iclass encode. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle - sve_size_tsz_bhs iclass decode. - -2019-05-09 Matthew Malcomson - - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking - for SVE_Zm4_11_INDEX. - (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. - (fields): Handle SVE_i2h field. - * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. - * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. - -2019-05-09 Matthew Malcomson - - * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle - sve_shift_tsz_bhsd iclass encode. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle - sve_shift_tsz_bhsd iclass decode. - -2019-05-09 Matthew Malcomson - - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - * aarch64-asm.c (aarch64_ins_sve_shrimm): - (aarch64_encode_variant_using_iclass): Handle - sve_shift_tsz_hsd iclass encode. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle - sve_shift_tsz_hsd iclass decode. - * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking - for SVE_SHRIMM_UNPRED_22. - (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. - * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 - operand. - -2019-05-09 Matthew Malcomson - - * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle - sve_size_013 iclass encode. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle - sve_size_013 iclass decode. - -2019-05-09 Matthew Malcomson - - * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle - sve_size_bh iclass encode. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle - sve_size_bh iclass decode. - -2019-05-09 Matthew Malcomson - - * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle - sve_size_sd2 iclass encode. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle - sve_size_sd2 iclass decode. - * aarch64-opc.c (fields): Handle SVE_sz2 field. - * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. - -2019-05-09 Matthew Malcomson - - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking - for SVE_ADDR_ZX. - (aarch64_print_operand): Add printing for SVE_ADDR_ZX. - * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. - -2019-05-09 Matthew Malcomson - - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking - for SVE_Zm3_11_INDEX. - (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. - (fields): Handle SVE_i3l and SVE_i3h2 fields. - * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 - fields. - * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. - -2019-05-09 Matthew Malcomson - - * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle - sve_size_hsd2 iclass encode. - * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle - sve_size_hsd2 iclass decode. - * aarch64-opc.c (fields): Handle SVE_size field. - * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. - -2019-05-09 Matthew Malcomson - - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking - for SVE_IMM_ROT3. - (aarch64_print_operand): Add printing for SVE_IMM_ROT3. - (fields): Handle SVE_rot3 field. - * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. - * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. - -2019-05-09 Matthew Malcomson - - * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 - instructions. +2020-01-20 Alan Modra -2019-05-09 Matthew Malcomson + * hppa-dis.c (fput_const): Remove useless cast. - * aarch64-tbl.h - (aarch64_feature_sve2, aarch64_feature_sve2aes, - aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, - aarch64_feature_sve2bitperm): New feature sets. - (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros - for feature set addresses. - (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, - SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. +2020-01-20 Alan Modra -2019-05-06 Andrew Bennett - Faraz Shahbazker + * arm-dis.c (print_insn_arm): Wrap 'T' value. - * mips-dis.c (mips_calculate_combination_ases): Add ISA - argument and set ASE_EVA_R6 appropriately. - (set_default_mips_dis_options): Pass ISA to above. - (parse_mips_dis_option): Likewise. - * mips-opc.c (EVAR6): New macro. - (mips_builtin_opcodes): Add llwpe, scwpe. +2020-01-18 Nick Clifton -2019-05-01 Sudakshina Das + * configure: Regenerate. + * po/opcodes.pot: Regenerate. - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - * aarch64-opc.c (operand_general_constraint_met_p): Add case for - AARCH64_OPND_TME_UIMM16. - (aarch64_print_operand): Likewise. - * aarch64-tbl.h (QL_IMM_NIL): New. - (TME): New. - (_TME_INSN): New. - (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. +2020-01-18 Nick Clifton -2019-04-29 John Darrington + Binutils 2.34 branch created. - * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. +2020-01-17 Christian Biesinger -2019-04-26 Andrew Bennett - Faraz Shahbazker + * opintl.h: Fix spelling error (seperate). - * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. +2020-01-17 H.J. Lu -2019-04-24 John Darrington + * i386-opc.tbl: Add {vex} pseudo prefix. + * i386-tbl.h: Regenerated. - * s12z-opc.h: Add extern "C" bracketing to help - users who wish to use this interface in c++ code. +2020-01-16 Andre Vieira -2019-04-24 John Darrington + PR 25376 + * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. + (neon_opcodes): Likewise. + (select_arm_features): Make sure we enable MVE bits when selecting + armv8.1-m.main. Make sure we do not enable MVE bits when not selecting + any architecture. - * s12z-opc.c (bm_decode): Handle bit map operations with the - "reserved0" mode. +2020-01-16 Jan Beulich -2019-04-15 Thomas Preud'homme + * i386-opc.tbl: Drop stale comment from XOP section. - * arm-dis.c (coprocessor_opcodes): Document new %J and %K format - specifier. Add entries for VLDR and VSTR of system registers. - (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in - coprocessor instructions on Armv8.1-M Mainline targets. Add handling - of %J and %K format specifier. +2020-01-16 Jan Beulich -2019-04-15 Thomas Preud'homme + * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. + (extractps): Add VexWIG to SSE2AVX forms. + * i386-tbl.h: Re-generate. - * arm-dis.c (coprocessor_opcodes): Document new %C format control code. - Add new entries for VSCCLRM instruction. - (print_insn_coprocessor): Handle new %C format control code. +2020-01-16 Jan Beulich -2019-04-15 Thomas Preud'homme + * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop + Size64 from and use VexW1 on SSE2AVX forms. + (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from + VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1. + * i386-tbl.h: Re-generate. - * arm-dis.c (enum isa): New enum. - (struct sopcode32): New structure. - (coprocessor_opcodes): change type of entries to struct sopcode32 and - set isa field of all current entries to ANY. - (print_insn_coprocessor): Change type of insn to struct sopcode32. - Only match an entry if its isa field allows the current mode. +2020-01-15 Alan Modra -2019-04-15 Thomas Preud'homme + * tic4x-dis.c (tic4x_version): Make unsigned long. + (optab, optab_special, registernames): New file scope vars. + (tic4x_print_register): Set up registernames rather than + malloc'd registertable. + (tic4x_disassemble): Delete optable and optable_special. Use + optab and optab_special instead. Throw away old optab, + optab_special and registernames when info->mach changes. - * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for - CLRM. - (print_insn_thumb32): Add logic to print %n CLRM register list. +2020-01-14 Sergey Belyashov -2019-04-15 Sudakshina Das + PR 25377 + * z80-dis.c (suffix): Use .db instruction to generate double + prefix. - * arm-dis.c (print_insn_thumb32): Updated to accept new %P - and %Q patterns. +2020-01-14 Alan Modra -2019-04-15 Sudakshina Das + * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short + values to unsigned before shifting. - * arm-dis.c (thumb32_opcodes): New instruction bfcsel. - (print_insn_thumb32): Edit the switch case for %Z. +2020-01-13 Thomas Troeger -2019-04-15 Sudakshina Das + * arm-dis.c (print_insn_arm): Fill in insn info fields for control + flow instructions. + (print_insn_thumb16, print_insn_thumb32): Likewise. + (print_insn): Initialize the insn info. + * i386-dis.c (print_insn): Initialize the insn info fields, and + detect jumps. - * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. +2012-01-13 Claudiu Zissulescu -2019-04-15 Sudakshina Das + * arc-opc.c (C_NE): Make it required. - * arm-dis.c (thumb32_opcodes): New instruction bfl. +2012-01-13 Claudiu Zissulescu -2019-04-15 Sudakshina Das + * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo + reserved register name. - * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. +2020-01-13 Alan Modra -2019-04-15 Sudakshina Das + * ns32k-dis.c (Is_gen): Use strchr, add 'f'. + (print_insn_ns32k): Adjust ioffset for 'f' index_offset. - * arm-dis.c (print_insn_thumb32): Add '%S' to print an - Arm register with r13 and r15 unpredictable. - (thumb32_opcodes): New instructions for bfx and bflx. +2020-01-13 Alan Modra -2019-04-15 Sudakshina Das + * wasm32-dis.c (print_insn_wasm32): Localise variables. Store + result of wasm_read_leb128 in a uint64_t and check that bits + are not lost when copying to other locals. Use uint32_t for + most locals. Use PRId64 when printing int64_t. - * arm-dis.c (thumb32_opcodes): New instructions for bf. +2020-01-13 Alan Modra -2019-04-15 Sudakshina Das + * score-dis.c: Formatting. + * score7-dis.c: Formatting. - * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. +2020-01-13 Alan Modra -2019-04-15 Sudakshina Das + * score-dis.c (print_insn_score48): Use unsigned variables for + unsigned values. Don't left shift negative values. + (print_insn_score32): Likewise. + * score7-dis.c (print_insn_score32, print_insn_score16): Likewise. - * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. +2020-01-13 Alan Modra -2019-04-15 Thomas Preud'homme + * tic4x-dis.c (tic4x_print_register): Remove dead code. - * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. +2020-01-13 Alan Modra -2019-04-12 John Darrington + * fr30-ibld.c: Regenerate. - s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with - "optr". ("operator" is a reserved word in c++). +2020-01-13 Alan Modra -2019-04-11 Sudakshina Das + * xgate-dis.c (print_insn): Don't left shift signed value. + (ripBits): Formatting, use 1u. - * aarch64-opc.c (aarch64_print_operand): Add case for - AARCH64_OPND_Rt_SP. - (verify_constraints): Likewise. - * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. - (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions - to accept Rt|SP as first operand. - (AARCH64_OPERANDS): Add new Rt_SP. - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. +2020-01-10 Alan Modra -2019-04-11 Sudakshina Das + * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. + * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval. - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Likewise. - * aarch64-opc-2.c: Likewise. - * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. - -2019-04-09 Robert Suchanek - - * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. - -2019-04-08 H.J. Lu - - * i386-opc.tbl: Consolidate AVX512 BF16 entries. - * i386-init.h: Regenerated. - -2019-04-07 Alan Modra - - * ppc-dis.c (print_insn_powerpc): Use a tiny state machine - op_separator to control printing of spaces, comma and parens - rather than need_comma, need_paren and spaces vars. - -2019-04-07 Alan Modra - - PR 24421 - * arm-dis.c (print_insn_coprocessor): Correct bracket placement. - (print_insn_neon, print_insn_arm): Likewise. +2020-01-10 Alan Modra -2019-04-05 Xuepeng Guo - - * i386-dis-evex.h (evex_table): Updated to support BF16 - instructions. - * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 - and EVEX_W_0F3872_P_3. - * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. - (cpu_flags): Add bitfield for CpuAVX512_BF16. - * i386-opc.h (enum): Add CpuAVX512_BF16. - (i386_cpu_flags): Add bitfield for cpuavx512_bf16. - * i386-opc.tbl: Add AVX512 BF16 instructions. - * i386-init.h: Regenerated. - * i386-tbl.h: Likewise. - -2019-04-05 Alan Modra - - * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. - (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics - to favour printing of "-" branch hint when using the "y" bit. - Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. - -2019-04-05 Alan Modra - - * ppc-dis.c (print_insn_powerpc): Delay printing spaces after - opcode until first operand is output. - -2019-04-04 Peter Bergner - - PR gas/24349 - * ppc-opc.c (valid_bo_pre_v2): Add comments. - (valid_bo_post_v2): Add support for 'at' branch hints. - (insert_bo): Only error on branch on ctr. - (get_bo_hint_mask): New function. - (insert_boe): Add new 'branch_taken' formal argument. Add support - for inserting 'at' branch hints. - (extract_boe): Add new 'branch_taken' formal argument. Add support - for extracting 'at' branch hints. - (insert_bom, extract_bom, insert_bop, extract_bop): New functions. - (BOE): Delete operand. - (BOM, BOP): New operands. - (RM): Update value. - (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. - (powerpc_opcodes) : Replace BOE with BOM. - (powerpc_opcodes) : Replace BOE with BOP. - : New extended mnemonics. - -2019-03-28 Alan Modra - - PR 24390 - * ppc-opc.c (BTF): Define. - (powerpc_opcodes): Use for mtfsb*. - * ppc-dis.c (print_insn_powerpc): Print fields with both - PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. - -2019-03-25 Tamar Christina - - * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. - (mapping_symbol_for_insn): Implement new algorithm. - (print_insn): Remove duplicate code. - -2019-03-25 Tamar Christina - - * aarch64-dis.c (print_insn_aarch64): - Implement override. - -2019-03-25 Tamar Christina - - * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search - order. - -2019-03-25 Tamar Christina - - * aarch64-dis.c (last_stop_offset): New. - (print_insn_aarch64): Use stop_offset. - -2019-03-19 H.J. Lu - - PR gas/24359 - * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to - CPU_ANY_AVX2_FLAGS. - * i386-init.h: Regenerated. - -2019-03-18 H.J. Lu - - PR gas/24348 - * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, - vmovdqu16, vmovdqu32 and vmovdqu64. - * i386-tbl.h: Regenerated. + * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, + and XRREG value earlier to avoid a shift with negative exponent. + * m10200-dis.c (disassemble): Similarly. -2019-03-12 Andreas Krebbel +2020-01-09 Nick Clifton - * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand - from vstrszb, vstrszh, and vstrszf. + PR 25224 + * z80-dis.c (ld_ii_ii): Use correct cast. -2019-03-12 Andreas Krebbel +2020-01-03 Sergey Belyashov - * s390-opc.txt: Add instruction descriptions. + PR 25224 + * z80-dis.c (ld_ii_ii): Use character constant when checking + opcode byte value. -2019-02-08 Jim Wilson +2020-01-09 Jan Beulich - * riscv-opc.c (riscv_opcodes) : Use Cz to compress 3 operand form. - : Likewise. + * i386-dis.c (SEP_Fixup): New. + (SEP): Define. + (dis386_twobyte): Use it for sysenter/sysexit. + (enum x86_64_isa): Change amd64 enumerator to value 1. + (OP_J): Compare isa64 against intel64 instead of amd64. + * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64 + forms. + * i386-tbl.h: Re-generate. -2019-02-07 Tamar Christina +2020-01-08 Alan Modra - * arm-dis.c (arm_opcodes): Redefine hlt to armv1. + * z8k-dis.c: Include libiberty.h + (instr_data_s): Make max_fetched unsigned. + (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. + Don't exceed byte_info bounds. + (output_instr): Make num_bytes unsigned. + (unpack_instr): Likewise for nibl_count and loop. + * z8kgen.c (gas ): Make noperands, length and + idx unsigned. + * z8k-opc.h: Regenerate. -2019-02-07 Tamar Christina +2020-01-07 Shahab Vahedi - PR binutils/23212 - * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. - * aarch64-opc.c (verify_elem_sd): New. - (fields): Add FLD_sz entr. - * aarch64-tbl.h (_SIMD_INSN): New. - (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and - fmulx scalar and vector by element isns. + * arc-tbl.h (llock): Use 'LLOCK' as class. + (llockd): Likewise. + (scond): Use 'SCOND' as class. + (scondd): Likewise. + (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit. + (scondd): Likewise. -2019-02-07 Nick Clifton +2020-01-06 Alan Modra - * po/sv.po: Updated Swedish translation. + * m32c-ibld.c: Regenerate. -2019-01-31 Andreas Krebbel +2020-01-06 Alan Modra - * s390-mkopc.c (main): Accept arch13 as cpu string. - * s390-opc.c: Add new instruction formats and instruction opcode - masks. - * s390-opc.txt: Add new arch13 instructions. + PR 25344 + * z80-dis.c (suffix): Don't use a local struct buffer copy. + Peek at next byte to prevent recursion on repeated prefix bytes. + Ensure uninitialised "mybuf" is not accessed. + (print_insn_z80): Don't zero n_fetch and n_used here,.. + (print_insn_z80_buf): ..do it here instead. -2019-01-25 Sudakshina Das +2020-01-04 Alan Modra - * aarch64-tbl.h (QL_LDST_AT): Update macro. - (aarch64_opcode): Change encoding for stg, stzg - st2g and st2zg. - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. + * m32r-ibld.c: Regenerate. -2019-01-25 Sudakshina Das +2020-01-04 Alan Modra - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Likewise. - * aarch64-opc-2.c: Likewise. - * aarch64-tbl.h (aarch64_opcode): Add new stzgm. - -2019-01-25 Sudakshina Das - Ramana Radhakrishnan - - * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. - * aarch64-asm.h (ins_addr_simple_2): Likeiwse. - * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. - * aarch64-dis.h (ext_addr_simple_2): Likewise. - * aarch64-opc.c (operand_general_constraint_met_p): Remove - case for ldstgv_indexed. - (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. - * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. - (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. - * aarch64-asm-2.c: Regenerated. - * aarch64-dis-2.c: Regenerated. - * aarch64-opc-2.c: Regenerated. - -2019-01-23 Nick Clifton + * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. - * po/pt_BR.po: Updated Brazilian Portuguese translation. +2020-01-04 Alan Modra -2019-01-21 Nick Clifton + * crx-dis.c (match_opcode): Avoid shift left of signed value. - * po/de.po: Updated German translation. - * po/uk.po: Updated Ukranian translation. +2020-01-04 Alan Modra -2019-01-20 Chenghua Xu - * mips-dis.c (mips_arch_choices): Fix typo in - gs464, gs464e and gs264e descriptors. + * d30v-dis.c (print_insn): Avoid signed overflow in left shift. -2019-01-19 Nick Clifton +2020-01-03 Jan Beulich - * configure: Regenerate. - * po/opcodes.pot: Regenerate. + * aarch64-tbl.h (aarch64_opcode_table): Use + SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. -2018-06-24 Nick Clifton +2020-01-03 Jan Beulich - 2.32 branch created. + * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD + forms of SUDOT and USDOT. -2019-01-09 John Darrington +2020-01-03 Jan Beulich - * s12z-dis.c (print_insn_s12z): Do not dereference an operand - if it is null. - -dis.c (opr_emit_disassembly): Do not omit an index if it is - zero. + * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from + uzip{1,2}. + * opcodes/aarch64-dis-2.c: Re-generate. -2019-01-09 Andrew Paprocki +2020-01-03 Jan Beulich - * configure: Regenerate. + * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit + FMMLA encoding. + * opcodes/aarch64-dis-2.c: Re-generate. -2019-01-07 Alan Modra +2020-01-02 Sergey Belyashov - * configure: Regenerate. - * po/POTFILES.in: Regenerate. - -2019-01-03 John Darrington - - * s12z-opc.c: New file. - * s12z-opc.h: New file. - * s12z-dis.c: Removed all code not directly related to display - of instructions. Used the interface provided by the new files - instead. - * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. - * Makefile.in: Regenerate. - * configure.ac (bfd_s12z_arch): Correct the dependencies. - * configure: Regenerate. + * z80-dis.c: Add support for eZ80 and Z80 instructions. -2019-01-01 Alan Modra +2020-01-01 Alan Modra Update year range in copyright notice of all files. -For older changes see ChangeLog-2018 +For older changes see ChangeLog-2019 -Copyright (C) 2019 Free Software Foundation, Inc. +Copyright (C) 2020 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright