X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=debf81e0e37906af79090c9a04150d6090b18fdc;hb=7b61b0945fdd8320955a04e1f53b9d4d637d25bf;hp=7f9ec69bde06ae84067195766867d1c7e091fd17;hpb=f4cbd84efee69de9e1d9a4c5fbb78d3b8c7c99d2;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7f9ec69bde..debf81e0e3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,664 @@ +Fri Jun 19 09:16:42 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. + +start-sanitize-am33 +Fri Jun 19 09:42:51 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Support for 3 byte and 4 byte extended instructions + found on the mn10300. + +end-sanitize-am33 +1998-06-18 Ulrich Drepper + + * i386-dis.c: Add support for fxsave, fxrstor, sysenter and + sysexit. + +Thu Jun 18 10:22:24 1998 John Metzler + + * mips-dis.c (print_insn_little_mips): Previously, instruction + printing references the symbol table to determine whether the + instruction resides in a block regular instructions or mips16 + instructions. However, when the disassembler gets used in other + environments where the symbol table is not present, we no longer + rely in the symbol table, rather, use the low bit of the + instructions address to guess. There should be no change for usage + of the disassembler in host based programse, gdb ,objdump. + (print_insn_big_mips): ditto. + (print_insn_mips): ditto + +Wed Jun 17 21:19:01 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes. + +Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com) + +start-sanitize-am33 + * m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New + operands for the am33. + (mn10300_opcodes): Add new instructions from the am33. +end-sanitize-am33 + * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". + +Tue Jun 16 13:10:51 1998 Alan Modra + + * i386-dis.c (index16): Add '%' to register names. Use ',' + instead of '+'. + +Sat Jun 13 11:33:55 1998 Alan Modra + + * i386-dis.c: Don't print opcode suffix when we can figure out the + size (and gas can!) by register operands, or from the default + size. + (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' + macro to 'E'. + (dis386, dis386_twobyte, grps): Use new suffix macros. + (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be + consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse + order of cmps operands to agree with Intel docs. Correct operand + of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to + agree with Intel docs. + (print_insn_x86): Print orphan fwait before other prefixes. + Return correct byte count for orphan fwait with prefixes. Don't + print `bound' operands in reverse order. + (ckprefix): Stop accumulating prefixes if we get fwait. + (OP_DIR): Print `$' before Ap operands of ljmp, lcall. + +Fri Jun 12 13:40:38 1998 Tom Tromey + + * po/Make-in (all-yes): If maintainer mode, depend on .pot file. + ($(PACKAGE).pot): Unconditionally depend on POTFILES. + +Fri Jun 12 11:04:06 1998 Andreas Schwab + + Fix problems when bfd_vma is wider than long. + * i386-dis.c: Make op_address and start_pc unsigned. + (set_op): Make parameter unsigned. + (print_insn_x86): Cast to bfd_vma when passing a value to + print_address_func. + * ns32k-dis.c (CORE_ADDR): Don't define. + (print_insn_ns32k): Change type of addr to bfd_vma. Use + bfd_scan_vma to read back address. + (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma + to format it. + * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. + (NEXTULONG): New definition. + (print_insn_m68k): Avoid overflow when computing third argument of + print_insn_arg. + (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. + Use disp instead of val to store offset values. + (print_indexed): Use base_disp instead of word to store base + displacement, to avoid overflow. + * m10300-dis.c (disassemble): Cast value to long when computing + pc-relative address, to get correct sign extension. + +Wed Jun 10 15:58:37 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Tue Jun 9 14:27:57 1998 Nick Clifton + + * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as + 'mov rX, rY'. Patch courtesy of Tony Thompson + +Mon Jun 8 18:17:21 1998 Nick Clifton + + * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn. + +Fri Jun 5 23:47:55 1998 Alan Modra + + * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* + functions to void. + (OP_DSreg): Rename from OP_DSSI. + (OP_ESreg): Rename from OP_ESDI. + (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. + (DSBX): Define. + (append_seg): Rename from append_prefix. + (ptr_reg): New function. + (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. + Add DSBX for xlat. + (PREFIX_ADDR): Rename from PREFIX_ADR. + (float_reg): Add non-broken opcodes for people who don't want + UNIXWARE_COMPAT. + +Fri Jun 5 19:15:04 1998 Andreas Schwab + + * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on + 68000/68008/68010. + +Wed Jun 3 18:56:22 1998 H.J. Lu + + * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS". + +Tue Jun 2 15:06:46 1998 Geoff Keating + + * ppc-opc.c (powerpc_macros): Support shifts and rotates of size + 0; produce error message for shifts of size 32 (or 64 for 64-bit + shifts), because the hardware doesn't support them. + +start-sanitize-r5900 +Mon Jun 1 10:27:26 1998 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c (c.lt.s): Remove r5900 specific variant. + (c.le.s): Likewise. + + * vu0.h (sqc2): Fix opcode. + + * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1 + (sqrt.s): Likewise. + +end-sanitize-r5900 +start-sanitize-vr5400 +Thu May 28 08:46:09 1998 Catherine Moore + + * mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu): + Change pinfo to use WR_HILO. + +end-sanitize-vr5400 +start-sanitize-d30v +Wed May 27 15:29:13 1998 Nick Clifton + + * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b, + LONG_2, LONG_2b formats to use this new operand. + +end-sanitize-d30v +Tue May 26 20:47:48 1998 Stan Cox + + * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le. + +Tue May 26 20:45:33 1998 Mark Alexander + + * sparc-dis.c (print_insn_sparc): big endian instruction / little + endian data support. + +start-sanitize-d30v +Tue May 26 16:14:39 1998 Nick Clifton + + * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3 + and SHORT_B3b formats to use Rb instead of Ra. + + Add FLAG_MUL16 to MUL2XH opcode. + + Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension + to existing 1.1.1 parallelisation prohibition procedure. + +end-sanitize-d30v +Fri May 22 16:00:00 1998 Doug Evans + + * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts. + * cgen-dis.in (extract_normal): Likewise. + * m32r-asm.c,m32r-dis.c: Regenerate. + +start-sanitize-sky +Fri May 22 11:44:10 1998 Doug Evans + + * dvp-opc.c (parse_dotdest): Missing dest -> xyzw. + +end-sanitize-sky +start-sanitize-r5900 +Wed May 20 00:22:27 1998 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c (multu1): Add two operand variant for the r5900. + +end-sanitize-r5900 +Tue May 19 17:36:08 1998 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly + with a shift count of 0. + +start-sanitize-r5900 +Mon May 18 14:27:06 1998 Frank Ch. Eigler + + * mips-opc.c (mult1): Add two-operand variety of mult1 for R5900. + +Mon May 18 11:44:00 1998 Jeffrey A Law (law@cygnus.com) + + * mips-dis.c (print_insn_arg): Handle ';' opcode completer. + (_print_insn_mips): Likewise. + * vu0.h (vopmula, vopmsub): Correctly handle opcode/operand + completers. + +end-sanitize-r5900 +Fri May 15 14:58:31 1998 Doug Evans + + * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. + (cgen_hw_lookup_by_num): New function. + +start-sanitize-m32rx + * m32r-opc.c, m32r-opc.h: Regenerate, delete h-abort. + +end-sanitize-m32rx +Wed May 13 17:03:59 1998 Doug Evans + + * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA). + +Wed May 13 14:34:31 1998 Mark Alexander + + * sparc-dis.c (print_insn_sparc): Always fetch instructions + as big-endian on SPARClite. + +start-sanitize-m32rx +Tue May 12 13:39:51 1998 Nick Clifton + + * m32r-opc.c: Regenerated - SPECIAL attribute added to some + insns. + * m32r-opc.h: Regenerated - SPECIAL attribute added to some + insns. + +end-sanitize-m32rx +start-sanitize-d30v +Tue May 12 11:46:31 1998 Richard Henderson + + * d30v-opc.c (pre_defined_register): Remove alias for r0. + +end-sanitize-d30v +start-sanitize-r5900 +Mon May 11 13:12:15 1998 Frank Ch. Eigler + + * mips-opc.c (break): Added 20-bit single-operand break + instruction for R5900 only. + +end-sanitize-r5900 +Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com) + + * po/Make-in (install-info): New target. + +Thu May 7 17:15:59 1998 Ian Lance Taylor + + * configure.in (WIN32LIBADD): Add -lintl on cygwin32. + * configure: Rebuild. + +Thu May 7 12:49:46 1998 Frank Ch. Eigler + + * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand + variety of ISA2 instructions to set bottom ten bits of trap code. + +Thu May 7 11:54:25 1998 Ian Lance Taylor + + * Makefile.am (config.status): Add explicit target so that + config.status depends upon bfd/configure.in. + * Makefile.in: Rebuild. + +Thu May 7 09:33:02 1998 Frank Ch. Eigler + + * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1 + instructions to set bottom ten bits of break code. + * mips-dis.c (print_insn_arg): Implement 'q' operand format used + for above optional argument. + +start-sanitize-cygnus +Wed May 6 14:47:17 1998 Doug Evans + + * cgen.sh: s/@ARCH@/${ARCH}/ in opc.h generation. + * m32r-opc.h: Regenerate. + +end-sanitize-cygnus +Wed May 6 15:30:06 1998 Klaus Kaempf + + * makefile.vms: Run dec c with /nodebug. + +Mon May 4 10:19:57 1998 Tom Tromey + + * Makefile.in: Rebuilt. + * Makefile.am: Regenerated dependencies with mkdep. + + * opintl.h (_): Define as dgettext. + +start-sanitize-cygnus +Fri May 1 13:47:42 1998 Doug Evans + + * configure.in: Add support for --enable-cgen-maint. + * Makefile.am (M32R_DEPS): New variable. + (m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c): Update dependencies. + * aclocal.m4: Regenerate. + * Makefile.in: Regenerate. + * configure: Regenerate. + + * Makefile.am (CGENFILES): Add minsn.scm. + +end-sanitize-cygnus +Tue Apr 28 14:12:12 1998 Nick Clifton + + * cgen-asm.c: Internationalised. +start-sanitize-cygnus + * cgen-asm.in: Internationalised. + * cgen-opc.in: Internationalised. +end-sanitize-cygnus + * m32r-asm.c: Internationalised. + * m32r-dis.c: Internationalised. + * m32r-opc.c: Internationalised. + + * aclocal.m4: Regenerated. + * configure: Regenerated. + * Makefile.am (POTFILES): Remove inclusion of BFD_H. + * Makefile.in: Rebuild. + * po/POTFILES.in: Rebuilt using rule in Makefile.in. + * po/opcodes.pot: Rebuilt after changing POTFILES.in. + +Tue Apr 28 13:13:13 1998 Ian Lance Taylor + + * configure.in: Call AC_ISC_POSIX near start. Move CY_GNU_GETTEXT + after AC_PROG_CC. + * aclocal.m4, configure: Rebuild with current tools. + +Mon Apr 27 14:31:00 1998 Nick Clifton + + * opintl.h: New file - contains internationalisation macros used + by source files in this directory. + * po/: New subdirectory - contains internationalisation files. + * po/Make-in: New file - Makefile constructor. + * po/POTFILES.in: New file - list of files in opcodes directory + that should be scan for internationalisation macros. + * po/opcodes.pot: New file - list of internationisation strings + found in files mentioned in po/POTFILES.in. + * Makefile.am: Add rule to build po/POTFILES.in. Add SUBDIRS + entry. Add intl directory to include paths. + * acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT, + HAVE_STRCPY, HAVE_LC_MESSAGES + * configure.in: Add rule to build Makefile in po subdirectory. + * Makefile.in: Rebuilt. + * aclocal.m4: Rebuilt. + * config.in: Rebuilt. + * configure: Rebuilt. + * alpha-opc.c: Internationalised. + * arc-dis.c: Internationalised. + * arc-opc.c: Internationalised. + * arm-dis.c: Internationalised. + * cgen-asm.c: Internationalised. +start-sanitize-d30v + * d30v-dis.c: Internationalised. +end-sanitize-d30v + * dis-buf.c: Internationalised. +start-sanitize-sky + * dvp-dis.c: Internationalised. + * dvp-opc.c: Internationalised. +end-sanitize-sky + * h8300-dis.c: Internationalised. + * h8500-dis.c: Internationalised. + * i386-dis.c: Internationalised. + * m10200-dis.c: Internationalised. + * m10300-dis.c: Internationalised. + * m68k-dis.c: Internationalised. + * m88k-dis.c: Internationalised. + * mips-dis.c: Internationalised. + * ns32k-dis.c: Internationalised. + * opintl.h: Internationalised. + * ppc-opc.c: Internationalised. + * sparc-dis.c: Internationalised. + * v850-dis.c: Internationalised. + * v850-opc.c: Internationalised. + +Mon Apr 27 10:33:56 1998 Doug Evans + + * cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data. + (asm_hash_table_entries): New variable. + (cgen_asm_init): Free asm_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_asm_hash_table): Use them. Hash macro insns as well. + (cgen_asm_lookup_insn): Update. + * cgen_dis.c (cgen_current_opcode_table): Renamed from ..._data. + (dis_hash_table_entries): New variable. + (cgen_dis_init): Free dis_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_dis_hash_table): Use them. Hash macro insns as well. + (cgen_dis_lookup_insn): Update. + * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. + (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. + (cgen_macro_insn_count): New function. + * cgen-opc.in (@arch@_cgen_lookup_insn): New arg alias_p. + All callers updated. Sanity check result of extract fn. + (@arch@_cgen_get_insn_operands): Change result type to void. + Delete args insn_value, length. New arg fields. All callers updated. + (@arch@_cgen_lookup_get_insn_operands): New function. + * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + +Fri Apr 24 16:07:57 1998 Alan Modra + + * i386-dis.c (OP_DSSI): Print segment override. + +start-sanitize-r5900 +Thu Apr 23 12:32:07 1998 Frank Ch. Eigler + + * mips-opc.c (msub.s): Correct mask pattern for disassembly. + +end-sanitize-r5900 +start-sanitize-r5900 +Mon Apr 20 19:11:55 1998 Frank Ch. Eigler + + * mips-opc.c (madd.s): Correct mask pattern for disassembly. + +end-sanitize-r5900 +start-sanitize-r5900 +Sat Apr 18 00:29:18 1998 Jeffrey A Law (law@cygnus.com) + + * vu0.h (vlqd, vlqi): Update per revised specs. + +end-sanitize-r5900 +start-sanitize-sky +Thu Apr 16 11:44:59 1998 Doug Evans + + * dvp-opc.c (parse_vif_unpackloc,insert_vif_unpackloc): Delete. + (vif_operands): Update. + (vif_get_unpackloc): Delete. + (state_vif_unpackloc{,_star_p}): Delete. + (dvp_opcode_init_parse): Update. + (vif_unpack_len_value): Avoid divide by zero. + +end-sanitize-sky +start-sanitize-r5900 +Wed Apr 15 10:30:07 1998 Frank Ch. Eigler + + * vu0.h: Specs changed for VCALLMSR bit pattern. + * mips-dis.c: (print_insn_arg) Matching change. + +end-sanitize-r5900 +Mon Apr 13 16:59:39 1998 Nick Clifton + + * arm-dis.c (print_insn_arm): Add "_all" extension to 'C' + operator. + +Mon Apr 13 16:50:27 1998 Ian Lance Taylor + + * Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@. + (libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@. + * configure.in: Define and substitute WIN32LDFLAGS and + WIN32LIBADD. + * aclocal.m4: Rebuild with new libtool. + * configure, Makefile.in: Rebuild. + +start-sanitize-r5900 +Mon Apr 13 16:02:02 1998 Frank Ch. Eigler + + * vu0.h: Corrected bit pattern for VMAXI opcode. + +end-sanitize-r5900 +Fri Apr 10 18:14:31 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +start-sanitize-sky +Mon Apr 6 17:16:48 1998 Doug Evans + + * dvp-opc.c (vif_macros): Tweak unpackloc operand. + (dvp_expand_macro): Implement. + (insert_vif_datalen): Record value with max+1 -> 0 conversion. + (vif_unpack_len): Perform 0 -> max+1 conversion on `wl' value. + +end-sanitize-sky +Sun Apr 5 16:04:39 1998 H.J. Lu + + * Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists + before trying to copy it. + * Makefile.in: Rebuild. + +Thu Apr 2 17:25:49 1998 Nick Clifton + + * m32r-opc.c: Use signed immediate values for CMPUI instruction. + +start-sanitize-m32rx +Thu Apr 2 16:44:23 1998 Nick Clifton + + * m32r-opc.c: Fix bit patterns for SAT and SATB. + +end-sanitize-m32rx +Wed Apr 1 16:20:27 1998 Ian Dall + + * ns32k-dis.c (bit_extract_simple): New function to extract bits + from an arbitrary valid buffer instead of fetching them on demand + using fetch_data(). + (invalid_float): use bit_extract_simple() instead of bit_extract(). + +start-sanitize-m32rx +Wed Apr 1 14:57:54 1998 Nick Clifton + + * m32r-opc.c: Fix SATB bit pattern. Add extra control registers. + * m32r-opc.h: Add extra control registers. + +end-sanitize-m32rx +Tue Mar 31 11:09:08 1998 Ian Lance Taylor + + From H.J. Lu : + * i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew + to Ev for both. + +Mon Mar 30 17:32:03 1998 Ian Lance Taylor + + * Branched binutils 2.9. + +start-sanitize-d30v +Mon Mar 30 15:18:00 1998 Ken Raeburn + + * d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when + disassembling last 4 bytes of a section. + +end-sanitize-d30v +Fri Mar 27 18:08:13 1998 Ian Lance Taylor + + Fix some gcc -Wall warnings: + * arc-dis.c (print_insn): Add casts to avoid warnings. + * cgen-opc.c (cgen_keyword_lookup_name): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. +start-sanitize-sky + * dvp-opc.c (issymchar, SKIP_BLANKS): Likewise. + (parse_dotdest, parse_dotdest1, u_parse_sdest): Likewise. + (parse_bc, parse_vfreg, parse_accdest): Likewise. + (parse_ffstreg, parse_vif_mode): Likewise. +end-sanitize-sky + * m10200-dis.c (disassemble): Likewise. + * m10300-dis.c (disassemble): Likewise. + * ns32k-dis.c (print_insn_ns32k): Likewise. + * ppc-opc.c (insert_ral, insert_ram): Likewise. + * cgen-dis.c (build_dis_hash_table): Remove used local variables. + * cgen-opc.c (cgen_keyword_search_next): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. +start-sanitize-d30v + * d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise. +end-sanitize-d30v +start-sanitize-sky + * dvp-dis.c (print_dma, print_vif, print_gif): Likewise. + * dvp-opc.c (parse_dest1, print_uflags): Likewise. + (parse_gif_nloop, dvp_opcode_init_tables): Likewise. +end-sanitize-sky + * ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise. +start-sanitize-tic80 + * tic80-dis.c (print_one_instruction): Likewise. +end-sanitize-tic80 + * w65-dis.c (print_operand): Likewise. + * z8k-dis.c (fetch_data): Likewise. + * a29k-dis.c: Add return type for find_byte_func_type. + * arc-opc.c: Include . Remove declarations of + insert_multshift and extract_multshift. +start-sanitize-d30v + * d30v-dis.c (lookup_opcode): Parenthesize assignments in + conditionals. + (extract_value): Fully parenthesize expression. +end-sanitize-d30v +start-sanitize-sky + * dvp-opc.c: Include . + (print_sdest): Add default case to switch. +end-sanitize-sky + * h8500-dis.c (print_insn_h8500): Initialize local variables. + * h8500-opc.h (h8500_table): Fully bracket initializer. + * w65-opc.h (optable): Likewise. + * i386-dis.c (print_insn_x86): Declare aflag and flag parameters. + * i386-dis.c (OP_E): Initialize local variables. + * m10200-dis.c (print_insn_mn10200): Likewise. + * mips-dis.c (print_insn_mips16): Likewise. + * sh-dis.c (print_insn_shx): Likewise. + * v850-dis.c (print_insn_v850): Likewise. + * ns32k-dis.c (print_insn_arg): Declare. + (get_displacement, invalid_float): Declare. + (list_search, sign_extend, flip_bytes): Declare return type. + (get_displacement): Likewise. + (print_insn_arg): Likewise. Make d int. Fix sprintf format + string. + (print_insn_ns32k): Make i unsigned. + (invalid_float): Make static. Declare type of val. + * tic30-dis.c (print_par_insn): Make i size_t. Don't check strlen + on each for iteration. + * tic30-dis.c (get_indirect_operand): Likewise. + * z8k-dis.c (print_insn_z8001): Declare return type. + (print_insn_z8002): Likewise. + (unparse_instr): Fix sprintf format strings. + +Fri Mar 27 00:05:23 1998 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Add "sync.l" and "sync.p". + +start-sanitize-sky +Thu Mar 26 13:27:37 1998 Doug Evans + + * dvp-opc.c (extract_vif_datalen): Rewrite. + (vif_insn_len): Perform 0->max+1 conversion for direct length. + +Wed Mar 25 13:32:36 1998 Doug Evans + + * dvp-dis.c (print_insn): Print unpack address in hex. + * dvp-opc.c (parse_vif_mpgloc): Renamed from parse_vif_mpgloc_star. + Don't skip over '*', just record it. + (insert_vif_mpgloc): Don't update state_vif_mpgloc if '*' value. + (parse_vif_unpackloc): Renamed from parse_vif_unpackloc_star. + Don't skip over '*', just record it. + (insert_vif_unpackloc): Don't update state_vif_unpackloc if '*' value. + (vif_operands): Delete VIF_MPGLOC_STAR,VIF_UNPACKLOC_STAR entries. + (vif_opcodes): Likewise. + (state_vif_{mpg,unpack}loc_star_p): New static locals. + (vif_macros,vif_macro_count): New globals. + (vif_unpack_len_value): New arguments wl,cl. All callers updated. + (vif_set_{mpg,unpack}loc): Delete. All callers updated. + (vif_get_wl_cl): New function. + (dvp_opcode_init_parse): Init mpgloc,unpackloc state. + +end-sanitize-sky +Wed Mar 25 14:32:48 1998 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Use info->mach to select the + default m68k variant to recognize. + + * i960-dis.c (pinsn): Change type of first argument to bfd_vma. + (ctrl, cobr, mem, ea): Likewise. + (print_addr): Likewise. Remove cast. + (ea): Cast argument of print_addr to bfd_vma. + + * cgen-asm.c (cgen_parse_signed_integer): Fix type of local + variable value. + (cgen_parse_unsigned_integer): Likewise. + (cgen_parse_address): Likewise. + +Wed Mar 25 14:31:31 1998 Ian Lance Taylor + + * i960-dis.c (ctrl): Add full braces to structure initialization. + (cobr, mem, reg): Likewise. + (ea): Correct parenthesization in expression. + + * cgen-asm.c: Include . + (build_asm_hash_table): Remove unused local variable i. + (cgen_parse_keyword): Add casts to avoid warnings. + + * arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF + symbol. Fix indentation. + (print_insn_little_arm): Likewise. + start-sanitize-r5900 Tue Mar 24 18:11:13 1998 Jeffrey A Law (law@cygnus.com) @@ -33,8 +694,7 @@ Fri Mar 20 18:55:18 1998 Ian Lance Taylor start-sanitize-r5900 Fri Mar 20 09:01:31 1998 Jeffrey A Law (law@cygnus.com) - * mips-dis.c: Change '%' to '#' to avoid conflict with vr5400 - support. + * mips-dis.c: Change '%' to '#' in r5900 support. * vu0.h: Likewise. end-sanitize-r5900 @@ -42,7 +702,7 @@ Thu Mar 19 15:46:53 1998 Nick Clifton These patches are courtesy of Jonathan Walton and Tony Thompson (athompso@cambridge.arm.com). - + * arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC relative addresses. @@ -318,8 +978,8 @@ Fri Feb 13 13:12:14 1998 Ian Lance Taylor Fri Feb 13 09:50:32 1998 Nick Clifton - * m32r-opc.c: Regenerate. - * m32r-opc.h: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. Thu Feb 12 11:01:40 1998 Doug Evans @@ -558,12 +1218,12 @@ Wed Dec 10 17:42:35 1997 Nick Clifton * arm-dis.c (print_insn_little_arm): Prevent examination of stored symbol if none is present. (print_insn_big_arm): Prevent examination of stored symbol if - none is present. + none is present. Thu Oct 23 21:13:37 1997 Fred Fish - + * d10v-opc.c (d10v_opcodes): Correct entry for RTE. - + Mon Dec 8 11:21:07 1997 Nick Clifton * disassemble.c: Remove disasm_symaddr() function. @@ -647,7 +1307,7 @@ end-sanitize-vr5400 start-sanitize-tx49 Wed Oct 29 15:10:56 1997 Gavin Koch - * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): + * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): Add tx49 insns and configury. end-sanitize-tx49 @@ -779,7 +1439,7 @@ Thu Sep 18 11:21:43 1997 Doug Evans Tue Sep 16 15:18:20 1997 Nick Clifton - * v850-opc.c (v850_opcodes): Further rearrangements. + * v850-opc.c (v850_opcodes): Further rearrangements. start-sanitize-d30v Tue Sep 16 16:12:11 1997 Ken Raeburn @@ -827,7 +1487,7 @@ Wed Aug 27 21:42:39 1997 Ken Raeburn and cmp instructions. * d30v-opc.c: Correct entries for repeat*, and sat*. - Make IMM5 unsigned. Create IMM6U and IMM12S3U operand + Make IMM5 unsigned. Create IMM6U and IMM12S3U operand types. Correct several formats. * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc. @@ -848,7 +1508,7 @@ Wed Aug 27 21:42:39 1997 Ken Raeburn New form: SHORT_A2; a SHORT_A form that needs an even register as the first operand. - * d30v-dis.c (print_insn_d30v): Fix problem where the last + * d30v-dis.c (print_insn_d30v): Fix problem where the last instruction was not being disassembled if there were an odd number of instructions. @@ -960,18 +1620,18 @@ Wed Aug 13 18:52:11 1997 Nick Clifton start-sanitize-v850e * v850-dis.c (disassemble): Add support for v850EA instructions. - + * v850-opc.c (insert_i5div, extract_i5div): New Functions. (v850_opcodes): Add v850EA instructions. * v850-dis.c (disassemble): Add support for v850E instructions. - + * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16, extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9, insert_spe, extract_spe): New Functions. (v850_opcodes): Add v850E instructions. end-sanitize-v850e - + * v850-opc.c: Reorganised and re-layed out to improve readability and portability. @@ -1056,7 +1716,7 @@ Wed Jun 25 15:25:57 1997 Felix Lee negating it. (UNUSED): remove one level of parens, so MSVC doesn't choke on nesting depth when all the macros are expanded. - + Tue Jun 17 17:02:17 1997 Ian Lance Taylor * sparc-opc.c: The fcmp v9a instructions take an integer register @@ -1115,7 +1775,7 @@ Thu May 22 14:06:02 1997 Doug Evans Tue May 20 11:26:27 1997 Gavin Koch - * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new + * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new field membership. * mips16-opc.c (mip16_opcodes): same. @@ -1287,7 +1947,7 @@ Wed Mar 19 06:53:58 1997 J.T. Conklin * m68k-opc.c (m68k_opcodes): Provide coldfire division module instructions. - + end-sanitize-coldfire Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com) @@ -1298,7 +1958,7 @@ Mon Mar 17 08:48:03 1997 J.T. Conklin * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and mulul insns on the coldfire. - + Sat Mar 15 17:13:05 1997 Ian Lance Taylor * arm-dis.c (print_insn_arm): Don't print instruction bytes. @@ -1346,7 +2006,7 @@ Mon Mar 3 07:45:20 1997 J.T. Conklin * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on the mc68000. - + Thu Feb 27 14:04:32 1997 Philippe De Muyter * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction. @@ -1375,7 +2035,7 @@ Mon Feb 24 19:26:12 1997 Dawn Perchik Mon Feb 24 15:19:01 1997 Martin M. Hunt - * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to + * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. start-sanitize-tic80 @@ -1391,9 +2051,9 @@ end-sanitize-tic80 Sat Feb 22 21:25:00 1997 Dawn Perchik * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, + Change mips_opcodes from const array to a pointer, and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table + so that we can increase the size of the mips opcodes table dynamically. start-sanitize-tic80 @@ -1411,7 +2071,7 @@ Fri Feb 21 16:31:18 1997 Martin M. Hunt * d30v-opc.c: Removed references to FLAG_X. -end-sanitize-d30v +end-sanitize-d30v Wed Feb 19 14:51:20 1997 Ian Lance Taylor * Makefile.in: Add dependencies on ../bfd/bfd.h as required. @@ -1426,11 +2086,11 @@ Tue Feb 18 17:43:43 1997 Martin M. Hunt * d30v-opc.c: New file. * disassemble.c (disassembler) Add entry for d30v. -end-sanitize-d30v +end-sanitize-d30v start-sanitize-tic80 Tue Feb 18 16:32:08 1997 Fred Fish - * tic80-opc.c (tic80_predefined_symbols): Add symbolic + * tic80-opc.c (tic80_predefined_symbols): Add symbolic representations for the floating point BITNUM values. Fri Feb 14 12:14:05 1997 Fred Fish @@ -1494,9 +2154,9 @@ Tue Feb 11 15:26:47 1997 Ian Lance Taylor start-sanitize-r5900 Fri Feb 7 11:12:44 1997 Gavin Koch - + * mips-opc.c: add r5900. - + end-sanitize-r5900 start-sanitize-tic80 Mon Feb 10 10:12:41 1997 Fred Fish @@ -1561,7 +2221,7 @@ Fri Jan 24 12:08:21 1997 J.T. Conklin * m68k-opc.c (m68k_opcodes): Changed operand specifier for the coldfire moveb instruction to not allow an address register as destination. Although the documentation does not indicate that - this is invalid, experiments uncovered unexpected behavior. + this is invalid, experiments uncovered unexpected behavior. Added a comment explaining the situation. Thanks to Andreas Schwab for pointing this out to me. @@ -1572,7 +2232,7 @@ Wed Jan 22 20:13:51 1997 Fred Fish entries are presorted so that entries with the same mnemonic are adjacent to each other in the table. Sort the entries for each instruction so that this is true. - + end-sanitize-tic80 Mon Jan 20 12:48:57 1997 Andreas Schwab @@ -1587,7 +2247,7 @@ Sat Jan 18 15:15:05 1997 Fred Fish "vsub", "vst", "xnor", and "xor" instructions. (V_a1): Renamed from V_a, msb of accumulator reg number. (V_a0): Add macro, lsb of accumulator reg number. - + Fri Jan 17 18:24:31 1997 Fred Fish * tic80-dis.c (print_insn_tic80): Broke excessively long @@ -1597,13 +2257,13 @@ Fri Jan 17 18:24:31 1997 Fred Fish math instruction packed into a single opcode. * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode to explain why it comes after the other vector opcodes. - + end-sanitize-tic80 Fri Jan 17 16:19:15 1997 J.T. Conklin - * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire + * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire move insns to handle immediate operands. - + Thu Jan 17 16:19:00 1997 Andreas Schwab * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". @@ -1619,7 +2279,7 @@ Thu Jan 16 20:54:40 1997 Fred Fish Remove some opcodes that are possible, but illegal, such as long immediate instructions with doubles for immediate values. Add "vadd" and "vld" instructions. - + Wed Jan 15 18:59:51 1997 Fred Fish * tic80-opc.c (tic80_operands): Reorder some table entries to make @@ -1645,7 +2305,7 @@ Tue Jan 14 19:42:50 1997 Fred Fish followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather than old TIC80_OPERAND_RELATIVE. Add support for new TIC80_OPERAND_BASEREL flag bit. - + Mon Jan 13 15:58:56 1997 Fred Fish * tic80-dis.c (print_insn_tic80): Print floating point operands @@ -1660,8 +2320,8 @@ Mon Jan 13 15:58:56 1997 Fred Fish (P2): Macro for the 'P2' field. (P1): Macro for the 'P1' field. (tic80_opcodes): Add entries for "exts", "extu", "fadd", - "fcmp", and "fdiv". - + "fcmp", and "fdiv". + end-sanitize-tic80 Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) @@ -1675,14 +2335,14 @@ Mon Jan 6 10:56:25 1997 Fred Fish (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. - (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, + (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, REG_BASE_M_SI, REG_BASE_M_LI respectively. (REG_SCALED, LSI_SCALED): New operand types. (E): New macro for 'E' bit at bit 27. (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap opcodes, including the various size flavors (b,h,w,d) for the direct load and store instructions. - + Sun Jan 5 12:18:14 1997 Fred Fish * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit @@ -1694,7 +2354,7 @@ Sun Jan 5 12:18:14 1997 Fred Fish (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode masks with "MASK_* & ~M_*" to get the M bit reset. (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. - + Sat Jan 4 19:05:05 1997 Fred Fish * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE @@ -1751,7 +2411,7 @@ Mon Dec 30 17:02:11 1996 Fred Fish start-sanitize-tic80 (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. end-sanitize-tic80 - + Mon Dec 30 11:38:01 1996 Ian Lance Taylor * mips16-opc.c: Add "abs". @@ -1771,7 +2431,7 @@ Fri Dec 27 22:30:57 1996 Fred Fish * configure: Regenerate with autoconf. * tic80-dis.c: Add file. * tic80-opc.c: Add file. - + end-sanitize-tic80 Fri Dec 20 14:30:19 1996 Martin M. Hunt @@ -1898,7 +2558,7 @@ Mon Nov 25 16:15:17 1996 J.T. Conklin * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use register operands for immediate arithmetic, not, neg, negx, and set according to condition instructions. - + * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage specifier of the effective-address operand in immediate forms of arithmetic instructions. The specifier for the immediate operand @@ -1909,7 +2569,7 @@ Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" opcode. - * mn10300-dis.c (disassemble): Use '$' instead of '%' for + * mn10300-dis.c (disassemble): Use '$' instead of '%' for register prefix. * mn10300-dis.c (disassemble): Prefix registers with '%'. @@ -1940,7 +2600,7 @@ Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c (mn10300_operands): Add "REGS" for a register list. (mn10300_opcodes): Use REGS for register list in "movm" instructions. - + Mon Nov 18 15:20:35 1996 Michael Meissner * d10v-opc.c (d10v_opcodes): Add3 sets the carry. @@ -1960,7 +2620,7 @@ Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c (mn10300_operands): Hijack "bits" field in MN10300_OPERAND_SPLIT operands for how many bits appear in the basic insn word. Add IMM32_HIGH24, - IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. + IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. (mn10300_opcodes): Use new operands as needed. * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 @@ -2001,7 +2661,7 @@ Fri Nov 1 10:29:11 1996 Richard Henderson standard disassembly. * alpha-opc.c (alpha_operands): Rearrange flags slot. - (alpha_opcodes): Add new BWX, CIX, and MAX instructions. + (alpha_opcodes): Add new BWX, CIX, and MAX instructions. Recategorize PALcode instructions. Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com) @@ -2069,7 +2729,7 @@ Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". - + Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. @@ -2090,7 +2750,7 @@ Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) Update many operand fields to deal with signed vs unsigned issues. Fix one or two typos in the "mov" instruction opcode, mask and/or operand fields. - + Mon Oct 7 11:39:49 1996 Andreas Schwab * m68k-opc.c (plusha): Prefer encoding for m68040up, in case @@ -2339,7 +2999,7 @@ Tue Aug 20 14:41:03 1996 J.T. Conklin * configure: (bfd_v850v_arch) Add new case. * configure.in: (bfd_v850_arch) Add new case. * v850-opc.c: New file. - + Mon Aug 19 15:21:38 1996 Doug Evans * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. @@ -3073,7 +3733,7 @@ Wed Sep 6 15:08:09 1995 Jim Wilson * sh-opc.h (sh_arg_type): Add F_FR0. (sh_table, case fmac): Add F_FR0 as first argument. - + Wed Sep 6 15:08:09 1995 Jim Wilson * sh-opc.h (sh_opcode_info): Increase arg array size to 4. @@ -3292,7 +3952,7 @@ Wed May 24 14:16:08 1995 Steve Chamberlain * sh-opc.h: Added bsrf and braf. -Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) +Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete bogus [ls]fm{ea,fd} patterns. @@ -3340,7 +4000,7 @@ Mon Apr 10 15:55:01 1995 Stan Shebs * mpw-config.in (target_arch): Compute from canonical target. (m68k, mips, powerpc, sparc): Add architectures. * mpw-make.in (disassemble.c.o): Add. - (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). + (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). * mpw-config.in (BFD_MACHINES): Set to a default value. * mpw-make.in (BFD_MACHINES): Remove wired-in value. @@ -3839,7 +4499,7 @@ Fri Jan 21 19:01:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu) * hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template. - No space before 'u', 'f', or 'N'. + No space before 'u', 'f', or 'N'. Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com) @@ -3871,7 +4531,7 @@ Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add - FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct + FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct FLOAT_FORMAT_CODE to put out floating point register names. Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) @@ -4144,7 +4804,7 @@ Fri Jun 11 18:40:21 1993 Ken Raeburn (raeburn@cygnus.com) defined, since gdb has been fixed. Changes from Jeff Law, law@cs.utah.edu: - * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, + * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, fput_reg_r, fput_creg, fput_const, and fputs_filtered should be a *disassemble_info, not a *FILE. * hppa-dis.c: Support 'd', '!', and 'a'.