X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=f0b84b1ed9f27232d38e9bb0392b939b19bf773c;hb=cf769ed505ed9b3eca24df67bb9cfc0adc1a033f;hp=4561f5385f23116d5ba508cee71598452a7d2a23;hpb=eca4b721468e239a6a1ca7c9bd9c967085067dfe;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4561f5385f..f0b84b1ed9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,175 @@ +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512DQ templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512BW templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512CD templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.h (DISP8_SHIFT_VL): New. + * i386-opc.tbl (Disp8ShiftVL): Define. + (various): Fold AVX512VL templates into their respective + AVX512F counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * Makefile.am: Change dependencies and rule for + $(srcdir)/i386-init.h. + * Makefile.in: Re-generate. + * i386-gen.c (process_i386_opcodes): New local variable + "marker". Drop opening of input file. Recognize marker and line + number directives. + * i386-opc.tbl (OPCODE_I386_H): Define. + (i386-opc.h): Include it. + (None): Undefine. + +2018-07-18 H.J. Lu + + PR gas/23418 + * i386-opc.h (Byte): Update comments. + (Word): Likewise. + (Dword): Likewise. + (Fword): Likewise. + (Qword): Likewise. + (Tbyte): Likewise. + (Xmmword): Likewise. + (Ymmword): Likewise. + (Zmmword): Likewise. + * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and + vcvttps2uqq. + * i386-tbl.h: Regenerated. + +2018-07-12 Sudakshina Das + + * aarch64-tbl.h (aarch64_opcode_table): Add entry for + ssbb and pssbb and update dsb flags to F_HAS_ALIAS. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2018-07-12 Tamar Christina + + PR binutils/23192 + * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, + mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, + umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, + sqdmulh, sqrdmulh): Use Em16. + +2018-07-11 Sudakshina Das + + * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move + csdb together with them. + (thumb32_opcodes): Likewise. + +2018-07-11 Jan Beulich + + * i386-opc.tbl (monitor, monitorx): Add 64-bit template + requiring 32-bit registers as operands 2 and 3. Improve + comments. + (mwait, mwaitx): Fold templates. Improve comments. + OPERAND_TYPE_INOUTPORTREG. + * i386-tbl.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-gen.c (operand_type_init): Remove + OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of + OPERAND_TYPE_INOUTPORTREG. + * i386-init.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-opc.tbl (wrssd, wrussd): Add Dword. + (wrssq, wrussq): Add Qword. + * i386-tbl.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-opc.h: Rename OTMax to OTNum. + (OTNumOfUints): Adjust calculation. + (OTUnused): Directly alias to OTNum. + +2018-07-09 Maciej W. Rozycki + + * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to + `reg_xys'. + (lea_reg_xys): Likewise. + (print_insn_loop_primitive): Rename `reg' local variable to + `reg_dxy'. + +2018-07-06 Tamar Christina + + PR binutils/23242 + * aarch64-tbl.h (ldarh): Fix disassembly mask. + +2018-07-06 Tamar Christina + + PR binutils/23369 + * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, + vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. + +2018-07-02 Maciej W. Rozycki + + PR tdep/8282 + * mips-dis.c (mips_option_arg_t): New enumeration. + (mips_options): New variable. + (disassembler_options_mips): New function. + (print_mips_disassembler_options): Reimplement in terms of + `disassembler_options_mips'. + * arm-dis.c (disassembler_options_arm): Adapt to using the + `disasm_options_and_args_t' structure. + * ppc-dis.c (disassembler_options_powerpc): Likewise. + * s390-dis.c (disassembler_options_s390): Likewise. + +2018-07-02 Thomas Preud'homme + + * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in + expected result. + * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. + * testsuite/ld-arm/tls-longplt-lib.d: Likewise. + * testsuite/ld-arm/tls-longplt.d: Likewise. + +2018-06-29 Tamar Christina + + PR binutils/23192 + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. + * aarch64-opc.c (operand_general_constraint_met_p, + aarch64_print_operand): Likewise. + * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, + smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, + fmlal2, fmlsl2. + (AARCH64_OPERANDS): Add Em2. + +2018-06-26 Nick Clifton + + * po/uk.po: Updated Ukranian translation. + * po/de.po: Updated German translation. + * po/pt_BR.po: Updated Brazilian Portuguese translation. + 2018-06-26 Nick Clifton * nfp-dis.c: Fix spelling mistake.