X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=f8ea8653e69d38e46224332f8a1090a50823b2cf;hb=2b02b9a2abfc773ad3cce49ecc36c37a1a84bcc9;hp=005ca9355824c2c224af92429b652c430911c279;hpb=a9660a6f4063c7e1fb892ec709c954c56896ab8d;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 005ca93558..f8ea8653e6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,661 @@ +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from GNFI insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64. + (vpbroadcastw, rdpid): Drop NoRex64. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl (vmovsd, vmovss): Fold register form load and + store templates, adding D. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd, + movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps, + movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd, + vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32, + vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups): + Fold load and store templates where possible, adding D. Drop + IgnoreSize where it was pointlessly present. Drop redundant + *word. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-dis.c (Mv_bnd, v_bndmk_mode): New. + (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk. + (intel_operand_size): Handle v_bndmk_mode. + (OP_E_memory): Likewise. Produce (bad) when also riprel. + +2018-09-08 John Darrington + + * disassemble.c (ARCH_s12z): Define if ARCH_all. + +2018-08-31 Kito Cheng + + * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for + compressed floating point instructions. + +2018-08-30 Kito Cheng + + * riscv-dis.c (riscv_disassemble_insn): Check XLEN by + riscv_opcode.xlen_requirement. + * riscv-opc.c (riscv_opcodes): Update for struct change. + +2018-08-29 Martin Aberg + + * sparc-opc.c (sparc_opcodes): Add Leon specific partial write + psr (PWRPSR) instruction. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add gs264e descriptors. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add gs464e descriptors. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep + loongson3a as an alias of gs464 for compatibility. + * mips-opc.c (mips_opcodes): Change Comments. + +2018-08-29 Chenghua Xu + + * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext + option. + (print_mips_disassembler_options): Document -M loongson-ext. + * mips-opc.c (LEXT2): New macro. + (mips_opcodes): Add cto, ctz, dcto, dctz instructions. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add EXT to loongson3a + descriptors. + (parse_mips_ase_option): Handle -M loongson-ext option. + (print_mips_disassembler_options): Document -M loongson-ext. + * mips-opc.c (IL3A): Delete. + * mips-opc.c (LEXT): New macro. + (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT + instructions. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add CAM to loongson3a + descriptors. + (parse_mips_ase_option): Handle -M loongson-cam option. + (print_mips_disassembler_options): Document -M loongson-cam. + * mips-opc.c (LCAM): New macro. + (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM + instructions. + +2018-08-21 Alan Modra + + * ppc-dis.c (operand_value_powerpc): Init "invalid". + (skip_optional_operands): Count optional operands, and update + ppc_optional_operand_value call. + * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. + (extract_vlensi): Likewise. + (extract_fxm): Return default value for missing optional operand. + (extract_ls, extract_raq, extract_tbr): Likewise. + (insert_sxl, extract_sxl): New functions. + (insert_esync, extract_esync): Remove Power9 handling and simplify. + (powerpc_operands ): Delete PPC_OPERAND_OPTIONAL_VALUE + flag and extra entry. + (powerpc_operands ): Likewise, and use insert_sxl and + extract_sxl. + +2018-08-20 Alan Modra + + * sh-opc.h (MASK): Simplify. + +2018-08-18 John Darrington + + * s12z-dis.c (bm_decode): Deal with cases where the mode is + BM_RESERVED0 or BM_RESERVED1 + (bm_rel_decode, bm_n_bytes): Ditto. + +2018-08-18 John Darrington + + * s12z.h: Delete. + +2018-08-14 H.J. Lu + + * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for + address with the addr32 prefix and without base nor index + registers. + +2018-08-11 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to + CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS, + CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS. + (cpu_flags): Add CpuCMOV and CpuFXSR. + * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64, + fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2018-08-06 Claudiu Zissulescu + + * arc-regs.h: Update auxiliary registers. + +2018-08-06 Jan Beulich + + * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines. + (RegIP, RegIZ): Define. + * i386-reg.tbl: Adjust comments. + (rip): Use Qword instead of BaseIndex. Use RegIP. + (eip): Use Dword instead of BaseIndex. Use RegIP. + (riz): Add Qword. Use RegIZ. + (eiz): Add Dword. Use RegIZ. + * i386-tbl.h: Re-generate. + +2018-08-03 Jan Beulich + + * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw, + pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw, + vpmovzxdq, vpmovzxwd): Remove NoRex64. + * i386-tbl.h: Re-generate. + +2018-08-03 Jan Beulich + + * i386-gen.c (operand_types): Remove Mem field. + * i386-opc.h (union i386_operand_type): Remove mem field. + * i386-init.h, i386-tbl.h: Re-generate. + +2018-08-01 Alan Modra + + * po/POTFILES.in: Regenerate. + +2018-07-31 Nick Clifton + + * po/sv.po: Updated Swedish translation. + +2018-07-31 Jan Beulich + + * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize. + * i386-init.h, i386-tbl.h: Re-generate. + +2018-07-31 Jan Beulich + + * i386-opc.h (ZEROING_MASKING) Rename to ... + (DYNAMIC_MASKING): ... this. Adjust comment. + * i386-opc.tbl (MaskingMorZ): Define. + (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4, + vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4, + vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps, + vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64, + vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd, + vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw, + vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb, + vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw, + vpmovuswb, vpmovwb): Fold AVX512 register and memory forms. + +2018-07-31 Jan Beulich + + * i386-opc.tbl: Use element rather than vector size for AVX512* + scatter/gather insns. + * i386-tbl.h: Re-generate. + +2018-07-31 Jan Beulich + + * i386-gen.c (cpu_flag_init): Drop CpuVREX uses. + (cpu_flags): Drop CpuVREX. + * i386-opc.h (CpuVREX): Delete. + (union i386_cpu_flags): Remove cpuvrex. + * i386-init.h, i386-tbl.h: Re-generate. + +2018-07-30 Jim Wilson + + * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size + fields. + * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns. + +2018-07-30 Andrew Jenner + + * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. + * Makefile.in: Regenerated. + * configure.ac: Add C-SKY. + * configure: Regenerated. + * csky-dis.c: New file. + * csky-opc.h: New file. + * disassemble.c (ARCH_csky): Define. + (disassembler, disassemble_init_for_target): Add case for ARCH_csky. + * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. + +2018-07-27 Alan Modra + + * ppc-opc.c (insert_sprbat): Correct function parameter and + return type. + (extract_sprbat): Likewise, variable too. + +2018-07-26 Alex Chadwick + Alan Modra + + * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. + (powerpc_init_dialect): Handle bfd_mach_ppc_750. + * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to + support disjointed BAT. + (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. + (XSPRGQR_MASK, GEKKO, BROADWAY): Define. + (powerpc_opcodes): Add 750cl extended mnemonics for spr access. + +2018-07-25 H.J. Lu + Igor Tsimbalist + + * i386-gen.c (adjust_broadcast_modifier): New function. + (process_i386_opcode_modifier): Add an argument for operands. + Adjust the Broadcast value based on operands. + (output_i386_opcode): Pass operand_types to + process_i386_opcode_modifier. + (process_i386_opcodes): Pass NULL as operands to + process_i386_opcode_modifier. + * i386-opc.h (BYTE_BROADCAST): New. + (WORD_BROADCAST): Likewise. + (DWORD_BROADCAST): Likewise. + (QWORD_BROADCAST): Likewise. + (i386_opcode_modifier): Expand broadcast to 3 bits. + * i386-tbl.h: Regenerated. + +2018-07-24 Alan Modra + + PR 23430 + * or1k-desc.h: Regenerate. + +2018-07-24 Jan Beulich + + * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd, + vcvtusi2ss, and vcvtusi2sd. + * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss): + Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms. + * i386-tbl.h: Re-generate. + +2018-07-23 Claudiu Zissulescu + + * arc-opc.c (extract_w6): Fix extending the sign. + +2018-07-23 Claudiu Zissulescu + + * arc-tbl.h (vewt): Allow it for ARC EM family. + +2018-07-23 Alan Modra + + PR 23419 + * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended + opcode variants for mtspr/mfspr encodings. + +2018-07-20 Chenghua Xu + Maciej W. Rozycki + + * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and + loongson3a descriptors. + (parse_mips_ase_option): Handle -M loongson-mmi option. + (print_mips_disassembler_options): Document -M loongson-mmi. + * mips-opc.c (LMMI): New macro. + (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI + instructions. + +2018-07-19 Jan Beulich + + * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, + vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop + IgnoreSize and [XYZ]MMword where applicable. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl (vfpclasspd, vfpclassps): Fold. + (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord. + (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord. + (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ, + AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and + VPCLMULQDQ templates into their respective AVX512VL counterparts + where possible, using Disp8ShiftVL and CheckRegSize instead of + Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512DQ templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512BW templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.tbl: Fold AVX512CD templates into their respective + AVX512VL counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * i386-opc.h (DISP8_SHIFT_VL): New. + * i386-opc.tbl (Disp8ShiftVL): Define. + (various): Fold AVX512VL templates into their respective + AVX512F counterparts where possible, using Disp8ShiftVL and + CheckRegSize instead of Evex= plus Disp8MemShift= (plus often + IgnoreSize) as appropriate. + * i386-tbl.h: Re-generate. + +2018-07-19 Jan Beulich + + * Makefile.am: Change dependencies and rule for + $(srcdir)/i386-init.h. + * Makefile.in: Re-generate. + * i386-gen.c (process_i386_opcodes): New local variable + "marker". Drop opening of input file. Recognize marker and line + number directives. + * i386-opc.tbl (OPCODE_I386_H): Define. + (i386-opc.h): Include it. + (None): Undefine. + +2018-07-18 H.J. Lu + + PR gas/23418 + * i386-opc.h (Byte): Update comments. + (Word): Likewise. + (Dword): Likewise. + (Fword): Likewise. + (Qword): Likewise. + (Tbyte): Likewise. + (Xmmword): Likewise. + (Ymmword): Likewise. + (Zmmword): Likewise. + * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and + vcvttps2uqq. + * i386-tbl.h: Regenerated. + +2018-07-12 Sudakshina Das + + * aarch64-tbl.h (aarch64_opcode_table): Add entry for + ssbb and pssbb and update dsb flags to F_HAS_ALIAS. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2018-07-12 Tamar Christina + + PR binutils/23192 + * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, + mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, + umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, + sqdmulh, sqrdmulh): Use Em16. + +2018-07-11 Sudakshina Das + + * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move + csdb together with them. + (thumb32_opcodes): Likewise. + +2018-07-11 Jan Beulich + + * i386-opc.tbl (monitor, monitorx): Add 64-bit template + requiring 32-bit registers as operands 2 and 3. Improve + comments. + (mwait, mwaitx): Fold templates. Improve comments. + OPERAND_TYPE_INOUTPORTREG. + * i386-tbl.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-gen.c (operand_type_init): Remove + OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of + OPERAND_TYPE_INOUTPORTREG. + * i386-init.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-opc.tbl (wrssd, wrussd): Add Dword. + (wrssq, wrussq): Add Qword. + * i386-tbl.h: Re-generate. + +2018-07-11 Jan Beulich + + * i386-opc.h: Rename OTMax to OTNum. + (OTNumOfUints): Adjust calculation. + (OTUnused): Directly alias to OTNum. + +2018-07-09 Maciej W. Rozycki + + * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to + `reg_xys'. + (lea_reg_xys): Likewise. + (print_insn_loop_primitive): Rename `reg' local variable to + `reg_dxy'. + +2018-07-06 Tamar Christina + + PR binutils/23242 + * aarch64-tbl.h (ldarh): Fix disassembly mask. + +2018-07-06 Tamar Christina + + PR binutils/23369 + * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, + vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. + +2018-07-02 Maciej W. Rozycki + + PR tdep/8282 + * mips-dis.c (mips_option_arg_t): New enumeration. + (mips_options): New variable. + (disassembler_options_mips): New function. + (print_mips_disassembler_options): Reimplement in terms of + `disassembler_options_mips'. + * arm-dis.c (disassembler_options_arm): Adapt to using the + `disasm_options_and_args_t' structure. + * ppc-dis.c (disassembler_options_powerpc): Likewise. + * s390-dis.c (disassembler_options_s390): Likewise. + +2018-07-02 Thomas Preud'homme + + * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in + expected result. + * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. + * testsuite/ld-arm/tls-longplt-lib.d: Likewise. + * testsuite/ld-arm/tls-longplt.d: Likewise. + +2018-06-29 Tamar Christina + + PR binutils/23192 + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. + * aarch64-opc.c (operand_general_constraint_met_p, + aarch64_print_operand): Likewise. + * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, + smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, + fmlal2, fmlsl2. + (AARCH64_OPERANDS): Add Em2. + +2018-06-26 Nick Clifton + + * po/uk.po: Updated Ukranian translation. + * po/de.po: Updated German translation. + * po/pt_BR.po: Updated Brazilian Portuguese translation. + +2018-06-26 Nick Clifton + + * nfp-dis.c: Fix spelling mistake. + +2018-06-24 Nick Clifton + + * configure: Regenerate. + * po/opcodes.pot: Regenerate. + +2018-06-24 Nick Clifton + + 2.31 branch created. + +2018-06-19 Tamar Christina + + * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + +2018-06-21 Maciej W. Rozycki + + * mips-dis.c (print_mips_disassembler_options): Fix a typo in + `-M ginv' option description. + +2018-06-20 Sebastian Huber + + PR gas/23305 + * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for + la and lla. + +2018-06-19 Simon Marchi + + * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11. + * configure.ac: Remove AC_PREREQ. + * Makefile.in: Re-generate. + * aclocal.m4: Re-generate. + * configure: Re-generate. + +2018-06-14 Faraz Shahbazker + + * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and + mips64r6 descriptors. + (parse_mips_ase_option): Handle -Mginv option. + (print_mips_disassembler_options): Document -Mginv. + * mips-opc.c (decode_mips_operand) <+\>: New operand format. + (GINV): New macro. + (mips_opcodes): Define ginvi and ginvt. + +2018-06-13 Scott Egerton + Faraz Shahbazker + + * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. + * mips-opc.c (CRC, CRC64): New macros. + (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, + crc32cb, crc32ch and crc32cw for CRC. Define crc32d and + crc32cd for CRC64. + +2018-06-08 Egeyar Bagcioglu + + PR 20319 + * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV. + (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV. + +2018-06-06 Alan Modra + + * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after + setjmp. Move init for some other vars later too. + +2018-06-04 Max Filippov + + * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes. + (dis_private): Add new fields for property section tracking. + (xtensa_coalesce_insn_tables, xtensa_find_table_entry) + (xtensa_instruction_fits): New functions. + (fetch_data): Bump minimal fetch size to 4. + (print_insn_xtensa): Make struct dis_private static. + Load and prepare property table on section change. + Don't disassemble literals. Don't disassemble instructions that + cross property table boundaries. + +2018-06-01 H.J. Lu + + * configure: Regenerated. + +2018-06-01 Jan Beulich + + * i386-opc.tbl (mov, movq): Fold to/from SReg* forms. + * i386-tbl.h: Re-generate. + +2018-06-01 Jan Beulich + + * i386-opc.tbl (sldt, str): Add NoRex64. + * i386-tbl.h: Re-generate. + +2018-06-01 Jan Beulich + + * i386-opc.tbl (invpcid): Add Oword. + * i386-tbl.h: Re-generate. + +2018-06-01 Alan Modra + + * sysdep.h (_bfd_error_handler): Don't declare. + * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here. + * rl78-decode.opc: Likewise. + * msp430-decode.c: Regenerate. + * rl78-decode.c: Regenerate. + 2018-05-30 Amit Pawar * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.