X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=f8ea8653e69d38e46224332f8a1090a50823b2cf;hb=2b02b9a2abfc773ad3cce49ecc36c37a1a84bcc9;hp=a9e1356ae5751df4a226d81360c49aa57000ded0;hpb=9cf7e5687f823a1009d25cb25ff653ee8372e517;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a9e1356ae5..f8ea8653e6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,151 @@
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from AVX insns where
+	meaningless.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from GNFI insns.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
+	meaningless.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
+	meaningless.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
+	meaningless.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
+	(vpbroadcastw, rdpid): Drop NoRex64.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (vmovsd, vmovss): Fold register form load and
+	store templates, adding D.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
+	movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
+	movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
+	vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
+	vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
+	Fold load and store templates where possible, adding D. Drop
+	IgnoreSize where it was pointlessly present. Drop redundant
+	*word.
+	* i386-tbl.h: Re-generate.
+
+2018-09-13  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c (Mv_bnd, v_bndmk_mode): New.
+	(mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
+	(intel_operand_size): Handle v_bndmk_mode.
+	(OP_E_memory): Likewise. Produce (bad) when also riprel.
+
+2018-09-08  John Darrington  <john@darrington.wattle.id.au>
+
+	* disassemble.c (ARCH_s12z): Define if ARCH_all.
+
+2018-08-31  Kito Cheng  <kito@andestech.com>
+
+	* riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
+	compressed floating point instructions.
+
+2018-08-30  Kito Cheng  <kito@andestech.com>
+
+	* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
+	riscv_opcode.xlen_requirement.
+	* riscv-opc.c (riscv_opcodes): Update for struct change.
+
+2018-08-29  Martin Aberg  <maberg@gaisler.com>
+
+	* sparc-opc.c (sparc_opcodes): Add Leon specific partial write
+        psr (PWRPSR) instruction.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
+	loongson3a as an alias of gs464 for compatibility.
+	* mips-opc.c (mips_opcodes): Change Comments.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
+	option.
+	(print_mips_disassembler_options): Document -M loongson-ext.
+	* mips-opc.c (LEXT2): New macro.
+	(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
+	 descriptors.
+	 (parse_mips_ase_option): Handle -M loongson-ext option.
+	 (print_mips_disassembler_options): Document -M loongson-ext.
+	 * mips-opc.c (IL3A): Delete.
+	 * mips-opc.c (LEXT): New macro.
+	 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
+	 instructions.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
+	descriptors.
+	(parse_mips_ase_option): Handle -M loongson-cam option.
+	(print_mips_disassembler_options): Document -M loongson-cam.
+	* mips-opc.c (LCAM): New macro.
+	(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
+	instructions.
+
 2018-08-21  Alan Modra  <amodra@gmail.com>
 
 	* ppc-dis.c (operand_value_powerpc): Init "invalid".