X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Faarch64-asm.c;h=b4846bf986ee9bbc0c3b0e3b73c1cc31e861ce18;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=e3380cbee96546bc3dd9a9271a4fa3777638beed;hpb=503ba600259856b41a88b56922e094ea826df270;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e3380cbee9..b4846bf986 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1,5 +1,5 @@
 /* aarch64-asm.c -- AArch64 assembler support.
-   Copyright (C) 2012-2018 Free Software Foundation, Inc.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -78,6 +78,17 @@ insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
 
 /* Operand inserters.  */
 
+/* Insert nothing.  */
+bfd_boolean
+aarch64_ins_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
+		  const aarch64_opnd_info *info ATTRIBUTE_UNUSED,
+		  aarch64_insn *code ATTRIBUTE_UNUSED,
+		  const aarch64_inst *inst ATTRIBUTE_UNUSED,
+		  aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+  return TRUE;
+}
+
 /* Insert register number.  */
 bfd_boolean
 aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
@@ -130,6 +141,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
       switch (info->qualifier)
 	{
 	case AARCH64_OPND_QLF_S_4B:
+	case AARCH64_OPND_QLF_S_2H:
 	  /* L:H */
 	  assert (reglane_index < 4);
 	  insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
@@ -618,17 +630,6 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
   return TRUE;
 }
 
-/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!.  */
-bfd_boolean
-aarch64_ins_addr_simple_2 (const aarch64_operand *self,
-			   const aarch64_opnd_info *info, aarch64_insn *code,
-			   const aarch64_inst *inst,
-			   aarch64_operand_error *errors)
-
-{
-  return aarch64_ins_addr_simple (self, info, code, inst, errors);
-}
-
 /* Encode the address operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
 bfd_boolean
@@ -1252,8 +1253,9 @@ aarch64_ins_sve_shrimm (const aarch64_operand *self,
   const aarch64_opnd_info *prev_operand;
   unsigned int esize;
 
-  assert (info->idx > 0);
-  prev_operand = &inst->operands[info->idx - 1];
+  unsigned int opnd_backshift = get_operand_specific_data (self);
+  assert (info->idx >= (int)opnd_backshift);
+  prev_operand = &inst->operands[info->idx - opnd_backshift];
   esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
   insert_all_fields (self, code, 16 * esize - info->imm.value);
   return TRUE;
@@ -1624,6 +1626,7 @@ do_special_encoding (struct aarch64_inst *inst)
 static void
 aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
 {
+  int variant = 0;
   switch (inst->opcode->iclass)
     {
     case sve_cpy:
@@ -1634,6 +1637,8 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
     case sve_index:
     case sve_shift_pred:
     case sve_shift_unpred:
+    case sve_shift_tsz_hsd:
+    case sve_shift_tsz_bhsd:
       /* For indices and shift amounts, the variant is encoded as
 	 part of the immediate.  */
       break;
@@ -1666,10 +1671,33 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
       insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
       break;
 
+    case sve_size_bh:
     case sve_size_sd:
       insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
       break;
 
+    case sve_size_sd2:
+      insert_field (FLD_SVE_sz2, &inst->value, aarch64_get_variant (inst), 0);
+      break;
+
+    case sve_size_hsd2:
+      insert_field (FLD_SVE_size, &inst->value,
+		    aarch64_get_variant (inst) + 1, 0);
+      break;
+
+    case sve_size_tsz_bhs:
+      insert_fields (&inst->value,
+		     (1 << aarch64_get_variant (inst)),
+		     0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
+      break;
+
+    case sve_size_13:
+      variant = aarch64_get_variant (inst) + 1;
+      if (variant == 2)
+	  variant = 3;
+      insert_field (FLD_size, &inst->value, variant, 0);
+      break;
+
     default:
       break;
     }
@@ -1950,7 +1978,7 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
       break;
     }
 
-convert_to_real_return:
+ convert_to_real_return:
   aarch64_replace_opcode (inst, real);
 }
 
@@ -2082,7 +2110,7 @@ aarch64_opcode_encode (const aarch64_opcode *opcode,
     }
 
 
-encoding_exit:
+ encoding_exit:
   DEBUG_TRACE ("exit with %s", opcode->name);
 
   *code = inst->value;