X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Faarch64-opc-2.c;h=b53bb5c3370529d97c8e8ebb15116b55af1891c4;hb=b5464a6825e40e6d8ab2dd86c7ff5d65bedd64d4;hp=968e99c91cdda88b00a281fe50f1e087a8d76f8c;hpb=622b9eb1a6047bd3ad3e1a3f120cf7318ac25b57;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 968e99c91c..b53bb5c337 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -1,5 +1,5 @@
 /* This file is automatically generated by aarch64-gen.  Do not edit!  */
-/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
+/* Copyright (C) 2012-2016 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -107,11 +107,12 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PSTATE field name"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address translation operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
-  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instructin cache maintenance operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instruction cache maintenance operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
-  {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an prefetch operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
+  {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
   {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
 };
 
@@ -121,74 +122,74 @@ const struct aarch64_operand aarch64_operands[] =
 static const unsigned op_enum_table [] =
 {
   0,
-  720,
-  721,
-  722,
-  725,
-  726,
-  727,
-  728,
-  729,
-  723,
-  724,
-  730,
-  731,
-  753,
-  754,
-  755,
-  758,
-  759,
-  760,
-  761,
-  762,
-  756,
-  757,
-  763,
-  764,
-  807,
-  808,
-  809,
-  810,
+  828,
+  829,
+  830,
+  833,
+  834,
+  835,
+  836,
+  837,
+  831,
+  832,
+  838,
+  839,
+  861,
+  862,
+  863,
+  866,
+  867,
+  868,
+  869,
+  870,
+  864,
+  865,
+  871,
+  872,
+  915,
+  916,
+  917,
+  918,
   12,
-  519,
-  520,
-  1002,
-  1004,
-  1006,
-  814,
-  1005,
-  1003,
-  261,
+  627,
+  628,
+  1110,
+  1112,
+  1114,
+  922,
+  1113,
+  1111,
+  311,
+  615,
+  626,
+  625,
+  920,
+  622,
+  619,
+  611,
+  610,
+  617,
+  618,
+  621,
+  623,
+  624,
+  930,
+  643,
+  646,
+  649,
+  644,
+  647,
+  772,
+  171,
+  172,
+  173,
+  174,
   507,
-  518,
-  517,
-  812,
-  514,
-  511,
-  503,
-  502,
-  509,
-  510,
-  513,
-  515,
-  516,
-  822,
-  535,
-  538,
-  541,
-  536,
-  539,
-  664,
-  162,
-  163,
-  164,
-  165,
-  426,
-  605,
-  318,
-  320,
-  340,
-  342,
+  713,
+  380,
+  382,
+  404,
+  406,
 };
 
 /* Given the opcode enumerator OP, return the pointer to the corresponding