X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Faarch64-opc.h;h=a197df69d88c0de23fe48e7d35aa6709f58cf4ab;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=f741deac3f9a8975ad59b69e23b4c2d99491aa85;hpb=f9830ec1655e7cc2aa88c9c34a20503978d9dc88;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index f741deac3f..a197df69d8 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -1,5 +1,5 @@
 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
-   Copyright (C) 2012-2018 Free Software Foundation, Inc.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -70,6 +70,7 @@ enum aarch64_field_kind
   FLD_imm6_2,
   FLD_imm4,
   FLD_imm4_2,
+  FLD_imm4_3,
   FLD_imm5,
   FLD_imm7,
   FLD_imm8,
@@ -77,6 +78,7 @@ enum aarch64_field_kind
   FLD_imm12,
   FLD_imm14,
   FLD_imm16,
+  FLD_imm16_2,
   FLD_imm26,
   FLD_imms,
   FLD_immr,
@@ -120,6 +122,9 @@ enum aarch64_field_kind
   FLD_SVE_Zt,
   FLD_SVE_i1,
   FLD_SVE_i3h,
+  FLD_SVE_i3l,
+  FLD_SVE_i3h2,
+  FLD_SVE_i2h,
   FLD_SVE_imm3,
   FLD_SVE_imm4,
   FLD_SVE_imm5,
@@ -135,7 +140,10 @@ enum aarch64_field_kind
   FLD_SVE_prfop,
   FLD_SVE_rot1,
   FLD_SVE_rot2,
+  FLD_SVE_rot3,
   FLD_SVE_sz,
+  FLD_SVE_size,
+  FLD_SVE_sz2,
   FLD_SVE_tsz,
   FLD_SVE_tszh,
   FLD_SVE_tszl_8,
@@ -145,7 +153,8 @@ enum aarch64_field_kind
   FLD_rotate1,
   FLD_rotate2,
   FLD_rotate3,
-  FLD_SM3_imm2
+  FLD_SM3_imm2,
+  FLD_sz
 };
 
 /* Field description.  */
@@ -183,6 +192,10 @@ typedef struct aarch64_operand aarch64_operand;
 
 extern const aarch64_operand aarch64_operands[];
 
+enum err_type
+verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
+		    bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
+
 /* Operand flags.  */
 
 #define OPD_F_HAS_INSERTER	0x00000001
@@ -195,6 +208,10 @@ extern const aarch64_operand aarch64_operands[];
 #define OPD_F_OD_MASK		0x000000e0	/* Operand-dependent data.  */
 #define OPD_F_OD_LSB		5
 #define OPD_F_NO_ZR		0x00000100	/* ZR index not allowed.  */
+#define OPD_F_SHIFT_BY_4	0x00000200	/* Need to left shift the field
+						   value by 4 to get the value
+						   of an immediate operand.  */
+
 
 /* Register flags.  */
 
@@ -216,6 +233,14 @@ extern const aarch64_operand aarch64_operands[];
 #define F_REG_WRITE	(1 << 4)  /* Register can only be written to but not
 				     read from.  */
 
+/* HINT operand flags.  */
+#define HINT_OPD_F_NOPRINT	(1 << 0)  /* Should not be printed.  */
+
+/* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
+#define HINT_ENCODE(flag, val) ((flag << 8) | val)
+#define HINT_FLAG(val) (val >> 8)
+#define HINT_VAL(val) (val & 0xff)
+
 static inline bfd_boolean
 operand_has_inserter (const aarch64_operand *operand)
 {
@@ -240,6 +265,12 @@ operand_need_shift_by_two (const aarch64_operand *operand)
   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 }
 
+static inline bfd_boolean
+operand_need_shift_by_four (const aarch64_operand *operand)
+{
+  return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
+}
+
 static inline bfd_boolean
 operand_maybe_stack_pointer (const aarch64_operand *operand)
 {
@@ -455,7 +486,7 @@ enum aarch64_modifier_kind
 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 
 
-bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
+bfd_boolean aarch64_wide_constant_p (uint64_t, int, unsigned int *);
 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 int aarch64_shrink_expanded_imm8 (uint64_t);