X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Farc-ext.c;h=dc907772335f51b27a7e5637307e3d4a1c8ae7a8;hb=efb763a5ea351f9d865cbe491909f03472ebf2d6;hp=45734a083299e229b399d37f697cc88e01b94a39;hpb=b99747aeed79ad69af8b8be4d9aa3a74200fca7d;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c index 45734a0832..dc90777233 100644 --- a/opcodes/arc-ext.c +++ b/opcodes/arc-ext.c @@ -1,5 +1,5 @@ /* ARC target-dependent stuff. Extension structure access functions - Copyright (C) 1995-2016 Free Software Foundation, Inc. + Copyright (C) 1995-2020 Free Software Foundation, Inc. This file is part of libopcodes. @@ -53,16 +53,16 @@ struct ExtAuxRegister { - long address; - char* name; - struct ExtAuxRegister* next; + unsigned address; + char * name; + struct ExtAuxRegister * next; }; struct ExtCoreRegister { short number; enum ExtReadWrite rw; - char* name; + char * name; }; struct arcExtMap @@ -70,7 +70,7 @@ struct arcExtMap struct ExtAuxRegister* auxRegisters; struct ExtInstruction* instructions[INST_HASH_SIZE]; struct ExtCoreRegister coreRegisters[NUM_EXT_CORE]; - char* condCodes[NUM_EXT_COND]; + char * condCodes[NUM_EXT_COND]; }; @@ -170,6 +170,7 @@ create_map (unsigned char *block, arc_extension_map. coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name = xstrdup (name); + break; } case EXT_COND_CODE: @@ -190,8 +191,8 @@ create_map (unsigned char *block, char *aux_name = xstrdup ((char *) (p + 6)); newAuxRegister->name = aux_name; - newAuxRegister->address = (p[2] << 24) | (p[3] << 16) - | (p[4] << 8) | p[5]; + newAuxRegister->address = (((unsigned) p[2] << 24) | (p[3] << 16) + | (p[4] << 8) | p[5]); newAuxRegister->next = arc_extension_map.auxRegisters; arc_extension_map.auxRegisters = newAuxRegister; break; @@ -244,17 +245,11 @@ destroy_map (void) /* Free core registers. */ for (i = 0; i < NUM_EXT_CORE; i++) - { - if (arc_extension_map.coreRegisters[i].name) - free (arc_extension_map.coreRegisters[i].name); - } + free (arc_extension_map.coreRegisters[i].name); /* Free condition codes. */ for (i = 0; i < NUM_EXT_COND; i++) - { - if (arc_extension_map.condCodes[i]) - free (arc_extension_map.condCodes[i]); - } + free (arc_extension_map.condCodes[i]); memset (&arc_extension_map, 0, sizeof (arc_extension_map)); } @@ -279,7 +274,7 @@ ExtReadWrite_image (enum ExtReadWrite val) /* Get the name of an extension instruction. */ const extInstruction_t * -arcExtMap_insn (int opcode, int insn) +arcExtMap_insn (int opcode, unsigned long long insn) { /* Here the following tasks need to be done. First of all, the opcode stored in the Extension Map is the real opcode. However, @@ -372,7 +367,7 @@ const char * arcExtMap_coreRegName (int regnum) { if (regnum < FIRST_EXTENSION_CORE_REGISTER - || regnum > LAST_EXTENSION_CONDITION_CODE) + || regnum > LAST_EXTENSION_CORE_REGISTER) return NULL; return arc_extension_map. coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name; @@ -384,7 +379,7 @@ enum ExtReadWrite arcExtMap_coreReadWrite (int regnum) { if (regnum < FIRST_EXTENSION_CORE_REGISTER - || regnum > LAST_EXTENSION_CONDITION_CODE) + || regnum > LAST_EXTENSION_CORE_REGISTER) return REG_INVALID; return arc_extension_map. coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw; @@ -405,7 +400,7 @@ arcExtMap_condCodeName (int code) /* Get the name of an extension auxiliary register. */ const char * -arcExtMap_auxRegName (long address) +arcExtMap_auxRegName (unsigned address) { /* Walk the list of auxiliary register names and find the name. */ struct ExtAuxRegister *r; @@ -437,7 +432,7 @@ build_ARC_extmap (bfd *text_bfd) sizeof (".gnu.linkonce.arcextmap.") - 1) || !strcmp (sect->name,".arcextmap")) { - bfd_size_type count = bfd_get_section_size (sect); + bfd_size_type count = bfd_section_size (sect); unsigned char* buffer = xmalloc (count); if (buffer) @@ -462,7 +457,7 @@ dump_ARC_extmap (void) while (r) { - printf ("AUX : %s %ld\n", r->name, r->address); + printf ("AUX : %s %u\n", r->name, r->address); r = r->next; } @@ -474,12 +469,24 @@ dump_ARC_extmap (void) insn != NULL; insn = insn->next) { printf ("INST: 0x%02x 0x%02x ", insn->major, insn->minor); - if (insn->flags & ARC_SYNTAX_2OP) - printf ("SYNTAX_2OP"); - else if (insn->flags & ARC_SYNTAX_3OP) - printf ("SYNTAX_3OP"); - else - printf ("SYNTAX_UNK"); + switch (insn->flags & ARC_SYNTAX_MASK) + { + case ARC_SYNTAX_2OP: + printf ("SYNTAX_2OP"); + break; + case ARC_SYNTAX_3OP: + printf ("SYNTAX_3OP"); + break; + case ARC_SYNTAX_1OP: + printf ("SYNTAX_1OP"); + break; + case ARC_SYNTAX_NOP: + printf ("SYNTAX_NOP"); + break; + default: + printf ("SYNTAX_UNK"); + break; + } if (insn->flags & 0x10) printf ("|MODIFIER"); @@ -493,8 +500,9 @@ dump_ARC_extmap (void) struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i]; if (reg.name) - printf ("CORE: %s %d %s\n", reg.name, reg.number, - ExtReadWrite_image (reg.rw)); + printf ("CORE: 0x%04x %s %s\n", reg.number, + ExtReadWrite_image (reg.rw), + reg.name); } for (i = 0; i < NUM_EXT_COND; i++) @@ -516,7 +524,7 @@ arcExtMap_genOpcode (const extInstruction_t *einsn, int count; /* Check for the class to see how many instructions we generate. */ - switch (einsn->flags & (ARC_SYNTAX_3OP | ARC_SYNTAX_2OP)) + switch (einsn->flags & ARC_SYNTAX_MASK) { case ARC_SYNTAX_3OP: count = (einsn->modsyn & ARC_OP1_MUST_BE_IMM) ? 10 : 20; @@ -524,6 +532,12 @@ arcExtMap_genOpcode (const extInstruction_t *einsn, case ARC_SYNTAX_2OP: count = (einsn->flags & 0x10) ? 7 : 6; break; + case ARC_SYNTAX_1OP: + count = 3; + break; + case ARC_SYNTAX_NOP: + count = 1; + break; default: count = 0; break; @@ -754,6 +768,35 @@ arcExtMap_genOpcode (const extInstruction_t *einsn, INSN3OP_C0LL (einsn->major, einsn->minor), MINSN3OP_C0LL, arc_target, arg_32bit_zalimmlimm, lflags_ccf); } + else if (einsn->flags & ARC_SYNTAX_1OP) + { + if (einsn->suffix & ARC_SUFFIX_COND) + *errmsg = "Suffix SUFFIX_COND ignored"; + + INSERT_XOP (q, einsn->name, + INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor), + MINSN2OP_0C, arc_target, arg_32bit_rc, lflags_f); + + INSERT_XOP (q, einsn->name, + INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor) + | (0x01 << 22), MINSN2OP_0U, arc_target, arg_32bit_u6, + lflags_f); + + INSERT_XOP (q, einsn->name, + INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor) + | FIELDC (62), MINSN2OP_0L, arc_target, arg_32bit_limm, + lflags_f); + + } + else if (einsn->flags & ARC_SYNTAX_NOP) + { + if (einsn->suffix & ARC_SUFFIX_COND) + *errmsg = "Suffix SUFFIX_COND ignored"; + + INSERT_XOP (q, einsn->name, + INSN2OP (einsn->major, 0x3F) | FIELDB (einsn->minor) + | (0x01 << 22), MINSN2OP_0L, arc_target, arg_none, lflags_f); + } else { *errmsg = "Unknown syntax";