X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Farc-opc.c;h=b89a873c2efb336104e557bd90e2602a09e538d3;hb=20b477a75c00de06a92b9577fd74416699d2c37f;hp=231ef4b5434eaaf497d7241b4ad76c99df4922f7;hpb=2cce10e71897b8b985c786c6c323922321408b39;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 231ef4b543..b89a873c2e 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1,5 +1,5 @@ /* Opcode table for the ARC. - Copyright (C) 1994-2016 Free Software Foundation, Inc. + Copyright (C) 1994-2017 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu (claziss@synopsys.com) @@ -27,22 +27,43 @@ #include "libiberty.h" /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom - instructions. Support for this target is available when binutils is - configured and built for the 'arc*-mellanox-*-*' target. As far as - possible all ARC NPS400 features are built into all ARC target builds as + instructions. All NPS400 features are built into all ARC target builds as this reduces the chances that regressions might creep in. */ +/* Insert RA register into a 32-bit opcode, with checks. */ +static unsigned long long +insert_ra_chk (unsigned long long insn, + long long int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value == 60) + *errmsg = _("LP_COUNT register cannot be used as destination register"); + + return insn | (value & 0x3F); +} /* Insert RB register into a 32-bit opcode. */ -static unsigned -insert_rb (unsigned insn, - int value, +static unsigned long long +insert_rb (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); } -static int -extract_rb (unsigned insn ATTRIBUTE_UNUSED, +/* Insert RB register with checks. */ +static unsigned long long +insert_rb_chk (unsigned long long insn, + long long int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value == 60) + *errmsg = _("LP_COUNT register cannot be used as destination register"); + + return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); +} + +static long long int +extract_rb (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); @@ -54,33 +75,35 @@ extract_rb (unsigned insn ATTRIBUTE_UNUSED, return value; } -static unsigned -insert_rad (unsigned insn, - int value, +static unsigned long long +insert_rad (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value & 0x01) - *errmsg = _("Improper register value."); + *errmsg = _("cannot use odd number destination register"); + if (value == 60) + *errmsg = _("LP_COUNT register cannot be used as destination register"); return insn | (value & 0x3F); } -static unsigned -insert_rcd (unsigned insn, - int value, +static unsigned long long +insert_rcd (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value & 0x01) - *errmsg = _("Improper register value."); + *errmsg = _("cannot use odd number source register"); return insn | ((value & 0x3F) << 6); } /* Dummy insert ZERO operand function. */ -static unsigned -insert_za (unsigned insn, - int value, +static unsigned long long +insert_za (unsigned long long insn, + long long int value, const char **errmsg) { if (value) @@ -91,9 +114,9 @@ insert_za (unsigned insn, /* Insert Y-bit in bbit/br instructions. This function is called only when solving fixups. */ -static unsigned -insert_Ybit (unsigned insn, - int value, +static unsigned long long +insert_Ybit (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value > 0) @@ -105,9 +128,9 @@ insert_Ybit (unsigned insn, /* Insert Y-bit in bbit/br instructions. This function is called only when solving fixups. */ -static unsigned -insert_NYbit (unsigned insn, - int value, +static unsigned long long +insert_NYbit (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value < 0) @@ -118,38 +141,38 @@ insert_NYbit (unsigned insn, /* Insert H register into a 16-bit opcode. */ -static unsigned -insert_rhv1 (unsigned insn, - int value, +static unsigned long long +insert_rhv1 (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); } -static int -extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_rhv1 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { - int value = 0; + int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); return value; } /* Insert H register into a 16-bit opcode. */ -static unsigned -insert_rhv2 (unsigned insn, - int value, +static unsigned long long +insert_rhv2 (unsigned long long insn, + long long int value, const char **errmsg) { if (value == 0x1E) *errmsg = - _("Register R30 is a limm indicator for this type of instruction."); + _("Register R30 is a limm indicator"); return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); } -static int -extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_rhv2 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); @@ -157,180 +180,180 @@ extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED, return value; } -static unsigned -insert_r0 (unsigned insn, - int value, +static unsigned long long +insert_r0 (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 0) - *errmsg = _("Register must be R0."); + *errmsg = _("Register must be R0"); return insn; } -static int -extract_r0 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 0; } -static unsigned -insert_r1 (unsigned insn, - int value, +static unsigned long long +insert_r1 (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 1) - *errmsg = _("Register must be R1."); + *errmsg = _("Register must be R1"); return insn; } -static int -extract_r1 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 1; } -static unsigned -insert_r2 (unsigned insn, - int value, +static unsigned long long +insert_r2 (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 2) - *errmsg = _("Register must be R2."); + *errmsg = _("Register must be R2"); return insn; } -static int -extract_r2 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 2; } -static unsigned -insert_r3 (unsigned insn, - int value, +static unsigned long long +insert_r3 (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 3) - *errmsg = _("Register must be R3."); + *errmsg = _("Register must be R3"); return insn; } -static int -extract_r3 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 3; } -static unsigned -insert_sp (unsigned insn, - int value, +static unsigned long long +insert_sp (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 28) - *errmsg = _("Register must be SP."); + *errmsg = _("Register must be SP"); return insn; } -static int -extract_sp (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_sp (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 28; } -static unsigned -insert_gp (unsigned insn, - int value, +static unsigned long long +insert_gp (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 26) - *errmsg = _("Register must be GP."); + *errmsg = _("Register must be GP"); return insn; } -static int -extract_gp (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_gp (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 26; } -static unsigned -insert_pcl (unsigned insn, - int value, +static unsigned long long +insert_pcl (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 63) - *errmsg = _("Register must be PCL."); + *errmsg = _("Register must be PCL"); return insn; } -static int -extract_pcl (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 63; } -static unsigned -insert_blink (unsigned insn, - int value, +static unsigned long long +insert_blink (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 31) - *errmsg = _("Register must be BLINK."); + *errmsg = _("Register must be BLINK"); return insn; } -static int -extract_blink (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_blink (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 31; } -static unsigned -insert_ilink1 (unsigned insn, - int value, +static unsigned long long +insert_ilink1 (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 29) - *errmsg = _("Register must be ILINK1."); + *errmsg = _("Register must be ILINK1"); return insn; } -static int -extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 29; } -static unsigned -insert_ilink2 (unsigned insn, - int value, +static unsigned long long +insert_ilink2 (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 30) - *errmsg = _("Register must be ILINK2."); + *errmsg = _("Register must be ILINK2"); return insn; } -static int -extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return 30; } -static unsigned -insert_ras (unsigned insn, - int value, +static unsigned long long +insert_ras (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { switch (value) @@ -348,14 +371,14 @@ insert_ras (unsigned insn, insn |= (value - 8); break; default: - *errmsg = _("Register must be either r0-r3 or r12-r15."); + *errmsg = _("Register must be either r0-r3 or r12-r15"); break; } return insn; } -static int -extract_ras (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_ras (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { int value = insn & 0x07; @@ -365,9 +388,9 @@ extract_ras (unsigned insn ATTRIBUTE_UNUSED, return value; } -static unsigned -insert_rbs (unsigned insn, - int value, +static unsigned long long +insert_rbs (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { switch (value) @@ -385,14 +408,14 @@ insert_rbs (unsigned insn, insn |= ((value - 8)) << 8; break; default: - *errmsg = _("Register must be either r0-r3 or r12-r15."); + *errmsg = _("Register must be either r0-r3 or r12-r15"); break; } return insn; } -static int -extract_rbs (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_rbs (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { int value = (insn >> 8) & 0x07; @@ -402,9 +425,9 @@ extract_rbs (unsigned insn ATTRIBUTE_UNUSED, return value; } -static unsigned -insert_rcs (unsigned insn, - int value, +static unsigned long long +insert_rcs (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { switch (value) @@ -422,14 +445,14 @@ insert_rcs (unsigned insn, insn |= ((value - 8)) << 5; break; default: - *errmsg = _("Register must be either r0-r3 or r12-r15."); + *errmsg = _("Register must be either r0-r3 or r12-r15"); break; } return insn; } -static int -extract_rcs (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_rcs (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { int value = (insn >> 5) & 0x07; @@ -439,9 +462,9 @@ extract_rcs (unsigned insn ATTRIBUTE_UNUSED, return value; } -static unsigned -insert_simm3s (unsigned insn, - int value, +static unsigned long long +insert_simm3s (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { int tmp = 0; @@ -472,7 +495,7 @@ insert_simm3s (unsigned insn, tmp = 0x06; break; default: - *errmsg = _("Accepted values are from -1 to 6."); + *errmsg = _("Accepted values are from -1 to 6"); break; } @@ -480,8 +503,8 @@ insert_simm3s (unsigned insn, return insn; } -static int -extract_simm3s (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_simm3s (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { int value = (insn >> 8) & 0x07; @@ -491,42 +514,42 @@ extract_simm3s (unsigned insn ATTRIBUTE_UNUSED, return value; } -static unsigned -insert_rrange (unsigned insn, - int value, +static unsigned long long +insert_rrange (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { int reg1 = (value >> 16) & 0xFFFF; int reg2 = value & 0xFFFF; if (reg1 != 13) { - *errmsg = _("First register of the range should be r13."); + *errmsg = _("First register of the range should be r13"); return insn; } if (reg2 < 13 || reg2 > 26) { - *errmsg = _("Last register of the range doesn't fit."); + *errmsg = _("Last register of the range doesn't fit"); return insn; } insn |= ((reg2 - 12) & 0x0F) << 1; return insn; } -static int -extract_rrange (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_rrange (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return (insn >> 1) & 0x0F; } -static unsigned -insert_fpel (unsigned insn, - int value, +static unsigned long long +insert_fpel (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 27) { - *errmsg = _("Invalid register number, should be fp."); + *errmsg = _("Invalid register number, should be fp"); return insn; } @@ -534,21 +557,21 @@ insert_fpel (unsigned insn, return insn; } -static int -extract_fpel (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_fpel (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return (insn & 0x0100) ? 27 : -1; } -static unsigned -insert_blinkel (unsigned insn, - int value, +static unsigned long long +insert_blinkel (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 31) { - *errmsg = _("Invalid register number, should be blink."); + *errmsg = _("Invalid register number, should be blink"); return insn; } @@ -556,21 +579,21 @@ insert_blinkel (unsigned insn, return insn; } -static int -extract_blinkel (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_blinkel (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return (insn & 0x0200) ? 31 : -1; } -static unsigned -insert_pclel (unsigned insn, - int value, +static unsigned long long +insert_pclel (unsigned long long insn, + long long int value, const char **errmsg ATTRIBUTE_UNUSED) { if (value != 63) { - *errmsg = _("Invalid register number, should be pcl."); + *errmsg = _("Invalid register number, should be pcl"); return insn; } @@ -578,8 +601,8 @@ insert_pclel (unsigned insn, return insn; } -static int -extract_pclel (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_pclel (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { return (insn & 0x0400) ? 63 : -1; @@ -588,9 +611,9 @@ extract_pclel (unsigned insn ATTRIBUTE_UNUSED, #define INSERT_W6 /* mask = 00000000000000000000111111000000 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ -static unsigned -insert_w6 (unsigned insn ATTRIBUTE_UNUSED, - int value ATTRIBUTE_UNUSED, +static unsigned long long +insert_w6 (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) { insn |= ((value >> 0) & 0x003f) << 6; @@ -600,8 +623,8 @@ insert_w6 (unsigned insn ATTRIBUTE_UNUSED, #define EXTRACT_W6 /* mask = 00000000000000000000111111000000. */ -static int -extract_w6 (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_w6 (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { unsigned value = 0; @@ -614,9 +637,9 @@ extract_w6 (unsigned insn ATTRIBUTE_UNUSED, #define INSERT_G_S /* mask = 0000011100022000 insn = 01000ggghhhGG0HH. */ -static unsigned -insert_g_s (unsigned insn ATTRIBUTE_UNUSED, - int value ATTRIBUTE_UNUSED, +static unsigned long long +insert_g_s (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) { insn |= ((value >> 0) & 0x0007) << 8; @@ -627,8 +650,8 @@ insert_g_s (unsigned insn ATTRIBUTE_UNUSED, #define EXTRACT_G_S /* mask = 0000011100022000. */ -static int -extract_g_s (unsigned insn ATTRIBUTE_UNUSED, +static long long int +extract_g_s (unsigned long long insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) { int value = 0; @@ -644,101 +667,470 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED, } /* ARC NPS400 Support: See comment near head of file. */ -static unsigned -insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, - int value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \ +static unsigned long long \ +insert_nps_3bit_reg_at_##OFFSET##_##NAME \ + (unsigned long long insn ATTRIBUTE_UNUSED, \ + long long int value ATTRIBUTE_UNUSED, \ + const char **errmsg ATTRIBUTE_UNUSED) \ +{ \ + switch (value) \ + { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + insn |= value << (OFFSET); \ + break; \ + case 12: \ + case 13: \ + case 14: \ + case 15: \ + insn |= (value - 8) << (OFFSET); \ + break; \ + default: \ + *errmsg = _("Register must be either r0-r3 or r12-r15"); \ + break; \ + } \ + return insn; \ +} \ + \ +static long long int \ +extract_nps_3bit_reg_at_##OFFSET##_##NAME \ + (unsigned long long insn ATTRIBUTE_UNUSED, \ + bfd_boolean * invalid ATTRIBUTE_UNUSED) \ +{ \ + int value = (insn >> (OFFSET)) & 0x07; \ + if (value > 3) \ + value += 8; \ + return value; \ +} \ + +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56) + +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53) + +static unsigned long long +insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { switch (value) { - case 0: case 1: + value = 0; + break; case 2: - case 3: - insn |= value << 24; + value = 1; break; - case 12: - case 13: - case 14: - case 15: - insn |= (value - 8) << 24; + case 4: + value = 2; + break; + case 8: + value = 3; break; default: - *errmsg = _("Register must be either r0-r3 or r12-r15."); + value = 0; + *errmsg = _("Invalid size, should be 1, 2, 4, or 8"); break; } + + insn |= value << 10; return insn; } -static int -extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, - bfd_boolean * invalid ATTRIBUTE_UNUSED) +static long long int +extract_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - int value = (insn >> 24) & 0x07; - if (value > 3) - return (value + 8); - else - return value; + return 1 << ((insn >> 10) & 0x3); +} + +static unsigned long long +insert_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value >> 5) & 7) << 12; + insn |= (value & 0x1f); + return insn; } -static unsigned -insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, - int value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static long long int +extract_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); +} + +static unsigned long long +insert_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { switch (value) { - case 0: case 1: case 2: - case 3: - insn |= value << 21; - break; - case 12: - case 13: - case 14: - case 15: - insn |= (value - 8) << 21; + case 4: break; + default: - *errmsg = _("Register must be either r0-r3 or r12-r15."); - break; + *errmsg = _("invalid immediate, must be 1, 2, or 4"); + value = 0; } + + insn |= (value << 6); return insn; } -static int -extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, - bfd_boolean * invalid ATTRIBUTE_UNUSED) +static long long int +extract_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - int value = (insn >> 21) & 0x07; - if (value > 3) - return (value + 8); - else - return value; + return (insn >> 6) & 0x3f; +} + +static unsigned long long +insert_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); + return insn; } -static unsigned -insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED, - int value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static long long int +extract_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - if (value < 1 || value > 32) + return (insn & 0x1f); +} + +static unsigned long long +insert_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + int top = (value >> 16) & 0xffff; + if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE) + *errmsg = _("invalid value for CMEM ld/st immediate"); + insn |= (value & 0xffff); + return insn; +} + +static long long int +extract_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff); +} + +#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \ +static unsigned long long \ +insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \ + long long int value ATTRIBUTE_UNUSED, \ + const char **errmsg ATTRIBUTE_UNUSED) \ +{ \ + switch (value) \ + { \ + case 0: \ + case 8: \ + case 16: \ + case 24: \ + value = value / 8; \ + break; \ + default: \ + *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \ + value = 0; \ + } \ + insn |= (value << SHIFT); \ + return insn; \ +} \ + \ +static long long int \ +extract_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \ + bfd_boolean * invalid ATTRIBUTE_UNUSED) \ +{ \ + return ((insn >> SHIFT) & 0x3) * 8; \ +} + +MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12) +MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10) + +#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\ +static unsigned long long \ +insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ + long long int value ATTRIBUTE_UNUSED, \ + const char **errmsg ATTRIBUTE_UNUSED) \ + { \ + if (value < LOWER || value > UPPER) \ + { \ + *errmsg = _("Invalid size, value must be " \ + #LOWER " to " #UPPER "."); \ + return insn; \ + } \ + value -= BIAS; \ + insn |= (value << SHIFT); \ + return insn; \ + } \ + \ +static long long int \ +extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ + bfd_boolean * invalid ATTRIBUTE_UNUSED) \ +{ \ + return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \ +} + +MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0) + +static long long int +extract_nps_qcmp_m3 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int m3 = (insn >> 5) & 0xf; + if (m3 == 0xf) + *invalid = TRUE; + return m3; +} + +static long long int +extract_nps_qcmp_m2 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + bfd_boolean tmp_invalid = FALSE; + int m2 = (insn >> 15) & 0x1; + int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); + + if (m2 == 0 && m3 == 0xf) + *invalid = TRUE; + return m2; +} + +static long long int +extract_nps_qcmp_m1 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + bfd_boolean tmp_invalid = FALSE; + int m1 = (insn >> 14) & 0x1; + int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid); + int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); + + if (m1 == 0 && m2 == 0 && m3 == 0xf) + *invalid = TRUE; + return m1; +} + +static unsigned long long +insert_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + unsigned pwr; + + if (value < 1 || value > 256) { - *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive."); - return insn; + *errmsg = _("value out of range 1 - 256"); + return 0; } - --value; - insn |= ((value & 0x1f) << 10); - return insn; + for (pwr = 0; (value & 1) == 0; value >>= 1) + ++pwr; + + if (value != 1) + { + *errmsg = _("value must be power of 2"); + return 0; + } + + return insn | (pwr << 8); +} + +static long long int +extract_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned entry_size = (insn >> 8) & 0xf; + return 1 << entry_size; +} + +static unsigned long long +insert_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47); +} + +static long long int +extract_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1); +} + +static unsigned long long +insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (value << 42) | (value << 37); +} + +static long long int +extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f)) + *invalid = TRUE; + return ((insn >> 37) & 0x1f); +} + +static unsigned long long +insert_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value < 0 || value > 28) + *errmsg = _("Value must be in the range 0 to 28"); + return insn | (value << 20); +} + +static long long int +extract_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 20) & 0x1f; + if (value > 28) + *invalid = TRUE; + return value; } -static int -extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED, - bfd_boolean * invalid ATTRIBUTE_UNUSED) +#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \ +static unsigned long long \ +insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ + long long int value ATTRIBUTE_UNUSED, \ + const char **errmsg ATTRIBUTE_UNUSED) \ +{ \ + if (value < 1 || value > UPPER) \ + *errmsg = _("Value must be in the range 1 to " #UPPER); \ + if (value == UPPER) \ + value = 0; \ + return insn | (value << SHIFT); \ +} \ + \ +static long long int \ +extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ + bfd_boolean * invalid ATTRIBUTE_UNUSED) \ +{ \ + int value = (insn >> SHIFT) & ((1 << BITS) - 1); \ + if (value == 0) \ + value = UPPER; \ + return value; \ +} + +MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6) + +static unsigned long long +insert_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value < 0 || value > 240) + *errmsg = _("Value must be in the range 0 to 240"); + if ((value % 16) != 0) + *errmsg = _("Value must be a multiple of 16"); + value = value / 16; + return insn | (value << 6); +} + +static long long int +extract_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - return ((insn >> 10) & 0x1f) + 1; + int value = (insn >> 6) & 0xF; + return value * 16; +} + +#define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \ +static unsigned long long \ +insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ + long long int value ATTRIBUTE_UNUSED, \ + const char **errmsg ATTRIBUTE_UNUSED) \ +{ \ + if (value != ARC_NPS400_ADDRTYPE_##VALUE) \ + *errmsg = _("Invalid address type for operand"); \ + return insn; \ +} \ + \ +static long long int \ +extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ + bfd_boolean * invalid ATTRIBUTE_UNUSED) \ +{ \ + return ARC_NPS400_ADDRTYPE_##VALUE; \ +} + +MAKE_INSERT_NPS_ADDRTYPE (bd, BD) +MAKE_INSERT_NPS_ADDRTYPE (jid, JID) +MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD) +MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD) +MAKE_INSERT_NPS_ADDRTYPE (sd, SD) +MAKE_INSERT_NPS_ADDRTYPE (sm, SM) +MAKE_INSERT_NPS_ADDRTYPE (xa, XA) +MAKE_INSERT_NPS_ADDRTYPE (xd, XD) +MAKE_INSERT_NPS_ADDRTYPE (cd, CD) +MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD) +MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID) +MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD) +MAKE_INSERT_NPS_ADDRTYPE (cm, CM) +MAKE_INSERT_NPS_ADDRTYPE (csd, CSD) +MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA) +MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD) + +static unsigned long long +insert_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value < 0 || value > 31) + *errmsg = _("Value must be in the range 0 to 31"); + return insn | (value << 43) | (value << 48); +} + + +static long long int +extract_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value1 = (insn >> 43) & 0x1F; + int value2 = (insn >> 48) & 0x1F; + + if (value1 != value2) + *invalid = TRUE; + + return value1; } /* Include the generic extract/insert functions. Order is important @@ -822,9 +1214,13 @@ const struct arc_flag_operand arc_flag_operands[] = { "d", 1, 1, 5, 1 }, #define F_DFAKE (F_D + 1) { "d", 0, 0, 0, 1 }, +#define F_DNZ_ND (F_DFAKE + 1) + { "nd", 0, 1, 16, 0 }, +#define F_DNZ_D (F_DNZ_ND + 1) + { "d", 1, 1, 16, 1 }, /* Data size. */ -#define F_SIZEB1 (F_DFAKE + 1) +#define F_SIZEB1 (F_DNZ_D + 1) { "b", 1, 2, 1, 1 }, #define F_SIZEB7 (F_SIZEB1 + 1) { "b", 1, 2, 7, 1 }, @@ -878,7 +1274,9 @@ const struct arc_flag_operand arc_flag_operands[] = { "di", 1, 1, 5, 1 }, #define F_DI11 (F_DI5 + 1) { "di", 1, 1, 11, 1 }, -#define F_DI15 (F_DI11 + 1) +#define F_DI14 (F_DI11 + 1) + { "di", 1, 1, 14, 1 }, +#define F_DI15 (F_DI14 + 1) { "di", 1, 1, 15, 1 }, /* ARCv2 specific. */ @@ -903,6 +1301,90 @@ const struct arc_flag_operand arc_flag_operands[] = #define F_NPS_FLAG (F_NPS_CL + 1) { "f", 1, 1, 20, 1 }, + +#define F_NPS_R (F_NPS_FLAG + 1) + { "r", 1, 1, 15, 1 }, + +#define F_NPS_RW (F_NPS_R + 1) + { "rw", 0, 1, 7, 1 }, + +#define F_NPS_RD (F_NPS_RW + 1) + { "rd", 1, 1, 7, 1 }, + +#define F_NPS_WFT (F_NPS_RD + 1) + { "wft", 0, 0, 0, 1 }, + +#define F_NPS_IE1 (F_NPS_WFT + 1) + { "ie1", 1, 2, 8, 1 }, + +#define F_NPS_IE2 (F_NPS_IE1 + 1) + { "ie2", 2, 2, 8, 1 }, + +#define F_NPS_IE12 (F_NPS_IE2 + 1) + { "ie12", 3, 2, 8, 1 }, + +#define F_NPS_SYNC_RD (F_NPS_IE12 + 1) + { "rd", 0, 1, 6, 1 }, + +#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1) + { "wr", 1, 1, 6, 1 }, + +#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1) + { "off", 0, 0, 0, 1 }, + +#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1) + { "restore", 0, 0, 0, 1 }, + +#define F_NPS_SX (F_NPS_HWS_RESTORE + 1) + { "sx", 1, 1, 14, 1 }, + +#define F_NPS_AR (F_NPS_SX + 1) + { "ar", 0, 1, 0, 1 }, + +#define F_NPS_AL (F_NPS_AR + 1) + { "al", 1, 1, 0, 1 }, + +#define F_NPS_S (F_NPS_AL + 1) + { "s", 0, 0, 0, 1 }, + +#define F_NPS_ZNCV_RD (F_NPS_S + 1) + { "rd", 0, 1, 15, 1 }, + +#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1) + { "wr", 1, 1, 15, 1 }, + +#define F_NPS_P0 (F_NPS_ZNCV_WR + 1) + { "p0", 0, 0, 0, 1 }, + +#define F_NPS_P1 (F_NPS_P0 + 1) + { "p1", 0, 0, 0, 1 }, + +#define F_NPS_P2 (F_NPS_P1 + 1) + { "p2", 0, 0, 0, 1 }, + +#define F_NPS_P3 (F_NPS_P2 + 1) + { "p3", 0, 0, 0, 1 }, + +#define F_NPS_LDBIT_DI (F_NPS_P3 + 1) + { "di", 0, 0, 0, 1 }, + +#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1) + { "cl", 1, 1, 6, 1 }, + +#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1) + { "cl", 1, 1, 16, 1 }, + +#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1) + { "x2", 1, 2, 9, 1 }, + +#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1) + { "x2", 1, 2, 22, 1 }, + +#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1) + { "x4", 2, 2, 9, 1 }, + +#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1) + { "x4", 2, 2, 22, 1 }, }; const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); @@ -917,12 +1399,13 @@ const struct arc_flag_class arc_flag_classes[] = { F_CLASS_NONE, { F_NULL } }, #define C_CC (C_EMPTY + 1) - { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, - F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, - F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, - F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, - F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, + { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, + F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, + F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, + F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, #define C_AA_ADDR3 (C_CC + 1) #define C_AA27 (C_CC + 1) @@ -943,13 +1426,17 @@ const struct arc_flag_class arc_flag_classes[] = { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, #define C_D (C_T + 1) { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } }, +#define C_DNZ_D (C_D + 1) + { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } }, -#define C_DHARD (C_D + 1) +#define C_DHARD (C_DNZ_D + 1) { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } }, #define C_DI20 (C_DHARD + 1) { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, -#define C_DI16 (C_DI20 + 1) +#define C_DI14 (C_DI20 + 1) + { F_CLASS_OPTIONAL, { F_DI14, F_NULL }}, +#define C_DI16 (C_DI14 + 1) { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, #define C_DI26 (C_DI16 + 1) { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, @@ -981,8 +1468,73 @@ const struct arc_flag_class arc_flag_classes[] = #define C_NPS_F (C_NPS_CL + 1) { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, + +#define C_NPS_R (C_NPS_F + 1) + { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}}, + +#define C_NPS_SCHD_RW (C_NPS_R + 1) + { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}}, + +#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1) + { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}}, + +#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1) + { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}}, + +#define C_NPS_SYNC (C_NPS_SCHD_IE + 1) + { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}}, + +#define C_NPS_HWS_OFF (C_NPS_SYNC + 1) + { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}}, + +#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1) + { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}}, + +#define C_NPS_SX (C_NPS_HWS_RESTORE + 1) + { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}}, + +#define C_NPS_AR_AL (C_NPS_SX + 1) + { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}}, + +#define C_NPS_S (C_NPS_AR_AL + 1) + { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}}, + +#define C_NPS_ZNCV (C_NPS_S + 1) + { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}}, + +#define C_NPS_P0 (C_NPS_ZNCV + 1) + { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }}, + +#define C_NPS_P1 (C_NPS_P0 + 1) + { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }}, + +#define C_NPS_P2 (C_NPS_P1 + 1) + { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }}, + +#define C_NPS_P3 (C_NPS_P2 + 1) + { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }}, + +#define C_NPS_LDBIT_DI (C_NPS_P3 + 1) + { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }}, + +#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }}, + +#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }}, + +#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }}, + +#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }}, }; +const unsigned char flags_none[] = { 0 }; +const unsigned char flags_f[] = { C_F }; +const unsigned char flags_cc[] = { C_CC }; +const unsigned char flags_ccf[] = { C_CC, C_F }; + /* The operands table. The format of the operands table is: @@ -994,13 +1546,21 @@ const struct arc_operand arc_operands[] = index is used to indicate end-of-list. */ #define UNUSED 0 { 0, 0, 0, 0, 0, 0 }, + +#define IGNORED (UNUSED + 1) + { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 }, + /* The plain integer register fields. Used by 32 bit instructions. */ -#define RA (UNUSED + 1) +#define RA (IGNORED + 1) { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, -#define RB (RA + 1) +#define RA_CHK (RA + 1) + { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 }, +#define RB (RA_CHK + 1) { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, -#define RC (RB + 1) +#define RB_CHK (RB + 1) + { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb }, +#define RC (RB_CHK + 1) { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, #define RBdup (RC + 1) { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, @@ -1054,11 +1614,11 @@ const struct arc_operand arc_operands[] = #define R3 (R2 + 1) #define R3_S (R2 + 1) { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, -#define SP (R3 + 1) +#define RSP (R3 + 1) #define SP_S (R3 + 1) { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, -#define SPdup (SP + 1) -#define SP_Sdup (SP + 1) +#define SPdup (RSP + 1) +#define SP_Sdup (RSP + 1) { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, #define GP (SPdup + 1) #define GP_S (SPdup + 1) @@ -1302,13 +1862,13 @@ const struct arc_operand arc_operands[] = /* ARC NPS400 Support: See comment near head of file. */ #define NPS_R_DST_3B (UIMM6_5_S + 1) - { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, + { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1) - { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, + { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1) - { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 }, + { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 }, #define NPS_R_DST (NPS_R_SRC2_3B + 1) { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL }, @@ -1323,30 +1883,376 @@ const struct arc_operand arc_operands[] = { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) - { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size }, + { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size }, -#define NPS_UIMM16 (NPS_BITOP_SIZE + 1) +#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1) + { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size }, + +#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b }, + +#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1) + { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 }, + +#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1) { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, -}; +#define NPS_SIMM16 (NPS_UIMM16 + 1) + { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL }, + +#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1) + { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 }, + +#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1) + { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 }, + +#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos }, + +#define NPS_SRC1_POS (NPS_SRC2_POS + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos }, + +#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size }, + +#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size }, + +#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size }, + +#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size }, + +#define NPS_R_XLDST (NPS_WXORB_SIZE + 1) + { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL }, + +#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1) + { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size }, + +#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1) + { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 }, + +#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1) + { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 }, + +#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1) + { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 }, + +#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size }, + +#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1) + { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, + +#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1) + { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, + +#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1) + { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 }, + +#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1) + { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size }, + +#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1) + { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size }, + +#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1) + { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 }, + +#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1) + { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1) + { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1) + { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1) + { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1) + { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1) + { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1) + { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1) + { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1) + { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4 }, + +#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1) + { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1) + { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1) + { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1) + { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext }, + +#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1) + { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1) + { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size }, + +#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1) + { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor }, + +#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1) + { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble }, + +#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1) + { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1) + { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len }, + +#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1) + { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs }, + +#define NPS_PSBC (NPS_MIN_HOFS + 1) + { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_DPI_DST (NPS_PSBC + 1) + { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL }, + + /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */ +#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1) + { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, + +#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1) + { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width }, + +#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1) + { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1) + { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1) + { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1) + { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len }, + +#define NPS_HASH_OFS (NPS_HASH_LEN + 1) + { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1) + { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1) + { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1) + { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1) + { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1) + { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 }, + +#define COLON (NPS_E4BY_INDEX3 + 1) + { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL }, + +#define NPS_BD (COLON + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd }, + +#define NPS_JID (NPS_BD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid }, + +#define NPS_LBD (NPS_JID + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd }, + +#define NPS_MBD (NPS_LBD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd }, + +#define NPS_SD (NPS_MBD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd }, + +#define NPS_SM (NPS_SD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm }, + +#define NPS_XA (NPS_SM + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa }, + +#define NPS_XD (NPS_XA + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd }, + +#define NPS_CD (NPS_XD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd }, + +#define NPS_CBD (NPS_CD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd }, + +#define NPS_CJID (NPS_CBD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid }, + +#define NPS_CLBD (NPS_CJID + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd }, + +#define NPS_CM (NPS_CLBD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm }, + +#define NPS_CSD (NPS_CM + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd }, + +#define NPS_CXA (NPS_CSD + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa }, + +#define NPS_CXD (NPS_CXA + 1) + { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd }, + +#define NPS_BD_TYPE (NPS_CXD + 1) + { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_BMU_NUM (NPS_BD_TYPE + 1) + { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff }, + +#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1) + { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1) + { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job }, + +#define NPS_R_DST_3B_48 (NPS_PMU_NUM_JOB + 1) + { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, + +#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1) + { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, + +#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1) + { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 }, + +#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1) + { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, + +#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1) + { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, + +#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1) + { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 }, + +#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1) + { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL }, + +#define NPS_RB_64 (NPS_RA_64 + 1) + { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL }, + +#define NPS_RBdup_64 (NPS_RB_64 + 1) + { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, + +#define NPS_RBdouble_64 (NPS_RBdup_64 + 1) + { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64 }, + +#define NPS_RC_64 (NPS_RBdouble_64 + 1) + { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL }, + +#define NPS_UIMM16_0_64 (NPS_RC_64 + 1) + { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, + +#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1) + { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size } +}; const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); const unsigned arc_Toperand = FKT_T; const unsigned arc_NToperand = FKT_NT; +const unsigned char arg_none[] = { 0 }; +const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC }; +const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC }; +const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC }; +const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 }; +const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 }; +const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 }; +const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 }; +const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC }; +const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM }; +const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC }; +const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM }; + +const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM }; +const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 }; +const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 }; + +const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 }; +const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup }; +const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup }; + +const unsigned char arg_32bit_rbrc[] = { RB, RC }; +const unsigned char arg_32bit_zarc[] = { ZA, RC }; +const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 }; +const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 }; +const unsigned char arg_32bit_rblimm[] = { RB, LIMM }; +const unsigned char arg_32bit_zalimm[] = { ZA, LIMM }; + +const unsigned char arg_32bit_limmrc[] = { LIMM, RC }; +const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 }; +const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 }; +const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup }; + +const unsigned char arg_32bit_rc[] = { RC }; +const unsigned char arg_32bit_u6[] = { UIMM6_20 }; +const unsigned char arg_32bit_limm[] = { LIMM }; + /* The opcode table. The format of the opcode table is: - NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. */ + NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. + + The table is organised such that, where possible, all instructions with + the same mnemonic are together in a block. When the assembler searches + for a suitable instruction the entries are checked in table order, so + more specific, or specialised cases should appear earlier in the table. + + As an example, consider two instructions 'add a,b,u6' and 'add + a,b,limm'. The first takes a 6-bit immediate that is encoded within the + 32-bit instruction, while the second takes a 32-bit immediate that is + encoded in a follow-on 32-bit, making the total instruction length + 64-bits. In this case the u6 variant must appear first in the table, as + all u6 immediates could also be encoded using the 'limm' extension, + however, we want to use the shorter instruction wherever possible. + + It is possible though to split instructions with the same mnemonic into + multiple groups. However, the instructions are still checked in table + order, even across groups. The only time that instructions with the + same mnemonic should be split into different groups is when different + variants of the instruction appear in different architectures, in which + case, grouping all instructions from a particular architecture together + might be preferable to merging the instruction into the main instruction + table. + + An example of this split instruction groups can be found with the 'sync' + instruction. The core arc architecture provides a 'sync' instruction, + while the nps instruction set extension provides 'sync.rd' and + 'sync.wr'. The rd/wr flags are instruction flags, not part of the + mnemonic, so we end up with two groups for the sync instruction, the + first within the core arc instruction table, and the second within the + nps extension instructions. */ const struct arc_opcode arc_opcodes[] = { #include "arc-tbl.h" #include "arc-nps400-tbl.h" #include "arc-ext-tbl.h" -}; -const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes); + { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } +}; /* List with special cases instructions and the applicable flags. */ const struct arc_flag_special arc_flag_special_cases[] = @@ -1496,8 +2402,8 @@ const unsigned arc_num_pseudo_insn = const struct arc_aux_reg arc_aux_regs[] = { #undef DEF -#define DEF(ADDR, NAME) \ - { ADDR, #NAME, sizeof (#NAME)-1 }, +#define DEF(ADDR, CPU, SUBCLASS, NAME) \ + { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, #include "arc-regs.h" @@ -1631,3 +2537,20 @@ const struct arc_opcode arc_relax_opcodes[] = }; const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes); + +/* Return length of an opcode in bytes. */ + +int +arc_opcode_len (const struct arc_opcode *opcode) +{ + if (opcode->mask < 0x10000ull) + return 2; + + if (opcode->mask < 0x100000000ull) + return 4; + + if (opcode->mask < 0x1000000000000ull) + return 6; + + return 8; +}