X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Farm-dis.c;h=0b1ed1abc4afc224219dc3a053c036dfd382b928;hb=8f250eb133241435bf70b2dbc4f620173f8067ea;hp=aedc9f2278f5d9ec6c4ace503f188d219d4880a2;hpb=4ce8808b2c5fa1b487af90a65e915995c6a76715;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index aedc9f2278..0b1ed1abc4 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1,6 +1,7 @@ /* Instruction printing code for the ARM - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 - 2007, Free Software Foundation, Inc. + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012 + Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) @@ -45,17 +46,43 @@ #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) #endif +/* Cached mapping symbol state. */ +enum map_type +{ + MAP_ARM, + MAP_THUMB, + MAP_DATA +}; + +struct arm_private_data +{ + /* The features to use when disassembling optional instructions. */ + arm_feature_set features; + + /* Whether any mapping symbols are present in the provided symbol + table. -1 if we do not know yet, otherwise 0 or 1. */ + int has_mapping_symbols; + + /* Track the last type (although this doesn't seem to be useful) */ + enum map_type last_type; + + /* Tracking symbol table information */ + int last_mapping_sym; + bfd_vma last_mapping_addr; +}; + struct opcode32 { unsigned long arch; /* Architecture defining this insn. */ - unsigned long value, mask; /* Recognise insn if (op&mask)==value. */ - const char *assembler; /* How to disassemble this insn. */ + unsigned long value; /* If arch == 0 then value is a sentinel. */ + unsigned long mask; /* Recognise insn if (op & mask) == value. */ + const char * assembler; /* How to disassemble this insn. */ }; struct opcode16 { unsigned long arch; /* Architecture defining this insn. */ - unsigned short value, mask; /* Recognise insn if (op&mask)==value. */ + unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ const char *assembler; /* How to disassemble this insn. */ }; @@ -65,17 +92,20 @@ struct opcode16 %c print condition code (always bits 28-31 in ARM mode) %q print shifter argument - %u print condition code (unconditional in ARM mode) + %u print condition code (unconditional in ARM mode, + UNPREDICTABLE if not AL in Thumb) %A print address for ldc/stc/ldf/stf instruction %B print vstm/vldm register list - %C print vstr/vldr address operand %I print cirrus signed shift immediate: bits 0..3|4..6 %F print the COUNT field of a LFM/SFM instruction. %P print floating point precision in arithmetic insn %Q print floating point precision in ldf/stf insn %R print floating point rounding mode + %c print as a condition code (for vsel) %r print as an ARM register + %R as %<>r but r15 is UNPREDICTABLE + %ru as %<>r but each u register must be unique. %d print the bitfield in decimal %k print immediate for VFPv3 conversion instruction %x print the bitfield in hex @@ -103,8 +133,17 @@ struct opcode16 versions. %i print 5-bit immediate in bits 8,3..0 (print "32" when 0) - %r print register offset address for wldt/wstr instruction -*/ + %r print register offset address for wldt/wstr instruction. */ + +enum opcode_sentinel_enum +{ + SENTINEL_IWMMXT_START = 1, + SENTINEL_IWMMXT_END, + SENTINEL_GENERIC_START +} opcode_sentinels; + +#define UNDEFINED_INSTRUCTION "\t\t; instruction: %0-31x" +#define UNPREDICTABLE_INSTRUCTION "\t; " /* Common coprocessor opcodes shared between Arm and Thumb-2. */ @@ -116,10 +155,9 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, - + /* Intel Wireless MMX technology instructions. */ -#define FIRST_IWMMXT_INSN 0x0e130130 -#define IWMMXT_INSN_COUNT 73 + { 0, SENTINEL_IWMMXT_START, 0, "" }, {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, @@ -134,11 +172,11 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, - {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, @@ -195,8 +233,9 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, + { 0, SENTINEL_IWMMXT_END, 0, "" }, - /* Floating point coprocessor (FPA) instructions */ + /* Floating point coprocessor (FPA) instructions. */ {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, @@ -241,15 +280,15 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, - /* Register load/store */ + /* Register load/store. */ {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, @@ -264,7 +303,7 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, - /* Data transfer between ARM and NEON registers */ + /* Data transfer between ARM and NEON registers. */ {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, @@ -280,10 +319,12 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, /* Half-precision conversion instructions. */ - {FPU_NEON_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, - {FPU_NEON_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, + {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, + {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, - /* Floating point coprocessor (VFP) instructions */ + /* Floating point coprocessor (VFP) instructions. */ {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, @@ -321,14 +362,14 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, + {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, - {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, + {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, - {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"}, + {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"}, {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"}, {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, @@ -438,24 +479,50 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, - /* Generic coprocessor instructions */ - {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + /* VFP Fused multiply add instructions. */ + {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, + + /* FP v5. */ + {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, + {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, + + /* Generic coprocessor instructions. */ + { 0, SENTINEL_GENERIC_START, 0, "" }, + {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, + {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, - /* V6 coprocessor instructions */ - {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + /* V6 coprocessor instructions. */ + {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, - /* V5 coprocessor instructions */ + /* V5 coprocessor instructions. */ {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, {0, 0, 0, 0} @@ -470,6 +537,8 @@ static const struct opcode32 coprocessor_opcodes[] = %% % %c print condition code + %u print condition code (unconditional in ARM mode, + UNPREDICTABLE if not AL in Thumb) %A print v{st,ld}[1234] operands %B print v{st,ld}[1234] any one operands %C print v{st,ld}[1234] single->all operands @@ -489,28 +558,41 @@ static const struct opcode32 coprocessor_opcodes[] = %'c print specified char iff bitfield is all ones %`c print specified char iff bitfield is all zeroes - %?ab... select from array of values in big endian order */ + %?ab... select from array of values in big endian order. */ static const struct opcode32 neon_opcodes[] = { - /* Extract */ + /* Extract. */ {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, - /* Move data element to all lanes */ + /* Move data element to all lanes. */ {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, - /* Table lookup */ + /* Table lookup. */ {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, /* Half-precision conversions. */ - {FPU_NEON_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, - - /* Two registers, miscellaneous */ + {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, + {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, + + /* NEON fused multiply add instructions. */ + {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + + /* Two registers, miscellaneous. */ + {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, @@ -545,7 +627,16 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, - /* Three registers of the same length */ + /* Three registers of the same length. */ + {FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, @@ -600,7 +691,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - /* One register and an immediate value */ + /* One register and an immediate value. */ {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, @@ -615,7 +706,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, - /* Two registers and a shift amount */ + /* Two registers and a shift amount. */ {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, @@ -675,7 +766,8 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, - /* Three registers of different lengths */ + /* Three registers of different lengths. */ + {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, @@ -694,7 +786,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - /* Two registers and a scalar */ + /* Two registers and a scalar. */ {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, @@ -718,7 +810,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - /* Element and structure load/store */ + /* Element and structure load/store. */ {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, @@ -752,6 +844,7 @@ static const struct opcode32 neon_opcodes[] = %a print address for ldr/str instruction %s print address for ldr/str halfword/signextend instruction + %S like %s but allow UNPREDICTABLE addressing %b print branch destination %c print condition code (always bits 28-31) %m print register mask for ldm/stm instruction @@ -764,6 +857,10 @@ static const struct opcode32 neon_opcodes[] = %P print address for pli instruction. %r print as an ARM register + %T print as an ARM register + 1 + %R as %r but r15 is UNPREDICTABLE + %{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE + %{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE %d print the bitfield in decimal %W print the bitfield plus one in decimal %x print the bitfield in hex @@ -775,48 +872,90 @@ static const struct opcode32 neon_opcodes[] = %e print arm SMI operand (bits 0..7,8..19). %E print the LSB and WIDTH fields of a BFI or BFC instruction. - %V print the 16-bit immediate field of a MOVT or MOVW instruction. */ + %V print the 16-bit immediate field of a MOVT or MOVW instruction. + %R print the SPSR/CPSR or banked register of an MRS. */ static const struct opcode32 arm_opcodes[] = { /* ARM instructions. */ - {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, + {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, + {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + + /* V8 instructions. */ + {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"}, + {ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_EXT_V8, 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, + {ARM_EXT_V8, 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, + {ARM_EXT_V8, 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, + {ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + /* CRC32 instructions. */ + {CRC_EXT_ARMV8, 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, + {CRC_EXT_ARMV8, 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, + + /* Virtualization Extension instructions. */ + {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"}, + {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, + + /* Integer Divide Extension instructions. */ + {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, + + /* MP Extension instructions. */ + {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"}, /* V7 instructions. */ {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, + {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"}, + {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"}, {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, /* ARM V6T2 instructions. */ - {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, - {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, - {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"}, - {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"}, - {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, - {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, - {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, + {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, + {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6T2, 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, + + {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, + {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, + + {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, + {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, + {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, - /* ARM V6Z instructions. */ - {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, + /* ARM Security extension instructions. */ + {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, /* ARM V6K instructions. */ {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, - {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"}, + {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, + {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, + {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, + {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, /* ARM V6K NOP hints. */ {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, @@ -825,214 +964,314 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, - /* ARM V6 instructions. */ + /* ARM V6 instructions. */ {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"}, - {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, - {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, + {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, + {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, - {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"}, - {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, - {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, - {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, - {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, + {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, - {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"}, + {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, + {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, - {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"}, - {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, + {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, + {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, + {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, /* V5J instruction. */ - {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, + {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, /* V5 Instructions. */ {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, - {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, - {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, + {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, + {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, /* V5E "El Segundo" Instructions. */ {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, - {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, - {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, - {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, - {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, + {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, /* ARM Instructions. */ - {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"}, - {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"}, - {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, - {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, - {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, + + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, + + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, + {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, + + {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, + {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, + {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, + {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, + + {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, + {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, + {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, + + {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, + {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, - {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"}, - {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"}, - {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"}, + {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, + {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, + {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, - {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"}, - {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"}, - {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, - {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"}, + {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, + + {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, + {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, + {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, + + {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, - {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"}, + + {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, + + {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, + + {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, - {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + + {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, - {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, /* The rest. */ - {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"}, + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, {0, 0x00000000, 0x00000000, 0} }; @@ -1052,6 +1291,7 @@ static const struct opcode32 arm_opcodes[] = %x print warning if conditional an not at end of IT block" %X print "\t; unpredictable " if conditional %I print IT instruction suffix and operands + %W print Thumb Writeback indicator for LDMIA %r print bitfield as an ARM register %d print bitfield as a decimal %H print (bitfield * 2) as a decimal @@ -1066,6 +1306,10 @@ static const struct opcode16 thumb_opcodes[] = { /* Thumb instructions. */ + /* ARM V8 instructions. */ + {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"}, + {ARM_EXT_V8, 0xba80, 0xffc0, "hlt\t%0-5x"}, + /* ARM V6K no-argument instructions. */ {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, @@ -1097,7 +1341,7 @@ static const struct opcode16 thumb_opcodes[] = /* This is BLX(2). BLX(1) is a 32-bit instruction. */ {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ - {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"}, + {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, /* Format 4. */ {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, @@ -1139,6 +1383,7 @@ static const struct opcode16 thumb_opcodes[] = {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 1 */ + {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, @@ -1148,7 +1393,7 @@ static const struct opcode16 thumb_opcodes[] = {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, /* format 6 */ - {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=" */ + {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=" */ /* format 9 */ {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, @@ -1161,15 +1406,15 @@ static const struct opcode16 thumb_opcodes[] = {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, /* format 12 */ - {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"}, + {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, /* format 15 */ {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, - {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"}, + {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, /* format 17 */ {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, /* format 16 */ - {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"}, + {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, /* format 18 */ {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, @@ -1178,7 +1423,7 @@ static const struct opcode16 thumb_opcodes[] = 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs are processed via that table. Thus, we can never encounter a bare "second half of BL/BLX(1)" instruction here. */ - {ARM_EXT_V1, 0x0000, 0x0000, "undefined"}, + {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, {0, 0, 0, 0} }; @@ -1194,8 +1439,10 @@ static const struct opcode16 thumb_opcodes[] = %M print a modified 12-bit immediate (same location) %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] + %H print a 16-bit immediate from hw2[3:0],hw1[11:0] %S print a possibly-shifted Rm + %L print address for a ldrd/strd instruction %a print the address of a plain load/store %w print the width and signedness of a core load/store %m print register mask for ldm/stm @@ -1215,6 +1462,8 @@ static const struct opcode16 thumb_opcodes[] = %d print bitfield in decimal %W print bitfield*4 in decimal %r print bitfield as an ARM register + %R as %<>r but r15 is UNPREDICTABLE + %S as %<>R but r13 is UNPREDICTABLE %c print bitfield as a condition code %'c print specified char iff bitfield is all ones @@ -1231,21 +1480,59 @@ static const struct opcode16 thumb_opcodes[] = makes heavy use of special-case bit patterns. */ static const struct opcode32 thumb32_opcodes[] = { + /* V8 instructions. */ + {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"}, + {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, + {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, + + /* CRC32 instructions. */ + {CRC_EXT_ARMV8, 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, + {CRC_EXT_ARMV8, 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, + /* V7 instructions. */ {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, + {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, + {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, + /* Virtualization Extension instructions. */ + {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, + /* We skip ERET as that is SUBS pc, lr, #0. */ + + /* MP Extension instructions. */ + {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"}, + + /* Security extension instructions. */ + {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, + /* Instructions defined in the basic V6T2 set. */ {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, - {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"}, + {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"}, {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, @@ -1254,7 +1541,7 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"}, + {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, @@ -1280,10 +1567,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, @@ -1294,12 +1581,12 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, @@ -1314,17 +1601,17 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, @@ -1354,24 +1641,23 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, - {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, @@ -1414,10 +1700,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, - {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, - {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, - {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, + {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, @@ -1428,14 +1714,14 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, /* These have been 32-bit since the invention of Thumb. */ - {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"}, + {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, /* Fallback. */ - {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"}, + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, {0, 0, 0, 0} }; - + static const char *const arm_conditional[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "", ""}; @@ -1506,17 +1792,9 @@ static unsigned int ifthen_next_state; /* The address of the insn for which the IT state is valid. */ static bfd_vma ifthen_address; #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) - -/* Cached mapping symbol state. */ -enum map_type { - MAP_ARM, - MAP_THUMB, - MAP_DATA -}; - -enum map_type last_type; -int last_mapping_sym = -1; -bfd_vma last_mapping_addr = 0; +/* Indicates that the current Conditional state is unconditional or outside + an IT block. */ +#define COND_UNCOND 16 /* Functions. */ @@ -1535,7 +1813,9 @@ set_arm_regname_option (int option) } int -get_arm_regnames (int option, const char **setname, const char **setdescription, +get_arm_regnames (int option, + const char **setname, + const char **setdescription, const char *const **register_names) { *setname = regnames[option].name; @@ -1547,11 +1827,13 @@ get_arm_regnames (int option, const char **setname, const char **setdescription, /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. Returns pointer to following character of the format string and fills in *VALUEP and *WIDTHP with the extracted value and number of - bits extracted. WIDTHP can be NULL. */ + bits extracted. WIDTHP can be NULL. */ static const char * -arm_decode_bitfield (const char *ptr, unsigned long insn, - unsigned long *valuep, int *widthp) +arm_decode_bitfield (const char *ptr, + unsigned long insn, + unsigned long *valuep, + int *widthp) { unsigned long value = 0; int width = 0; @@ -1583,7 +1865,7 @@ arm_decode_bitfield (const char *ptr, unsigned long insn, static void arm_decode_shift (long given, fprintf_ftype func, void *stream, - int print_shift) + bfd_boolean print_shift) { func (stream, "%s", arm_regnames[given & 0xf]); @@ -1610,6 +1892,8 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream, else func (stream, ", #%d", amount); } + else if ((given & 0x80) == 0x80) + func (stream, "\t; "); else if (print_shift) func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], arm_regnames[(given & 0xf00) >> 8]); @@ -1618,28 +1902,64 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream, } } +#define W_BIT 21 +#define I_BIT 22 +#define U_BIT 23 +#define P_BIT 24 + +#define WRITEBACK_BIT_SET (given & (1 << W_BIT)) +#define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) +#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) +#define PRE_BIT_SET (given & (1 << P_BIT)) + /* Print one coprocessor instruction on INFO->STREAM. Return TRUE if the instuction matched, FALSE if this is not a recognised coprocessor instruction. */ static bfd_boolean -print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, +print_insn_coprocessor (bfd_vma pc, + struct disassemble_info *info, + long given, bfd_boolean thumb) { const struct opcode32 *insn; void *stream = info->stream; fprintf_ftype func = info->fprintf_func; unsigned long mask; - unsigned long value; + unsigned long value = 0; + struct arm_private_data *private_data = info->private_data; + unsigned long allowed_arches = private_data->features.coproc; int cond; for (insn = coprocessor_opcodes; insn->assembler; insn++) { - if (insn->value == FIRST_IWMMXT_INSN - && info->mach != bfd_mach_arm_XScale - && info->mach != bfd_mach_arm_iWMMXt - && info->mach != bfd_mach_arm_iWMMXt2) - insn = insn + IWMMXT_INSN_COUNT; + unsigned long u_reg = 16; + bfd_boolean is_unpredictable = FALSE; + signed long value_in_comment = 0; + const char *c; + + if (insn->arch == 0) + switch (insn->value) + { + case SENTINEL_IWMMXT_START: + if (info->mach != bfd_mach_arm_XScale + && info->mach != bfd_mach_arm_iWMMXt + && info->mach != bfd_mach_arm_iWMMXt2) + do + insn++; + while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END); + continue; + + case SENTINEL_IWMMXT_END: + continue; + + case SENTINEL_GENERIC_START: + allowed_arches = private_data->features.core; + continue; + + default: + abort (); + } mask = insn->mask; value = insn->value; @@ -1653,7 +1973,7 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, if (ifthen_state) cond = IFTHEN_COND; else - cond = 16; + cond = COND_UNCOND; } else { @@ -1662,480 +1982,545 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, if ((given & 0xf0000000) == 0xf0000000) { mask |= 0xf0000000; - cond = 16; + cond = COND_UNCOND; } else { cond = (given >> 28) & 0xf; if (cond == 0xe) - cond = 16; + cond = COND_UNCOND; } } - if ((given & mask) == value) - { - const char *c; + + if ((given & mask) != value) + continue; - for (c = insn->assembler; *c; c++) + if ((insn->arch & allowed_arches) == 0) + continue; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') { - if (*c == '%') + switch (*++c) { - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'A': - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - - if ((given & (1 << 24)) != 0) - { - int offset = given & 0xff; + case '%': + func (stream, "%%"); + break; - if (offset) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "]"); - } - else - { - int offset = given & 0xff; + case 'A': + { + int rn = (given >> 16) & 0xf; + bfd_vma offset = given & 0xff; - func (stream, "]"); + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - if (given & (1 << 21)) - { - if (offset) - func (stream, ", #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); - } - else - func (stream, ", {%d}", offset); - } - break; + if (PRE_BIT_SET || WRITEBACK_BIT_SET) + { + /* Not unindexed. The offset is scaled. */ + offset = offset * 4; + if (NEGATIVE_BIT_SET) + offset = - offset; + if (rn != 15) + value_in_comment = offset; + } - case 'B': + if (PRE_BIT_SET) { - int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); - int offset = (given >> 1) & 0x3f; - - if (offset == 1) - func (stream, "{d%d}", regno); - else if (regno + offset > 32) - func (stream, "{d%d-}", regno, regno + offset - 1); + if (offset) + func (stream, ", #%d]%s", + (int) offset, + WRITEBACK_BIT_SET ? "!" : ""); + else if (NEGATIVE_BIT_SET) + func (stream, ", #-0]"); else - func (stream, "{d%d-d%d}", regno, regno + offset - 1); + func (stream, "]"); } - break; - - case 'C': + else { - int rn = (given >> 16) & 0xf; - int offset = (given & 0xff) * 4; - int add = (given >> 23) & 1; - - func (stream, "[%s", arm_regnames[rn]); - - if (offset) + func (stream, "]"); + + if (WRITEBACK_BIT_SET) { - if (!add) - offset = -offset; - func (stream, ", #%d", offset); + if (offset) + func (stream, ", #%d", (int) offset); + else if (NEGATIVE_BIT_SET) + func (stream, ", #-0"); } - func (stream, "]"); - if (rn == 15) + else { - func (stream, "\t; "); - /* FIXME: Unsure if info->bytes_per_chunk is the - right thing to use here. */ - info->print_address_func (offset + pc - + info->bytes_per_chunk * 2, info); + func (stream, ", {%s%d}", + (NEGATIVE_BIT_SET && !offset) ? "-" : "", + (int) offset); + value_in_comment = offset; } } - break; + if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) + { + func (stream, "\t; "); + /* For unaligned PCs, apply off-by-alignment + correction. */ + info->print_address_func (offset + pc + + info->bytes_per_chunk * 2 + - (pc & 3), + info); + } + } + break; - case 'c': - func (stream, "%s", arm_conditional[cond]); - break; + case 'B': + { + int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); + int offset = (given >> 1) & 0x3f; + + if (offset == 1) + func (stream, "{d%d}", regno); + else if (regno + offset > 32) + func (stream, "{d%d-}", regno, regno + offset - 1); + else + func (stream, "{d%d-d%d}", regno, regno + offset - 1); + } + break; - case 'I': - /* Print a Cirrus/DSP shift immediate. */ - /* Immediates are 7bit signed ints with bits 0..3 in - bits 0..3 of opcode and bits 4..6 in bits 5..7 - of opcode. */ - { - int imm; + case 'u': + if (cond != COND_UNCOND) + is_unpredictable = TRUE; - imm = (given & 0xf) | ((given & 0xe0) >> 1); + /* Fall through. */ + case 'c': + func (stream, "%s", arm_conditional[cond]); + break; + + case 'I': + /* Print a Cirrus/DSP shift immediate. */ + /* Immediates are 7bit signed ints with bits 0..3 in + bits 0..3 of opcode and bits 4..6 in bits 5..7 + of opcode. */ + { + int imm; - /* Is ``imm'' a negative number? */ - if (imm & 0x40) - imm |= (-1 << 7); + imm = (given & 0xf) | ((given & 0xe0) >> 1); - func (stream, "%d", imm); - } + /* Is ``imm'' a negative number? */ + if (imm & 0x40) + imm |= (-1 << 7); + + func (stream, "%d", imm); + } + + break; + case 'F': + switch (given & 0x00408000) + { + case 0: + func (stream, "4"); + break; + case 0x8000: + func (stream, "1"); + break; + case 0x00400000: + func (stream, "2"); break; + default: + func (stream, "3"); + } + break; - case 'F': - switch (given & 0x00408000) - { - case 0: - func (stream, "4"); - break; - case 0x8000: - func (stream, "1"); - break; - case 0x00400000: - func (stream, "2"); - break; - default: - func (stream, "3"); - } + case 'P': + switch (given & 0x00080080) + { + case 0: + func (stream, "s"); + break; + case 0x80: + func (stream, "d"); + break; + case 0x00080000: + func (stream, "e"); + break; + default: + func (stream, _("")); break; + } + break; - case 'P': - switch (given & 0x00080080) - { - case 0: - func (stream, "s"); - break; - case 0x80: - func (stream, "d"); - break; - case 0x00080000: - func (stream, "e"); - break; - default: - func (stream, _("")); - break; - } + case 'Q': + switch (given & 0x00408000) + { + case 0: + func (stream, "s"); break; - case 'Q': - switch (given & 0x00408000) - { - case 0: - func (stream, "s"); - break; - case 0x8000: - func (stream, "d"); - break; - case 0x00400000: - func (stream, "e"); - break; - default: - func (stream, "p"); - break; - } + case 0x8000: + func (stream, "d"); break; - case 'R': - switch (given & 0x60) - { - case 0: - break; - case 0x20: - func (stream, "p"); - break; - case 0x40: - func (stream, "m"); - break; - default: - func (stream, "z"); - break; - } + case 0x00400000: + func (stream, "e"); + break; + default: + func (stream, "p"); break; + } + break; - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': + case 'R': + switch (given & 0x60) + { + case 0: + break; + case 0x20: + func (stream, "p"); + break; + case 0x40: + func (stream, "m"); + break; + default: + func (stream, "z"); + break; + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int width; + + c = arm_decode_bitfield (c, given, &value, &width); + + switch (*c) { - int width; - unsigned long value; + case 'R': + if (value == 15) + is_unpredictable = TRUE; + /* Fall through. */ + case 'r': + if (c[1] == 'u') + { + /* Eat the 'u' character. */ + ++ c; - c = arm_decode_bitfield (c, given, &value, &width); + if (u_reg == value) + is_unpredictable = TRUE; + u_reg = value; + } + func (stream, "%s", arm_regnames[value]); + break; + case 'D': + func (stream, "d%ld", value); + break; + case 'Q': + if (value & 1) + func (stream, "", value >> 1); + else + func (stream, "q%ld", value >> 1); + break; + case 'd': + func (stream, "%ld", value); + value_in_comment = value; + break; + case 'k': + { + int from = (given & (1 << 7)) ? 32 : 16; + func (stream, "%ld", from - value); + } + break; - switch (*c) + case 'f': + if (value > 7) + func (stream, "#%s", arm_fp_const[value & 7]); + else + func (stream, "f%ld", value); + break; + + case 'w': + if (width == 2) + func (stream, "%s", iwmmxt_wwnames[value]); + else + func (stream, "%s", iwmmxt_wwssnames[value]); + break; + + case 'g': + func (stream, "%s", iwmmxt_regnames[value]); + break; + case 'G': + func (stream, "%s", iwmmxt_cregnames[value]); + break; + + case 'x': + func (stream, "0x%lx", (value & 0xffffffffUL)); + break; + + case 'c': + switch (value) { - case 'r': - func (stream, "%s", arm_regnames[value]); - break; - case 'D': - func (stream, "d%ld", value); - break; - case 'Q': - if (value & 1) - func (stream, "", value >> 1); - else - func (stream, "q%ld", value >> 1); - break; - case 'd': - func (stream, "%ld", value); - break; - case 'k': - { - int from = (given & (1 << 7)) ? 32 : 16; - func (stream, "%ld", from - value); - } - break; - - case 'f': - if (value > 7) - func (stream, "#%s", arm_fp_const[value & 7]); - else - func (stream, "f%ld", value); + case 0: + func (stream, "eq"); break; - case 'w': - if (width == 2) - func (stream, "%s", iwmmxt_wwnames[value]); - else - func (stream, "%s", iwmmxt_wwssnames[value]); + case 1: + func (stream, "vs"); break; - case 'g': - func (stream, "%s", iwmmxt_regnames[value]); - break; - case 'G': - func (stream, "%s", iwmmxt_cregnames[value]); + case 2: + func (stream, "ge"); break; - case 'x': - func (stream, "0x%lx", value); + case 3: + func (stream, "gt"); break; - case '`': - c++; - if (value == 0) - func (stream, "%c", *c); + default: + func (stream, "??"); break; - case '\'': - c++; - if (value == ((1ul << width) - 1)) - func (stream, "%c", *c); - break; - case '?': - func (stream, "%c", c[(1 << width) - (int)value]); - c += 1 << width; - break; - default: - abort (); } break; - case 'y': - case 'z': - { - int single = *c++ == 'y'; - int regno; - - switch (*c) - { - case '4': /* Sm pair */ - case '0': /* Sm, Dm */ - regno = given & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 5) & 1; - } - else - regno += ((given >> 5) & 1) << 4; - break; + case '`': + c++; + if (value == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if (value == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + case '?': + func (stream, "%c", c[(1 << width) - (int) value]); + c += 1 << width; + break; + default: + abort (); + } + break; - case '1': /* Sd, Dd */ - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - else - regno += ((given >> 22) & 1) << 4; - break; + case 'y': + case 'z': + { + int single = *c++ == 'y'; + int regno; - case '2': /* Sn, Dn */ - regno = (given >> 16) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 7) & 1; - } - else - regno += ((given >> 7) & 1) << 4; - break; - - case '3': /* List */ - func (stream, "{"); - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - else - regno += ((given >> 22) & 1) << 4; - break; - - default: - abort (); + switch (*c) + { + case '4': /* Sm pair */ + case '0': /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 5) & 1; } + else + regno += ((given >> 5) & 1) << 4; + break; - func (stream, "%c%d", single ? 's' : 'd', regno); + case '1': /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + else + regno += ((given >> 22) & 1) << 4; + break; - if (*c == '3') + case '2': /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) { - int count = given & 0xff; - - if (single == 0) - count >>= 1; - - if (--count) - { - func (stream, "-%c%d", - single ? 's' : 'd', - regno + count); - } - - func (stream, "}"); + regno <<= 1; + regno += (given >> 7) & 1; } - else if (*c == '4') - func (stream, ", %c%d", single ? 's' : 'd', - regno + 1); - } - break; + else + regno += ((given >> 7) & 1) << 4; + break; - case 'L': - switch (given & 0x00400100) - { - case 0x00000000: func (stream, "b"); break; - case 0x00400000: func (stream, "h"); break; - case 0x00000100: func (stream, "w"); break; - case 0x00400100: func (stream, "d"); break; - default: - break; - } - break; + case '3': /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + else + regno += ((given >> 22) & 1) << 4; + break; - case 'Z': - { - int value; - /* given (20, 23) | given (0, 3) */ - value = ((given >> 16) & 0xf0) | (given & 0xf); - func (stream, "%d", value); + default: + abort (); } - break; - case 'l': - /* This is like the 'A' operator, except that if - the width field "M" is zero, then the offset is - *not* multiplied by four. */ + func (stream, "%c%d", single ? 's' : 'd', regno); + + if (*c == '3') { - int offset = given & 0xff; - int multiplier = (given & 0x00000100) ? 4 : 1; + int count = given & 0xff; - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + if (single == 0) + count >>= 1; - if (offset) + if (--count) { - if ((given & 0x01000000) != 0) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * multiplier, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "], #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * multiplier); + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); } - else - func (stream, "]"); + + func (stream, "}"); } + else if (*c == '4') + func (stream, ", %c%d", single ? 's' : 'd', + regno + 1); + } + break; + + case 'L': + switch (given & 0x00400100) + { + case 0x00000000: func (stream, "b"); break; + case 0x00400000: func (stream, "h"); break; + case 0x00000100: func (stream, "w"); break; + case 0x00400100: func (stream, "d"); break; + default: break; + } + break; - case 'r': - { - int imm4 = (given >> 4) & 0xf; - int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1); - int ubit = (given >> 23) & 1; - const char *rm = arm_regnames [given & 0xf]; - const char *rn = arm_regnames [(given >> 16) & 0xf]; + case 'Z': + { + /* given (20, 23) | given (0, 3) */ + value = ((given >> 16) & 0xf0) | (given & 0xf); + func (stream, "%d", (int) value); + } + break; - switch (puw_bits) - { - case 1: - /* fall through */ - case 3: - func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); - if (imm4) - func (stream, ", lsl #%d", imm4); - break; + case 'l': + /* This is like the 'A' operator, except that if + the width field "M" is zero, then the offset is + *not* multiplied by four. */ + { + int offset = given & 0xff; + int multiplier = (given & 0x00000100) ? 4 : 1; - case 4: - /* fall through */ - case 5: - /* fall through */ - case 6: - /* fall through */ - case 7: - func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); - if (imm4 > 0) - func (stream, ", lsl #%d", imm4); - func (stream, "]"); - if (puw_bits == 5 || puw_bits == 7) - func (stream, "!"); - break; + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - default: - func (stream, "INVALID"); - } + if (multiplier > 1) + { + value_in_comment = offset * multiplier; + if (NEGATIVE_BIT_SET) + value_in_comment = - value_in_comment; } - break; - case 'i': + if (offset) { - long imm5; - imm5 = ((given & 0x100) >> 4) | (given & 0xf); - func (stream, "%ld", (imm5 == 0) ? 32 : imm5); + if (PRE_BIT_SET) + func (stream, ", #%s%d]%s", + NEGATIVE_BIT_SET ? "-" : "", + offset * multiplier, + WRITEBACK_BIT_SET ? "!" : ""); + else + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", + offset * multiplier); } - break; + else + func (stream, "]"); + } + break; - default: - abort (); - } + case 'r': + { + int imm4 = (given >> 4) & 0xf; + int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); + int ubit = ! NEGATIVE_BIT_SET; + const char *rm = arm_regnames [given & 0xf]; + const char *rn = arm_regnames [(given >> 16) & 0xf]; + + switch (puw_bits) + { + case 1: + case 3: + func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); + if (imm4) + func (stream, ", lsl #%d", imm4); + break; + + case 4: + case 5: + case 6: + case 7: + func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); + if (imm4 > 0) + func (stream, ", lsl #%d", imm4); + func (stream, "]"); + if (puw_bits == 5 || puw_bits == 7) + func (stream, "!"); + break; + + default: + func (stream, "INVALID"); + } + } + break; + + case 'i': + { + long imm5; + imm5 = ((given & 0x100) >> 4) | (given & 0xf); + func (stream, "%ld", (imm5 == 0) ? 32 : imm5); } + break; + + default: + abort (); + } } - else - func (stream, "%c", *c); } - return TRUE; + else + func (stream, "%c", *c); } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + + return TRUE; } return FALSE; } -static void +/* Decodes and prints ARM addressing modes. Returns the offset + used in the address, if any, if it is worthwhile printing the + offset as a hexadecimal value in a comment at the end of the + line of disassembly. */ + +static signed long print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) { void *stream = info->stream; fprintf_ftype func = info->fprintf_func; + bfd_vma offset = 0; if (((given & 0x000f0000) == 0x000f0000) && ((given & 0x02000000) == 0)) { - int offset = given & 0xfff; + offset = given & 0xfff; func (stream, "[pc"); - if (given & 0x01000000) + if (PRE_BIT_SET) { - if ((given & 0x00800000) == 0) - offset = - offset; + /* Pre-indexed. Elide offset of positive zero when + non-writeback. */ + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); - /* Pre-indexed. */ - func (stream, ", #%d]", offset); + if (NEGATIVE_BIT_SET) + offset = -offset; offset += pc + 8; @@ -2143,67 +2528,62 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) being used. Probably a very dangerous thing for the programmer to do, but who are we to argue ? */ - if (given & 0x00200000) - func (stream, "!"); + func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); } - else + else /* Post indexed. */ { - /* Post indexed. */ - func (stream, "], #%d", offset); + func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); - /* ie ignore the offset. */ + /* Ie ignore the offset. */ offset = pc + 8; } func (stream, "\t; "); info->print_address_func (offset, info); + offset = 0; } else { func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) + + if (PRE_BIT_SET) { if ((given & 0x02000000) == 0) { - int offset = given & 0xfff; - if (offset) - func (stream, ", #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); + /* Elide offset of positive zero when non-writeback. */ + offset = given & 0xfff; + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); } else { - func (stream, ", %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream, 1); + func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); + arm_decode_shift (given, func, stream, TRUE); } func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); + WRITEBACK_BIT_SET ? "!" : ""); } else { if ((given & 0x02000000) == 0) { - int offset = given & 0xfff; - if (offset) - func (stream, "], #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); + /* Always show offset. */ + offset = given & 0xfff; + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); } else { func (stream, "], %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream, 1); + NEGATIVE_BIT_SET ? "-" : ""); + arm_decode_shift (given, func, stream, TRUE); } } } + + return (signed long) offset; } /* Print one neon instruction on INFO->STREAM. @@ -2221,7 +2601,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) { if ((given & 0xef000000) == 0xef000000) { - /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ + /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ unsigned long bit28 = given & (1 << 28); given &= 0x00ffffff; @@ -2240,6 +2620,8 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) { if ((given & insn->mask) == insn->value) { + signed long value_in_comment = 0; + bfd_boolean is_unpredictable = FALSE; const char *c; for (c = insn->assembler; *c; c++) @@ -2252,6 +2634,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "%%"); break; + case 'u': + if (thumb && ifthen_state) + is_unpredictable = TRUE; + + /* Fall through. */ case 'c': if (thumb && ifthen_state) func (stream, "%s", arm_conditional[IFTHEN_COND]); @@ -2292,7 +2679,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "d%d-d%d", rd, rd + n - 1); func (stream, "}, [%s", arm_regnames[rn]); if (align) - func (stream, ", :%d", 32 << align); + func (stream, " :%d", 32 << align); func (stream, "]"); if (rm == 0xd) func (stream, "!"); @@ -2367,7 +2754,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) rd + i * stride, idx); func (stream, "}, [%s", arm_regnames[rn]); if (align) - func (stream, ", :%d", align); + func (stream, " :%d", align); func (stream, "]"); if (rm == 0xd) func (stream, "!"); @@ -2404,13 +2791,13 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "}, [%s", arm_regnames[rn]); if (align) { - int align = (8 * (type + 1)) << size; + align = (8 * (type + 1)) << size; if (type == 3) align = (size > 1) ? align >> 1 : align; if (type == 2 || (type == 0 && !size)) - func (stream, ", :", align); + func (stream, " :", align); else - func (stream, ", :%d", align); + func (stream, " :%d", align); } func (stream, "]"); if (rm == 0xd) @@ -2432,7 +2819,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) break; case 'E': - /* Neon encoded constant for mov, mvn, vorr, vbic */ + /* Neon encoded constant for mov, mvn, vorr, vbic. */ { int bits = 0; int cmode = (given >> 8) & 0xf; @@ -2449,19 +2836,19 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if (cmode < 8) { shift = (cmode >> 1) & 3; - value = (unsigned long)bits << (8 * shift); + value = (unsigned long) bits << (8 * shift); size = 32; } else if (cmode < 12) { shift = (cmode >> 1) & 1; - value = (unsigned long)bits << (8 * shift); + value = (unsigned long) bits << (8 * shift); size = 16; } else if (cmode < 14) { shift = (cmode & 1) + 1; - value = (unsigned long)bits << (8 * shift); + value = (unsigned long) bits << (8 * shift); value |= (1ul << (8 * shift)) - 1; size = 32; } @@ -2469,7 +2856,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) { if (op) { - /* bit replication into bytes */ + /* Bit replication into bytes. */ int ix; unsigned long mask; @@ -2487,20 +2874,20 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } else { - /* byte replication */ - value = (unsigned long)bits; + /* Byte replication. */ + value = (unsigned long) bits; size = 8; } } else if (!op) { - /* floating point encoding */ + /* Floating point encoding. */ int tmp; - value = (unsigned long)(bits & 0x7f) << 19; - value |= (unsigned long)(bits & 0x80) << 24; + value = (unsigned long) (bits & 0x7f) << 19; + value |= (unsigned long) (bits & 0x80) << 24; tmp = bits & 0x40 ? 0x3c : 0x40; - value |= (unsigned long)tmp << 24; + value |= (unsigned long) tmp << 24; size = 32; isfloat = 1; } @@ -2535,16 +2922,17 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) valbytes[3] = (value >> 24) & 0xff; floatformat_to_double - (&floatformat_ieee_single_little, valbytes, - &fvalue); + (& floatformat_ieee_single_little, valbytes, + & fvalue); func (stream, "#%.7g\t; 0x%.8lx", fvalue, value); } else func (stream, "#%ld\t; 0x%.8lx", - (long) ((value & 0x80000000) - ? value | ~0xffffffffl : value), value); + (long) (((value & 0x80000000L) != 0) + ? value | ~0xffffffffL : value), + value); break; case 64: @@ -2570,7 +2958,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "{d%d-d%d}", regno, regno + num); } break; - + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': @@ -2587,6 +2975,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) break; case 'd': func (stream, "%ld", value); + value_in_comment = value; break; case 'e': func (stream, "%ld", (1ul << width) - value); @@ -2595,7 +2984,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) case 'S': case 'T': case 'U': - /* various width encodings */ + /* Various width encodings. */ { int base = 8 << (*c - 'S'); /* 8,16 or 32 */ int limit; @@ -2643,7 +3032,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "%c", *c); break; case '?': - func (stream, "%c", c[(1 << width) - (int)value]); + func (stream, "%c", c[(1 << width) - (int) value]); c += 1 << width; break; default: @@ -2659,12 +3048,87 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) else func (stream, "%c", *c); } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", value_in_comment); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + return TRUE; } } return FALSE; } +/* Return the name of a v7A special register. */ + +static const char * +banked_regname (unsigned reg) +{ + switch (reg) + { + case 15: return "CPSR"; + case 32: return "R8_usr"; + case 33: return "R9_usr"; + case 34: return "R10_usr"; + case 35: return "R11_usr"; + case 36: return "R12_usr"; + case 37: return "SP_usr"; + case 38: return "LR_usr"; + case 40: return "R8_fiq"; + case 41: return "R9_fiq"; + case 42: return "R10_fiq"; + case 43: return "R11_fiq"; + case 44: return "R12_fiq"; + case 45: return "SP_fiq"; + case 46: return "LR_fiq"; + case 48: return "LR_irq"; + case 49: return "SP_irq"; + case 50: return "LR_svc"; + case 51: return "SP_svc"; + case 52: return "LR_abt"; + case 53: return "SP_abt"; + case 54: return "LR_und"; + case 55: return "SP_und"; + case 60: return "LR_mon"; + case 61: return "SP_mon"; + case 62: return "ELR_hyp"; + case 63: return "SP_hyp"; + case 79: return "SPSR"; + case 110: return "SPSR_fiq"; + case 112: return "SPSR_irq"; + case 114: return "SPSR_svc"; + case 116: return "SPSR_abt"; + case 118: return "SPSR_und"; + case 124: return "SPSR_mon"; + case 126: return "SPSR_hyp"; + default: return NULL; + } +} + +/* Return the name of the DMB/DSB option. */ +static const char * +data_barrier_option (unsigned option) +{ + switch (option & 0xf) + { + case 0xf: return "sy"; + case 0xe: return "st"; + case 0xd: return "ld"; + case 0xb: return "ish"; + case 0xa: return "ishst"; + case 0x9: return "ishld"; + case 0x7: return "un"; + case 0x6: return "unst"; + case 0x5: return "nshld"; + case 0x3: return "osh"; + case 0x2: return "oshst"; + case 0x1: return "oshld"; + default: return NULL; + } +} + /* Print one ARM instruction from PC on INFO->STREAM. */ static void @@ -2673,6 +3137,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) const struct opcode32 *insn; void *stream = info->stream; fprintf_ftype func = info->fprintf_func; + struct arm_private_data *private_data = info->private_data; if (print_insn_coprocessor (pc, info, given, FALSE)) return; @@ -2682,25 +3147,31 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) for (insn = arm_opcodes; insn->assembler; insn++) { - if (insn->value == FIRST_IWMMXT_INSN - && info->mach != bfd_mach_arm_XScale - && info->mach != bfd_mach_arm_iWMMXt) - insn = insn + IWMMXT_INSN_COUNT; - - if ((given & insn->mask) == insn->value - /* Special case: an instruction with all bits set in the condition field - (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, - or by the catchall at the end of the table. */ - && ((given & 0xF0000000) != 0xF0000000 - || (insn->mask & 0xF0000000) == 0xF0000000 - || (insn->mask == 0 && insn->value == 0))) + if ((given & insn->mask) != insn->value) + continue; + + if ((insn->arch & private_data->features.core) == 0) + continue; + + /* Special case: an instruction with all bits set in the condition field + (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, + or by the catchall at the end of the table. */ + if ((given & 0xF0000000) != 0xF0000000 + || (insn->mask & 0xF0000000) == 0xF0000000 + || (insn->mask == 0 && insn->value == 0)) { + unsigned long u_reg = 16; + unsigned long U_reg = 16; + bfd_boolean is_unpredictable = FALSE; + signed long value_in_comment = 0; const char *c; for (c = insn->assembler; *c; c++) { if (*c == '%') { + bfd_boolean allow_unpredictable = FALSE; + switch (*++c) { case '%': @@ -2708,76 +3179,121 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) break; case 'a': - print_arm_address (pc, info, given); + value_in_comment = print_arm_address (pc, info, given); break; case 'P': /* Set P address bit and use normal address printing routine. */ - print_arm_address (pc, info, given | (1 << 24)); + value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); break; + case 'S': + allow_unpredictable = TRUE; case 's': if ((given & 0x004f0000) == 0x004f0000) { /* PC relative with immediate offset. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); + bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); - if ((given & 0x00800000) == 0) - offset = -offset; - - func (stream, "[pc, #%d]\t; ", offset); - info->print_address_func (offset + pc + 8, info); + if (PRE_BIT_SET) + { + /* Elide positive zero offset. */ + if (offset || NEGATIVE_BIT_SET) + func (stream, "[pc, #%s%d]\t; ", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); + else + func (stream, "[pc]\t; "); + if (NEGATIVE_BIT_SET) + offset = -offset; + info->print_address_func (offset + pc + 8, info); + } + else + { + /* Always show the offset. */ + func (stream, "[pc], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); + if (! allow_unpredictable) + is_unpredictable = TRUE; + } } else { + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) + + if (PRE_BIT_SET) { - /* Pre-indexed. */ - if ((given & 0x00400000) == 0x00400000) + if (IMMEDIATE_BIT_SET) { - /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) + /* Elide offset for non-writeback + positive zero. */ + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET + || offset) func (stream, ", #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); + NEGATIVE_BIT_SET ? "-" : "", offset); + + if (NEGATIVE_BIT_SET) + offset = -offset; + + value_in_comment = offset; } else { - /* Register. */ + /* Register Offset or Register Pre-Indexed. */ func (stream, ", %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); + NEGATIVE_BIT_SET ? "-" : "", + arm_regnames[given & 0xf]); + + /* Writing back to the register that is the source/ + destination of the load/store is unpredictable. */ + if (! allow_unpredictable + && WRITEBACK_BIT_SET + && ((given & 0xf) == ((given >> 12) & 0xf))) + is_unpredictable = TRUE; } func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); + WRITEBACK_BIT_SET ? "!" : ""); } else { - /* Post-indexed. */ - if ((given & 0x00400000) == 0x00400000) + if (IMMEDIATE_BIT_SET) { - /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, "], #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); + /* Immediate Post-indexed. */ + /* PR 10924: Offset must be printed, even if it is zero. */ + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", offset); + if (NEGATIVE_BIT_SET) + offset = -offset; + value_in_comment = offset; } else { - /* Register. */ + /* Register Post-indexed. */ func (stream, "], %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); + NEGATIVE_BIT_SET ? "-" : "", + arm_regnames[given & 0xf]); + + /* Writing back to the register that is the source/ + destination of the load/store is unpredictable. */ + if (! allow_unpredictable + && (given & 0xf) == ((given >> 12) & 0xf)) + is_unpredictable = TRUE; + } + + if (! allow_unpredictable) + { + /* Writeback is automatically implied by post- addressing. + Setting the W bit is unnecessary and ARM specify it as + being unpredictable. */ + if (WRITEBACK_BIT_SET + /* Specifying the PC register as the post-indexed + registers is also unpredictable. */ + || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) + is_unpredictable = TRUE; } } } @@ -2785,8 +3301,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'b': { - int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); - info->print_address_func (disp*4 + pc + 8, info); + bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); + info->print_address_func (disp * 4 + pc + 8, info); } break; @@ -2811,29 +3327,49 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%s", arm_regnames[reg]); } func (stream, "}"); + if (! started) + is_unpredictable = TRUE; } break; case 'q': - arm_decode_shift (given, func, stream, 0); + arm_decode_shift (given, func, stream, FALSE); break; case 'o': if ((given & 0x02000000) != 0) { - int rotate = (given & 0xf00) >> 7; - int immed = (given & 0xff); - immed = (((immed << (32 - rotate)) - | (immed >> rotate)) & 0xffffffff); - func (stream, "#%d\t; 0x%x", immed, immed); + unsigned int rotate = (given & 0xf00) >> 7; + unsigned int immed = (given & 0xff); + unsigned int a, i; + + a = (((immed << (32 - rotate)) + | (immed >> rotate)) & 0xffffffff); + /* If there is another encoding with smaller rotate, + the rotate should be specified directly. */ + for (i = 0; i < 32; i += 2) + if ((a << i | a >> (32 - i)) <= 0xff) + break; + + if (i != rotate) + func (stream, "#%d, %d", immed, rotate); + else + func (stream, "#%d", a); + value_in_comment = a; } else - arm_decode_shift (given, func, stream, 1); + arm_decode_shift (given, func, stream, TRUE); break; case 'p': if ((given & 0x0000f000) == 0x0000f000) - func (stream, "p"); + { + /* The p-variants of tst/cmp/cmn/teq are the pre-V6 + mechanism for setting PSR flag bits. They are + obsolete in V6 onwards. */ + if ((private_data->features.core & ARM_EXT_V6) == 0) + func (stream, "p"); + } break; case 't': @@ -2842,36 +3378,40 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) break; case 'A': - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + { + int offset = given & 0xff; - if ((given & (1 << 24)) != 0) - { - int offset = given & 0xff; + value_in_comment = offset * 4; + if (NEGATIVE_BIT_SET) + value_in_comment = - value_in_comment; - if (offset) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "]"); - } - else - { - int offset = given & 0xff; + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - func (stream, "]"); + if (PRE_BIT_SET) + { + if (offset) + func (stream, ", #%d]%s", + (int) value_in_comment, + WRITEBACK_BIT_SET ? "!" : ""); + else + func (stream, "]"); + } + else + { + func (stream, "]"); - if (given & (1 << 21)) - { - if (offset) - func (stream, ", #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); - } - else - func (stream, ", {%d}", offset); - } + if (WRITEBACK_BIT_SET) + { + if (offset) + func (stream, ", #%d", (int) value_in_comment); + } + else + { + func (stream, ", {%d}", (int) offset); + value_in_comment = offset; + } + } + } break; case 'B': @@ -2880,7 +3420,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) bfd_vma address; bfd_vma offset = 0; - if (given & 0x00800000) + if (! NEGATIVE_BIT_SET) /* Is signed, hi bits should be ones. */ offset = (-1) ^ 0x00ffffff; @@ -2898,27 +3438,52 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) break; case 'C': - func (stream, "_"); - if (given & 0x80000) - func (stream, "f"); - if (given & 0x40000) - func (stream, "s"); - if (given & 0x20000) - func (stream, "x"); - if (given & 0x10000) - func (stream, "c"); + if ((given & 0x02000200) == 0x200) + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; + + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } + else + { + func (stream, "%cPSR_", + (given & 0x00400000) ? 'S' : 'C'); + if (given & 0x80000) + func (stream, "f"); + if (given & 0x40000) + func (stream, "s"); + if (given & 0x20000) + func (stream, "x"); + if (given & 0x10000) + func (stream, "c"); + } break; case 'U': - switch (given & 0xf) + if ((given & 0xf0) == 0x60) { - case 0xf: func(stream, "sy"); break; - case 0x7: func(stream, "un"); break; - case 0xe: func(stream, "st"); break; - case 0x6: func(stream, "unst"); break; - default: - func(stream, "#%d", (int)given & 0xf); - break; + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } + } + else + { + const char * opt = data_barrier_option (given & 0xf); + if (opt != NULL) + func (stream, "%s", opt); + else + func (stream, "#%d", (int) given & 0xf); } break; @@ -2932,17 +3497,47 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) switch (*c) { + case 'R': + if (value == 15) + is_unpredictable = TRUE; + /* Fall through. */ case 'r': + case 'T': + /* We want register + 1 when decoding T. */ + if (*c == 'T') + ++value; + + if (c[1] == 'u') + { + /* Eat the 'u' character. */ + ++ c; + + if (u_reg == value) + is_unpredictable = TRUE; + u_reg = value; + } + if (c[1] == 'U') + { + /* Eat the 'U' character. */ + ++ c; + + if (U_reg == value) + is_unpredictable = TRUE; + U_reg = value; + } func (stream, "%s", arm_regnames[value]); break; case 'd': func (stream, "%ld", value); + value_in_comment = value; break; case 'b': func (stream, "%ld", value * 8); + value_in_comment = value * 8; break; case 'W': func (stream, "%ld", value + 1); + value_in_comment = value + 1; break; case 'x': func (stream, "0x%08lx", value); @@ -2956,6 +3551,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) break; case 'X': func (stream, "%01lx", value & 0xf); + value_in_comment = value; break; case '`': c++; @@ -2968,7 +3564,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%c", *c); break; case '?': - func (stream, "%c", c[(1 << width) - (int)value]); + func (stream, "%c", c[(1 << width) - (int) value]); c += 1 << width; break; default: @@ -2982,6 +3578,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) imm = (given & 0xf) | ((given & 0xfff00) >> 4); func (stream, "%d", imm); + value_in_comment = imm; } break; @@ -2991,15 +3588,31 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { long msb = (given & 0x001f0000) >> 16; long lsb = (given & 0x00000f80) >> 7; + long w = msb - lsb + 1; - long width = msb - lsb + 1; - if (width > 0) - func (stream, "#%lu, #%lu", lsb, width); + if (w > 0) + func (stream, "#%lu, #%lu", lsb, w); else func (stream, "(invalid: %lu:%lu)", lsb, msb); } break; + case 'R': + /* Get the PSR/banked register name. */ + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; + + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } + break; + case 'V': /* 16-bit unsigned immediate from a MOVT or MOVW instruction, encoded in bits 0:11 and 15:19. */ @@ -3007,7 +3620,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) long hi = (given & 0x000f0000) >> 4; long lo = (given & 0x00000fff); long imm16 = hi | lo; - func (stream, "#%lu\t; 0x%lx", imm16, imm16); + + func (stream, "#%lu", imm16); + value_in_comment = imm16; } break; @@ -3019,6 +3634,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) else func (stream, "%c", *c); } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + return; } } @@ -3037,7 +3659,9 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) for (insn = thumb_opcodes; insn->assembler; insn++) if ((given & insn->mask) == insn->value) { + signed long value_in_comment = 0; const char *c = insn->assembler; + for (; *c; c++) { int domaskpc = 0; @@ -3144,20 +3768,28 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) if (started) func (stream, ", "); started = 1; - func (stream, arm_regnames[14] /* "lr" */); + func (stream, "%s", arm_regnames[14] /* "lr" */); } if (domaskpc) { if (started) func (stream, ", "); - func (stream, arm_regnames[15] /* "pc" */); + func (stream, "%s", arm_regnames[15] /* "pc" */); } func (stream, "}"); } break; + case 'W': + /* Print writeback indicator for a LDMIA. We are doing a + writeback if the base register is not in the register + mask. */ + if ((given & (1 << ((given & 0x0700) >> 8))) == 0) + func (stream, "!"); + break; + case 'b': /* Print ARM V6T2 CZB address: pc+4+6 bits. */ { @@ -3192,7 +3824,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) { case '-': { - long reg; + bfd_vma reg; c++; while (*c >= '0' && *c <= '9') @@ -3201,6 +3833,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) abort (); reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; + switch (*c) { case 'r': @@ -3208,15 +3841,18 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'd': - func (stream, "%ld", reg); + func (stream, "%ld", (long) reg); + value_in_comment = reg; break; case 'H': - func (stream, "%ld", reg << 1); + func (stream, "%ld", (long) (reg << 1)); + value_in_comment = reg << 1; break; case 'W': - func (stream, "%ld", reg << 2); + func (stream, "%ld", (long) (reg << 2)); + value_in_comment = reg << 2; break; case 'a': @@ -3225,15 +3861,17 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) before the calculation. */ info->print_address_func (((pc + 4) & ~3) + (reg << 2), info); + value_in_comment = 0; break; case 'x': - func (stream, "0x%04lx", reg); + func (stream, "0x%04lx", (long) reg); break; case 'B': reg = ((reg ^ (1 << bitend)) - (1 << bitend)); info->print_address_func (reg * 2 + pc + 4, info); + value_in_comment = 0; break; case 'c': @@ -3270,6 +3908,9 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) abort (); } } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", value_in_comment); return; } @@ -3278,6 +3919,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) } /* Return the name of an V7M special register. */ + static const char * psr_name (int regno) { @@ -3294,7 +3936,7 @@ psr_name (int regno) case 9: return "PSP"; case 16: return "PRIMASK"; case 17: return "BASEPRI"; - case 18: return "BASEPRI_MASK"; + case 18: return "BASEPRI_MAX"; case 19: return "FAULTMASK"; case 20: return "CONTROL"; default: return ""; @@ -3319,7 +3961,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) for (insn = thumb32_opcodes; insn->assembler; insn++) if ((given & insn->mask) == insn->value) { + bfd_boolean is_unpredictable = FALSE; + signed long value_in_comment = 0; const char *c = insn->assembler; + for (; *c; c++) { if (*c != '%') @@ -3353,16 +3998,19 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 'I': { unsigned int imm12 = 0; + imm12 |= (given & 0x000000ffu); imm12 |= (given & 0x00007000u) >> 4; imm12 |= (given & 0x04000000u) >> 15; - func (stream, "#%u\t; 0x%x", imm12, imm12); + func (stream, "#%u", imm12); + value_in_comment = imm12; } break; case 'M': { unsigned int bits = 0, imm, imm8, mod; + bits |= (given & 0x000000ffu); bits |= (given & 0x00007000u) >> 4; bits |= (given & 0x04000000u) >> 15; @@ -3371,36 +4019,52 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) switch (mod) { case 0: imm = imm8; break; - case 1: imm = ((imm8<<16) | imm8); break; - case 2: imm = ((imm8<<24) | (imm8 << 8)); break; - case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break; + case 1: imm = ((imm8 << 16) | imm8); break; + case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; + case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; default: mod = (bits & 0xf80) >> 7; imm8 = (bits & 0x07f) | 0x80; imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); } - func (stream, "#%u\t; 0x%x", imm, imm); + func (stream, "#%u", imm); + value_in_comment = imm; } break; case 'J': { unsigned int imm = 0; + imm |= (given & 0x000000ffu); imm |= (given & 0x00007000u) >> 4; imm |= (given & 0x04000000u) >> 15; imm |= (given & 0x000f0000u) >> 4; - func (stream, "#%u\t; 0x%x", imm, imm); + func (stream, "#%u", imm); + value_in_comment = imm; } break; case 'K': { unsigned int imm = 0; + imm |= (given & 0x000f0000u) >> 16; imm |= (given & 0x00000ff0u) >> 0; imm |= (given & 0x0000000fu) << 12; - func (stream, "#%u\t; 0x%x", imm, imm); + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + + case 'V': + { + unsigned int imm = 0; + + imm |= (given & 0x00000fffu); + imm |= (given & 0x000f0000u) >> 4; + func (stream, "#%u", imm); + value_in_comment = imm; } break; @@ -3444,22 +4108,27 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 'a': { unsigned int Rn = (given & 0x000f0000) >> 16; - unsigned int U = (given & 0x00800000) >> 23; + unsigned int U = ! NEGATIVE_BIT_SET; unsigned int op = (given & 0x00000f00) >> 8; unsigned int i12 = (given & 0x00000fff); unsigned int i8 = (given & 0x000000ff); bfd_boolean writeback = FALSE, postind = FALSE; - int offset = 0; + bfd_vma offset = 0; func (stream, "[%s", arm_regnames[Rn]); - if (U) /* 12-bit positive immediate offset */ - offset = i12; - else if (Rn == 15) /* 12-bit negative immediate offset */ - offset = -(int)i12; - else if (op == 0x0) /* shifted register offset */ + if (U) /* 12-bit positive immediate offset. */ + { + offset = i12; + if (Rn != 15) + value_in_comment = offset; + } + else if (Rn == 15) /* 12-bit negative immediate offset. */ + offset = - (int) i12; + else if (op == 0x0) /* Shifted register offset. */ { unsigned int Rm = (i8 & 0x0f); unsigned int sh = (i8 & 0x30) >> 4; + func (stream, ", %s", arm_regnames[Rm]); if (sh) func (stream, ", lsl #%u", sh); @@ -3468,30 +4137,30 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } else switch (op) { - case 0xE: /* 8-bit positive immediate offset */ + case 0xE: /* 8-bit positive immediate offset. */ offset = i8; break; - case 0xC: /* 8-bit negative immediate offset */ + case 0xC: /* 8-bit negative immediate offset. */ offset = -i8; break; - case 0xF: /* 8-bit + preindex with wb */ + case 0xF: /* 8-bit + preindex with wb. */ offset = i8; writeback = TRUE; break; - case 0xD: /* 8-bit - preindex with wb */ + case 0xD: /* 8-bit - preindex with wb. */ offset = -i8; writeback = TRUE; break; - case 0xB: /* 8-bit + postindex */ + case 0xB: /* 8-bit + postindex. */ offset = i8; postind = TRUE; break; - case 0x9: /* 8-bit - postindex */ + case 0x9: /* 8-bit - postindex. */ offset = -i8; postind = TRUE; break; @@ -3502,11 +4171,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } if (postind) - func (stream, "], #%d", offset); + func (stream, "], #%d", (int) offset); else { if (offset) - func (stream, ", #%d", offset); + func (stream, ", #%d", (int) offset); func (stream, writeback ? "]!" : "]"); } @@ -3521,17 +4190,20 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 'A': { - unsigned int P = (given & 0x01000000) >> 24; - unsigned int U = (given & 0x00800000) >> 23; - unsigned int W = (given & 0x00400000) >> 21; + unsigned int U = ! NEGATIVE_BIT_SET; + unsigned int W = WRITEBACK_BIT_SET; unsigned int Rn = (given & 0x000f0000) >> 16; unsigned int off = (given & 0x000000ff); func (stream, "[%s", arm_regnames[Rn]); - if (P) + + if (PRE_BIT_SET) { if (off || !U) - func (stream, ", #%c%u", U ? '+' : '-', off * 4); + { + func (stream, ", #%c%u", U ? '+' : '-', off * 4); + value_in_comment = off * 4 * U ? 1 : -1; + } func (stream, "]"); if (W) func (stream, "!"); @@ -3540,9 +4212,15 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) { func (stream, "], "); if (W) - func (stream, "#%c%u", U ? '+' : '-', off * 4); + { + func (stream, "#%c%u", U ? '+' : '-', off * 4); + value_in_comment = off * 4 * U ? 1 : -1; + } else - func (stream, "{%u}", off); + { + func (stream, "{%u}", off); + value_in_comment = off; + } } } break; @@ -3551,6 +4229,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) { unsigned int Sbit = (given & 0x01000000) >> 24; unsigned int type = (given & 0x00600000) >> 21; + switch (type) { case 0: func (stream, Sbit ? "sb" : "b"); break; @@ -3588,6 +4267,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) { unsigned int msb = (given & 0x0000001f); unsigned int lsb = 0; + lsb |= (given & 0x000000c0u) >> 6; lsb |= (given & 0x00007000u) >> 10; func (stream, "#%u, #%u", lsb, msb - lsb + 1); @@ -3598,6 +4278,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) { unsigned int width = (given & 0x0000001f) + 1; unsigned int lsb = 0; + lsb |= (given & 0x000000c0u) >> 6; lsb |= (given & 0x00007000u) >> 10; func (stream, "#%u, #%u", lsb, width); @@ -3609,7 +4290,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned int S = (given & 0x04000000u) >> 26; unsigned int J1 = (given & 0x00002000u) >> 13; unsigned int J2 = (given & 0x00000800u) >> 11; - int offset = 0; + bfd_vma offset = 0; offset |= !S << 20; offset |= J2 << 19; @@ -3627,7 +4308,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned int S = (given & 0x04000000u) >> 26; unsigned int I1 = (given & 0x00002000u) >> 13; unsigned int I2 = (given & 0x00000800u) >> 11; - int offset = 0; + bfd_vma offset = 0; offset |= !S << 24; offset |= !(I1 ^ S) << 23; @@ -3648,9 +4329,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 's': { unsigned int shift = 0; + shift |= (given & 0x000000c0u) >> 6; shift |= (given & 0x00007000u) >> 10; - if (given & 0x00200000u) + if (WRITEBACK_BIT_SET) func (stream, ", asr #%u", shift); else if (shift) func (stream, ", lsl #%u", shift); @@ -3661,22 +4343,31 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case 'R': { unsigned int rot = (given & 0x00000030) >> 4; + if (rot) func (stream, ", ror #%u", rot * 8); } break; case 'U': - switch (given & 0xf) + if ((given & 0xf0) == 0x60) { - case 0xf: func(stream, "sy"); break; - case 0x7: func(stream, "un"); break; - case 0xe: func(stream, "st"); break; - case 0x6: func(stream, "unst"); break; - default: - func(stream, "#%d", (int)given & 0xf); - break; + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } } + else + { + const char * opt = data_barrier_option (given & 0xf); + if (opt != NULL) + func (stream, "%s", opt); + else + func (stream, "#%d", (int) given & 0xf); + } break; case 'C': @@ -3692,17 +4383,44 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) if (given & 0x100) func (stream, "c"); } + else if ((given & 0x20) == 0x20) + { + char const* name; + unsigned sysm = (given & 0xf00) >> 8; + + sysm |= (given & 0x30); + sysm |= (given & 0x00100000) >> 14; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } else { - func (stream, psr_name (given & 0xff)); + func (stream, "%s", psr_name (given & 0xff)); } break; case 'D': - if ((given & 0xff) == 0) - func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C'); + if (((given & 0xff) == 0) + || ((given & 0x20) == 0x20)) + { + char const* name; + unsigned sm = (given & 0xf0000) >> 16; + + sm |= (given & 0x30); + sm |= (given & 0x00100000) >> 14; + name = banked_regname (sm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sm); + } else - func (stream, psr_name (given & 0xff)); + func (stream, "%s", psr_name (given & 0xff)); break; case '0': case '1': case '2': case '3': case '4': @@ -3715,9 +4433,27 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) switch (*c) { - case 'd': func (stream, "%lu", val); break; - case 'W': func (stream, "%lu", val * 4); break; - case 'r': func (stream, "%s", arm_regnames[val]); break; + case 'd': + func (stream, "%lu", val); + value_in_comment = val; + break; + + case 'W': + func (stream, "%lu", val * 4); + value_in_comment = val * 4; + break; + + case 'S': + if (val == 13) + is_unpredictable = TRUE; + /* Fall through. */ + case 'R': + if (val == 15) + is_unpredictable = TRUE; + /* Fall through. */ + case 'r': + func (stream, "%s", arm_regnames[val]); + break; case 'c': func (stream, "%s", arm_conditional[val]); @@ -3736,9 +4472,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) break; case '?': - func (stream, "%c", c[(1 << width) - (int)val]); + func (stream, "%c", c[(1 << width) - (int) val]); c += 1 << width; break; + + case 'x': + func (stream, "0x%lx", val & 0xffffffffUL); + break; default: abort (); @@ -3746,10 +4486,32 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'L': + /* PR binutils/12534 + If we have a PC relative offset in an LDRD or STRD + instructions then display the decoded address. */ + if (((given >> 16) & 0xf) == 0xf) + { + bfd_vma offset = (given & 0xff) * 4; + + if ((given & (1 << 23)) == 0) + offset = - offset; + func (stream, "\t; "); + info->print_address_func ((pc & ~3) + 4 + offset, info); + } + break; + default: abort (); } } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", value_in_comment); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + return; } @@ -3760,7 +4522,8 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) /* Print data bytes on INFO->STREAM. */ static void -print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info, +print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, + struct disassemble_info *info, long given) { switch (info->bytes_per_chunk) @@ -3856,8 +4619,10 @@ parse_disassembler_options (char *options) /* Search back through the insn stream to determine if this instruction is conditionally executed. */ + static void -find_ifthen_state (bfd_vma pc, struct disassemble_info *info, +find_ifthen_state (bfd_vma pc, + struct disassemble_info *info, bfd_boolean little) { unsigned char b[2]; @@ -3882,7 +4647,7 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info, IT instruction until we find a definite instruction boundary. */ for (;;) { - if (addr == 0 || info->symbol_at_address_func(addr, info)) + if (addr == 0 || info->symbol_at_address_func (addr, info)) { /* A symbol must be on an instruction boundary, and will not be within an IT block. */ @@ -3892,7 +4657,7 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info, return; } addr -= 2; - status = info->read_memory_func (addr, (bfd_byte *)b, 2, info); + status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); if (status) return; @@ -3932,41 +4697,115 @@ find_ifthen_state (bfd_vma pc, struct disassemble_info *info, ifthen_state = 0; } -/* Try to infer the code type (Arm or Thumb) from a symbol. +/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a + mapping symbol. */ + +static int +is_mapping_symbol (struct disassemble_info *info, int n, + enum map_type *map_type) +{ + const char *name; + + name = bfd_asymbol_name (info->symtab[n]); + if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') + && (name[2] == 0 || name[2] == '.')) + { + *map_type = ((name[1] == 'a') ? MAP_ARM + : (name[1] == 't') ? MAP_THUMB + : MAP_DATA); + return TRUE; + } + + return FALSE; +} + +/* Try to infer the code type (ARM or Thumb) from a mapping symbol. + Returns nonzero if *MAP_TYPE was set. */ + +static int +get_map_sym_type (struct disassemble_info *info, + int n, + enum map_type *map_type) +{ + /* If the symbol is in a different section, ignore it. */ + if (info->section != NULL && info->section != info->symtab[n]->section) + return FALSE; + + return is_mapping_symbol (info, n, map_type); +} + +/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. Returns nonzero if *MAP_TYPE was set. */ static int -get_sym_code_type (struct disassemble_info *info, int n, +get_sym_code_type (struct disassemble_info *info, + int n, enum map_type *map_type) { elf_symbol_type *es; unsigned int type; - const char *name; + + /* If the symbol is in a different section, ignore it. */ + if (info->section != NULL && info->section != info->symtab[n]->section) + return FALSE; es = *(elf_symbol_type **)(info->symtab + n); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); /* If the symbol has function type then use that. */ - if (type == STT_FUNC || type == STT_ARM_TFUNC) + if (type == STT_FUNC || type == STT_GNU_IFUNC) { - *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM; + if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB) + *map_type = MAP_THUMB; + else + *map_type = MAP_ARM; return TRUE; } - /* Check for mapping symbols. */ - name = bfd_asymbol_name(info->symtab[n]); - if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') - && (name[2] == 0 || name[2] == '.')) + return FALSE; +} + +/* Given a bfd_mach_arm_XXX value, this function fills in the fields + of the supplied arm_feature_set structure with bitmasks indicating + the support base architectures and coprocessor extensions. + + FIXME: This could more efficiently implemented as a constant array, + although it would also be less robust. */ + +static void +select_arm_features (unsigned long mach, + arm_feature_set * features) +{ +#undef ARM_FEATURE +#define ARM_FEATURE(ARCH,CEXT) \ + features->core = (ARCH); \ + features->coproc = (CEXT) | FPU_FPA; \ + return + + switch (mach) { - *map_type = ((name[1] == 'a') ? MAP_ARM - : (name[1] == 't') ? MAP_THUMB - : MAP_DATA); - return TRUE; + case bfd_mach_arm_2: ARM_ARCH_V2; + case bfd_mach_arm_2a: ARM_ARCH_V2S; + case bfd_mach_arm_3: ARM_ARCH_V3; + case bfd_mach_arm_3M: ARM_ARCH_V3M; + case bfd_mach_arm_4: ARM_ARCH_V4; + case bfd_mach_arm_4T: ARM_ARCH_V4T; + case bfd_mach_arm_5: ARM_ARCH_V5; + case bfd_mach_arm_5T: ARM_ARCH_V5T; + case bfd_mach_arm_5TE: ARM_ARCH_V5TE; + case bfd_mach_arm_XScale: ARM_ARCH_XSCALE; + case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK); + case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT; + case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2; + /* If the machine type is unknown allow all + architecture types and all extensions. */ + case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL); + default: + abort (); } - - return FALSE; } + /* NOTE: There are no checks in these routines that the relevant number of data bytes exist. */ @@ -3982,6 +4821,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) unsigned int size = 4; void (*printer) (bfd_vma, struct disassemble_info *, long); bfd_boolean found = FALSE; + struct arm_private_data *private_data; if (info->disassembler_options) { @@ -3991,69 +4831,173 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) info->disassembler_options = NULL; } + /* PR 10288: Control which instructions will be disassembled. */ + if (info->private_data == NULL) + { + static struct arm_private_data private; + + if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) + /* If the user did not use the -m command line switch then default to + disassembling all types of ARM instruction. + + The info->mach value has to be ignored as this will be based on + the default archictecture for the target and/or hints in the notes + section, but it will never be greater than the current largest arm + machine value (iWMMXt2), which is only equivalent to the V5TE + architecture. ARM architectures have advanced beyond the machine + value encoding, and these newer architectures would be ignored if + the machine value was used. + + Ie the -m switch is used to restrict which instructions will be + disassembled. If it is necessary to use the -m switch to tell + objdump that an ARM binary is being disassembled, eg because the + input is a raw binary file, but it is also desired to disassemble + all ARM instructions then use "-marm". This will select the + "unknown" arm architecture which is compatible with any ARM + instruction. */ + info->mach = bfd_mach_arm_unknown; + + /* Compute the architecture bitmask from the machine number. + Note: This assumes that the machine number will not change + during disassembly.... */ + select_arm_features (info->mach, & private.features); + + private.has_mapping_symbols = -1; + private.last_mapping_sym = -1; + private.last_mapping_addr = 0; + + info->private_data = & private; + } + + private_data = info->private_data; + /* Decide if our code is going to be little-endian, despite what the function argument might say. */ little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); - /* First check the full symtab for a mapping symbol, even if there - are no usable non-mapping symbols for this address. */ - if (info->symtab != NULL - && * info->symtab + /* For ELF, consult the symbol table to determine what kind of code + or data we have. */ + if (info->symtab_size != 0 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) { bfd_vma addr; - int n; + int n, start; int last_sym = -1; enum map_type type = MAP_ARM; - if (pc <= last_mapping_addr) - last_mapping_sym = -1; - is_thumb = (last_type == MAP_THUMB); - found = FALSE; /* Start scanning at the start of the function, or wherever we finished last time. */ - n = info->symtab_pos + 1; - if (n < last_mapping_sym) - n = last_mapping_sym; + /* PR 14006. When the address is 0 we are either at the start of the + very first function, or else the first function in a new, unlinked + executable section (eg because uf -ffunction-sections). Either way + start scanning from the beginning of the symbol table, not where we + left off last time. */ + if (pc == 0) + start = 0; + else + { + start = info->symtab_pos + 1; + if (start < private_data->last_mapping_sym) + start = private_data->last_mapping_sym; + } + found = FALSE; - /* Scan up to the location being disassembled. */ - for (; n < info->symtab_size; n++) + /* First, look for mapping symbols. */ + if (private_data->has_mapping_symbols != 0) { - addr = bfd_asymbol_value (info->symtab[n]); - if (addr > pc) - break; - if ((info->section == NULL - || info->section == info->symtab[n]->section) - && get_sym_code_type (info, n, &type)) + /* Scan up to the location being disassembled. */ + for (n = start; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + } + } + + if (!found) + { + /* No mapping symbol found at this address. Look backwards + for a preceding one. */ + for (n = start - 1; n >= 0; n--) + { + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } + } + } + + if (found) + private_data->has_mapping_symbols = 1; + + /* No mapping symbols were found. A leading $d may be + omitted for sections which start with data; but for + compatibility with legacy and stripped binaries, only + assume the leading $d if there is at least one mapping + symbol in the file. */ + if (!found && private_data->has_mapping_symbols == -1) + { + /* Look for mapping symbols, in any section. */ + for (n = 0; n < info->symtab_size; n++) + if (is_mapping_symbol (info, n, &type)) + { + private_data->has_mapping_symbols = 1; + break; + } + if (private_data->has_mapping_symbols == -1) + private_data->has_mapping_symbols = 0; + } + + if (!found && private_data->has_mapping_symbols == 1) { - last_sym = n; + type = MAP_DATA; found = TRUE; } } + /* Next search for function symbols to separate ARM from Thumb + in binaries without mapping symbols. */ if (!found) { - n = info->symtab_pos; - if (n < last_mapping_sym - 1) - n = last_mapping_sym - 1; - - /* No mapping symbol found at this address. Look backwards - for a preceeding one. */ - for (; n >= 0; n--) + /* Scan up to the location being disassembled. */ + for (n = start; n < info->symtab_size; n++) { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; if (get_sym_code_type (info, n, &type)) { last_sym = n; found = TRUE; - break; + } + } + + if (!found) + { + /* No mapping symbol found at this address. Look backwards + for a preceding one. */ + for (n = start - 1; n >= 0; n--) + { + if (get_sym_code_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } } } } - last_mapping_sym = last_sym; - last_type = type; - is_thumb = (last_type == MAP_THUMB); - is_data = (last_type == MAP_DATA); + private_data->last_mapping_sym = last_sym; + private_data->last_type = type; + is_thumb = (private_data->last_type == MAP_THUMB); + is_data = (private_data->last_type == MAP_DATA); /* Look a little bit ahead to see if we should print out two or four bytes of data. If there's a symbol, @@ -4065,7 +5009,9 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) for (n = last_sym + 1; n < info->symtab_size; n++) { addr = bfd_asymbol_value (info->symtab[n]); - if (addr > pc) + if (addr > pc + && (info->section == NULL + || info->section == info->symtab[n]->section)) { if (addr - pc < size) size = addr - pc; @@ -4104,25 +5050,32 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) es = *(elf_symbol_type **)(info->symbols); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); + is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) + == ST_BRANCH_TO_THUMB) + || type == STT_ARM_16BIT); } } if (force_thumb) is_thumb = TRUE; - info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + if (is_data) + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + else + info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + info->bytes_per_line = 4; - if (is_data) + /* PR 10263: Disassemble data if requested to do so by the user. */ + if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) { int i; - /* size was already set above. */ + /* Size was already set above. */ info->bytes_per_chunk = size; printer = print_insn_data; - status = info->read_memory_func (pc, (bfd_byte *)b, size, info); + status = info->read_memory_func (pc, (bfd_byte *) b, size, info); given = 0; if (little) for (i = size - 1; i >= 0; i--) @@ -4139,7 +5092,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) info->bytes_per_chunk = 4; size = 4; - status = info->read_memory_func (pc, (bfd_byte *)b, 4, info); + status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); if (little_code) given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); else @@ -4155,7 +5108,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) info->bytes_per_chunk = 2; size = 2; - status = info->read_memory_func (pc, (bfd_byte *)b, 2, info); + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); if (little_code) given = (b[0]) | (b[1] << 8); else @@ -4169,7 +5122,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) || (given & 0xF800) == 0xF000 || (given & 0xF800) == 0xE800) { - status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info); + status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); if (little_code) given = (b[0]) | (b[1] << 8) | (given << 16); else @@ -4181,7 +5134,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) } if (ifthen_address != pc) - find_ifthen_state(pc, info, little_code); + find_ifthen_state (pc, info, little_code); if (ifthen_state) { @@ -4250,5 +5203,5 @@ the -M switch:\n")); regnames[i].description); fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); - fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); + fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n"); }