X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Farm-dis.c;h=55ec321bedf6a2e3beb6ff7b08cf93213f1b9d50;hb=cc6aa1a6e0a8f2b3eda496aef0b3579a8c2b5951;hp=85c573034ea1e149eecbbe73eb705945040448d9;hpb=33593eafc92b6376a71bef49f5cebd6e09abd283;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 85c573034e..55ec321bed 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1,5 +1,5 @@
 /* Instruction printing code for the ARM
-   Copyright (C) 1994-2019 Free Software Foundation, Inc.
+   Copyright (C) 1994-2020 Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    Modification by James G. Smith (jsmith@cygnus.co.uk)
 
@@ -396,6 +396,7 @@ struct opcode16
    %%			%
 
    %c			print condition code (always bits 28-31 in ARM mode)
+   %b			print condition code allowing cp_num == 9
    %q			print shifter argument
    %u			print condition code (unconditional in ARM mode,
                           UNPREDICTABLE if not AL in Thumb)
@@ -1207,11 +1208,15 @@ static const struct sopcode32 coprocessor_opcodes[] =
   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 
+  /* BFloat16 instructions.  */
+  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+    0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
+
   /* Dot Product instructions in the space of coprocessor 13.  */
   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
-    0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
+    0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 
   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
@@ -1452,6 +1457,34 @@ static const struct opcode32 neon_opcodes[] =
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
 
+  /* BFloat16 instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+    0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+    0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+    0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+    0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+    0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
+    0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
+
+  /* Matrix Multiply instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+    0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+    0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+    0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+    0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+    0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+    0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+
   /* Two registers, miscellaneous.  */
   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
@@ -2809,10 +2842,15 @@ static const struct mopcode32 mve_opcodes[] =
    "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
 
   /* Vector VMOV immediate to vector,
-     cmode == 11x1 -> VMVN which is UNDEFINED
-     for such a cmode.  */
+     undefinded for cmode == 1111 */
   {ARM_FEATURE_COPROC (FPU_MVE),
-   MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
+   MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
+
+  /* Vector VMOV immediate to vector,
+     cmode == 1101 */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
+   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
 
   /* Vector VMOV immediate to vector.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
@@ -3603,17 +3641,17 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
   /* CRC32 instructions.  */
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
 
   /* Privileged Access Never extension instructions.  */
@@ -4619,17 +4657,17 @@ static const struct opcode32 thumb32_opcodes[] =
     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
 
   /* CRC32 instructions.  */
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
 
   /* Speculation Barriers.  */
@@ -5631,11 +5669,11 @@ is_mve_encoding_conflict (unsigned long given,
       {
 	unsigned long cmode = arm_decode_field (given, 8, 11);
 
-	if ((cmode & 9) == 1)
+	if (cmode == 0xe)
 	  return TRUE;
-	else if ((cmode & 5) == 1)
+	else if ((cmode & 0x9) == 1)
 	  return TRUE;
-	else if ((cmode & 0xe) == 0xe)
+	else if ((cmode & 0xd) == 9)
 	  return TRUE;
 	else
 	  return FALSE;
@@ -8159,6 +8197,8 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
 		  if (cond != COND_UNCOND && cp_num == 9)
 		    is_unpredictable = TRUE;
 
+		  /* Fall through.  */
+		case 'b':
 		  func (stream, "%s", arm_conditional[cond]);
 		  break;
 
@@ -8772,6 +8812,10 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
 	}
       else if ((given & 0xff000000) == 0xf9000000)
 	given ^= 0xf9000000 ^ 0xf4000000;
+      /* BFloat16 neon instructions without special top byte handling.  */
+      else if ((given & 0xff000000) == 0xfe000000
+	       || (given & 0xff000000) == 0xfc000000)
+	;
       /* vdup is also a valid neon instruction.  */
       else if ((given & 0xff910f5f) != 0xee800b10)
 	return FALSE;
@@ -9883,12 +9927,12 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
 			  unsigned int immed = (given & 0xff);
 			  unsigned int a, i;
 
-			  a = (((immed << (32 - rotate))
-				| (immed >> rotate)) & 0xffffffff);
+			  a = (immed << ((32 - rotate) & 31)
+			       | immed >> rotate) & 0xffffffff;
 			  /* If there is another encoding with smaller rotate,
 			     the rotate should be specified directly.  */
 			  for (i = 0; i < 32; i += 2)
-			    if ((a << i | a >> (32 - i)) <= 0xff)
+			    if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
 			      break;
 
 			  if (i != rotate)
@@ -11625,11 +11669,11 @@ select_arm_features (unsigned long mach,
     case bfd_mach_arm_7EM:	 ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
     case bfd_mach_arm_8:
 	{
-	  /* Add bits for extensions that Armv8.5-A recognizes.  */
-	  arm_feature_set armv8_5_ext_fset
+	  /* Add bits for extensions that Armv8.6-A recognizes.  */
+	  arm_feature_set armv8_6_ext_fset
 	    = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
-	  ARM_SET_FEATURES (ARM_ARCH_V8_5A);
-	  ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
+	  ARM_SET_FEATURES (ARM_ARCH_V8_6A);
+	  ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
 	  break;
 	}
     case bfd_mach_arm_8R:	 ARM_SET_FEATURES (ARM_ARCH_V8R); break;
@@ -11661,7 +11705,7 @@ static int
 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
 {
   unsigned char b[4];
-  long		given;
+  unsigned long given;
   int           status;
   int           is_thumb = FALSE;
   int           is_data = FALSE;
@@ -11841,9 +11885,9 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
 
       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
       if (little_code)
-	given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
+	given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
       else
-	given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
+	given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
     }
   else
     {