X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Farm-opc.h;h=213d4f034dec15c20037035c0086663753c94557;hb=a3e64b75ca58524a4bda89ba15e747f5e3a54993;hp=34d3b309fe89d1dce216fb1f62481e5d31594c9b;hpb=395213c84649cdb5bf4f690896a1e3042fb2573d;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h index 34d3b309fe..213d4f034d 100644 --- a/opcodes/arm-opc.h +++ b/opcodes/arm-opc.h @@ -51,7 +51,6 @@ struct thumb_opcode %?ab print a if bit is one else print b %p print 'p' iff bits 12-15 are 15 %t print 't' iff bit 21 set and bit 24 clear - %h print 'h' iff bit 5 set, else print 'b' %o print operand2 (immediate or register + shift) %a print address for ldr/str instruction %s print address for ldr/str halfword/signextend instruction @@ -80,7 +79,7 @@ Thumb specific format options: /* Note: There is a partial ordering in this table - it must be searched from the top to obtain a correct match. */ -static struct arm_opcode arm_opcodes[] = +static const struct arm_opcode arm_opcodes[] = { /* ARM instructions. */ {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, @@ -146,8 +145,8 @@ static struct arm_opcode arm_opcodes[] = {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, /* ARM Instructions. */ - {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, - {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, + {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, + {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, @@ -396,7 +395,7 @@ static struct arm_opcode arm_opcodes[] = #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ -static struct thumb_opcode thumb_opcodes[] = +static const struct thumb_opcode thumb_opcodes[] = { /* Thumb instructions. */