X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fcgen-asm.in;h=1c43b142ce48b4e1d724bb1ab1b859daa7f3f772;hb=1d61b032265e69317f42e8019e072506f11890c5;hp=8a5099b4ed7c965359536f2a08b44df85cf9a62e;hpb=bfc10abe47d82b1c6d10070a69b5e6fc11f0d311;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in index 8a5099b4ed..1c43b142ce 100644 --- a/opcodes/cgen-asm.in +++ b/opcodes/cgen-asm.in @@ -1,125 +1,174 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -This file is used to generate @arch@-asm.c. + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Copyright (C) 1996-2019 Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of libopcodes. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ #include "sysdep.h" -#include #include #include "ansidecl.h" #include "bfd.h" -#include "@arch@-opc.h" - -/* ??? The layout of this stuff is still work in progress. - For speed in assembly/disassembly, we use inline functions. That of course - will only work for GCC. When this stuff is finished, we can decide whether - to keep the inline functions (and only get the performance increase when - compiled with GCC), or switch to macros, or use something else. -*/ - -static const char *parse_insn_normal - PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *)); -static void insert_insn_normal - PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *)); +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); -/* Default insertion routine. - - SHIFT is negative for left shifts, positive for right shifts. - All bits of VALUE to be inserted must be valid as we don't handle - signed vs unsigned shifts. - - ATTRS is a mask of the boolean attributes. We don't need any at the - moment, but for consistency with extract_normal we have them. */ - -/* FIXME: This duplicates functionality with bfd's howto table and - bfd_install_relocation. */ -/* FIXME: For architectures where insns can be representable as ints, - store insn in `field' struct and add registers, etc. while parsing. */ - -static CGEN_INLINE void -insert_normal (value, attrs, start, length, shift, total_length, buffer) - long value; - unsigned int attrs; - int start, length, shift, total_length; - char *buffer; +/* -- assembler routines inserted here. */ + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by @arch@_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +@arch@_cgen_build_insn_regex (CGEN_INSN *insn) { - bfd_vma x; + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; -#if 0 /*def CGEN_INT_INSN*/ - *buffer |= ((value & ((1 << length) - 1)) - << (total_length - (start + length))); -#else - switch (total_length) + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) { - case 8: - x = *(unsigned char *) buffer; - break; - case 16: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - x = bfd_getb16 (buffer); + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } else - x = bfd_getl16 (buffer); - break; - case 32: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - x = bfd_getb32 (buffer); + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } else - x = bfd_getl32 (buffer); - break; - default : - abort (); + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } } - if (shift < 0) - value <<= -shift; - else - value >>= shift; + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; - x |= ((value & ((1 << length) - 1)) - << (total_length - (start + length))); + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; - switch (total_length) + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else { - case 8: - *buffer = value; - break; - case 16: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - bfd_putb16 (x, buffer); - else - bfd_putl16 (x, buffer); - break; - case 32: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - bfd_putb32 (x, buffer); - else - bfd_putl32 (x, buffer); - break; - default : - abort (); + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; } -#endif } - -/* -- assembler routines inserted here */ + /* Default insn parser. @@ -132,263 +181,254 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer) but that can be handled there. Not handling backtracking here may get expensive in the case of the m68k. Deal with later. - Returns NULL for success, an error message for failure. -*/ + Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (insn, strp, fields) - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { + /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const char *str = *strp; const char *errmsg; const char *p; - const unsigned char *syn; + const CGEN_SYNTAX_CHAR_TYPE * syn; #ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ int past_opcode_p; #endif /* For now we assume the mnemonic is first (there are no leading operands). - We can parse it without needing to set up operand parsing. */ + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ p = CGEN_INSN_MNEMONIC (insn); - while (*p && *p == *str) + while (*p && TOLOWER (*p) == TOLOWER (*str)) ++p, ++str; - if (*p || (*str && !isspace (*str))) - return "unrecognized instruction"; - CGEN_INIT_PARSE (); - cgen_init_parse_operand (); + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); #ifdef CGEN_MNEMONIC_OPERANDS past_opcode_p = 0; #endif /* We don't check for (*str != '\0') here because we want to parse any trailing fake arguments in the syntax string. */ - syn = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn)); + syn = CGEN_SYNTAX_STRING (syntax); + /* Mnemonics come first for now, ensure valid string. */ - if (! CGEN_SYNTAX_MNEMONIC_P (*syn)) + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) abort (); + ++syn; - while (*syn != 0) + + while (* syn != 0) { /* Non operand chars must match exactly. */ - /* FIXME: Need to better handle whitespace. */ - if (CGEN_SYNTAX_CHAR_P (*syn)) + if (CGEN_SYNTAX_CHAR_P (* syn)) { - if (*str == CGEN_SYNTAX_CHAR (*syn)) + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS - if (*syn == ' ') + if (CGEN_SYNTAX_CHAR(* syn) == ' ') past_opcode_p = 1; #endif - ++syn; - ++str; + ++ syn; + ++ str; } - else + else if (*str) { /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return "expected char `c'" */ - return "syntax error"; + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; } continue; } +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif /* We have an operand of some sort. */ - errmsg = @arch@_cgen_parse_operand (CGEN_SYNTAX_FIELD (*syn), - &str, fields); + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); if (errmsg) return errmsg; /* Done with this operand, continue with next one. */ - ++syn; + ++ syn; } /* If we're at the end of the syntax string, we're done. */ - if (*syn == '\0') + if (* syn == 0) { /* FIXME: For the moment we assume a valid `str' can only contain blanks now. IE: We needn't try again with a longer version of the insn and it is assumed that longer versions of insns appear before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (isspace (*str)) - ++str; + while (ISSPACE (* str)) + ++ str; - if (*str != '\0') - return "junk at end of line"; /* FIXME: would like to include `str' */ + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ return NULL; } /* We couldn't parse it. */ - return "unrecognized instruction"; -} - -/* Default insn builder (insert handler). - The instruction is recorded in target byte order. */ - -static void -insert_insn_normal (insn, fields, buffer) - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - cgen_insn_t *buffer; -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - bfd_vma value; - const unsigned char *syn; - - CGEN_INIT_INSERT (); - value = CGEN_INSN_VALUE (insn); - - /* If we're recording insns as numbers (rather than a string of bytes), - target byte order handling is deferred until later. */ -#undef min -#define min(a,b) ((a) < (b) ? (a) : (b)) -#if 0 /*def CGEN_INT_INSN*/ - *buffer = value; -#else - switch (min (CGEN_BASE_INSN_BITSIZE, CGEN_FIELDS_BITSIZE (fields))) - { - case 8: - *buffer = value; - break; - case 16: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - bfd_putb16 (value, (char *) buffer); - else - bfd_putl16 (value, (char *) buffer); - break; - case 32: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - bfd_putb32 (value, (char *) buffer); - else - bfd_putl32 (value, (char *) buffer); - break; - default: - abort (); - } -#endif - - /* ??? Rather than scanning the syntax string again, we could store - in `fields' a null terminated list of the fields that are present. */ - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn != '\0'; ++syn) - { - if (CGEN_SYNTAX_CHAR_P (*syn)) - continue; - - @arch@_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, buffer); - } + return _("unrecognized instruction"); } /* Main entry point. This routine is called for each instruction to be assembled. STR points to the insn to be assembled. We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. The result is a pointer to the insn's entry in the opcode table, or NULL if an error occured (an error message will have already been - printed). */ + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ const CGEN_INSN * -@arch@_cgen_assemble_insn (str, fields, buf, errmsg) - const char *str; - CGEN_FIELDS *fields; - cgen_insn_t *buf; - char **errmsg; +@arch@_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; /* Skip leading white space. */ - while (isspace (*str)) - ++str; + while (ISSPACE (* str)) + ++ str; /* The instructions are stored in hashed lists. Get the first in the list. */ - ilist = CGEN_ASM_LOOKUP_INSN (str); + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); /* Keep looking until we find a match. */ - start = str; for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) { const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; -#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ /* Is this insn supported by the selected cpu? */ - if (! @arch@_cgen_insn_supported (insn)) + if (! @arch@_cgen_insn_supported (cd, insn)) continue; #endif - -#if 1 /* FIXME: wip */ - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; -#endif str = start; - /* Record a default length for the insn. This will get set to the - correct value while parsing. */ - /* FIXME: wip */ + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - /* ??? The extent to which moving the parse and insert handlers into - this function (thus removing the function call) will speed things up - is unclear. The simplicity and flexibility of the current scheme is - appropriate for now. One could have the best of both worlds with - inline functions but of course that would only work for gcc. Since - we're machine generating some code we could do that here too. Maybe - later. */ - if (! (*CGEN_PARSE_FN (insn)) (insn, &str, fields)) - { - (*CGEN_INSERT_FN (insn)) (insn, fields, buf); - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; - /* Try the next entry. */ + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; } - /* FIXME: We can return a better error message than this. - Need to track why it failed and pick the right one. */ { - static char errbuf[100]; - sprintf (errbuf, "bad instruction `%.50s%s'", - start, strlen (start) > 50 ? "..." : ""); + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + *errmsg = errbuf; return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -@arch@_cgen_asm_hash_keywords (opvals) - CGEN_KEYWORD *opvals; -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY *ke; - - while ((ke = cgen_keyword_search_next (&search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! @arch@_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (ke->name, ke->value); - } -} - -#endif /* 0 */