X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fcr16-opc.c;h=18753792230ef8714e0da4c7e8e70ab2c82fa429;hb=5d9310c4b88f807c1a3f1a0b4d7b6c10925dcaf7;hp=081c63d8206485f2664af96dd2576285371a7457;hpb=9b201bb5e5daa9b4f783e6ece9cbfbdbf9f1d6f4;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/cr16-opc.c b/opcodes/cr16-opc.c
index 081c63d820..1875379223 100644
--- a/opcodes/cr16-opc.c
+++ b/opcodes/cr16-opc.c
@@ -1,5 +1,5 @@
 /* cr16-opc.c -- Table of opcodes for the CR16 processor.
-   Copyright 2007 Free Software Foundation, Inc.
+   Copyright (C) 2007-2018 Free Software Foundation, Inc.
    Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com)
 
    This file is part of the GNU opcodes library.
@@ -34,7 +34,7 @@ const inst cr16_instruction[] =
   /* opc8 r r */                                                     \
   {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
 
-/* for Logincal operations, allow unsinged imm16 also */
+/* For Logical operations, allow unsigned imm16 also.  */
 #define  ARITH1_BYTE_INST(NAME, OPC, OP1)                            \
   /* opc8 imm16 r */                                                 \
   {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}
@@ -160,11 +160,11 @@ const inst cr16_instruction[] =
 /* Create a conditional branch instruction.  */
 #define  BRANCH_INST(NAME, OPC)                                       \
   /* opc4 c4 dispe9 */                                                \
-  {NAME,  1, OPC, 28, BRANCH_INS, {{cc,20}, {dispe9,16}}},            \
+  {NAME,  1, OPC, 28, BRANCH_INS | RELAXABLE, {{cc,20}, {dispe9,16}}},\
   /* opc4 c4 disps17 */                                               \
-  {NAME,  2, ((OPC<<4)+0x8), 24, BRANCH_INS, {{cc,20}, {disps17,0}}}, \
+  {NAME,  2, ((OPC<<4)+0x8), 24, BRANCH_INS | RELAXABLE, {{cc,20}, {disps17,0}}},\
   /* opc4 c4 disps25 */                                               \
-  {NAME,  3, (OPC<<4), 16 , BRANCH_INS, {{cc,4}, {disps25,16}}}
+  {NAME,  3, (OPC<<4), 16 , BRANCH_INS | RELAXABLE, {{cc,4}, {disps25,16}}}
 
   BRANCH_INST ("b", 0x1),
 
@@ -459,8 +459,11 @@ const unsigned int cr16_num_opcodes = ARRAY_SIZE (cr16_instruction);
    For example :
       REG(u4, 0x84, CR16_U_REGTYPE)
    is interpreted as :
-      {"u4",  u4, 0x84, CR16_U_REGTYPE}  */
-#define REG(NAME, N, TYPE)    {STRINGX(NAME), {NAME}, N, TYPE}
+      {"u4",  u4, 0x84, CR16_U_REGTYPE}
+   The union initializer (second member) always refers to the first
+   member of the union, so cast NAME to that type to avoid possible
+   compiler warnings when used for CR16_P_REGTYPE cases.  */
+#define REG(NAME, N, TYPE)    {STRINGX(NAME), {(reg) NAME}, N, TYPE}
 
 #define REGP(NAME, BNAME, N, TYPE)    {STRINGX(NAME), {BNAME}, N, TYPE}
 
@@ -593,6 +596,7 @@ const operand_entry cr16_optab[] =
   {4,    arg_cc,       OP_UNSIGNED}               /* cc - code */
 };
 
+const unsigned int cr16_num_optab = ARRAY_SIZE (cr16_optab);
 
 /* CR16 traps/interrupts.  */
 const trap_entry cr16_traps[] =