X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fcr16-opc.c;h=220813a3a94c790acb9dd8327cd6ba1ba77fb37f;hb=3f06e55061d0d8f72dfd11f6c432c23f45d9b597;hp=8b8bf2f421ed28d9990205cfcdc5735b2f6270c5;hpb=3d3d428f048cd724b634cb0252dd187f3fabc627;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/cr16-opc.c b/opcodes/cr16-opc.c index 8b8bf2f421..220813a3a9 100644 --- a/opcodes/cr16-opc.c +++ b/opcodes/cr16-opc.c @@ -1,18 +1,18 @@ /* cr16-opc.c -- Table of opcodes for the CR16 processor. - Copyright 2007 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com) - This file is part of GAS, GDB and the GNU binutils. + This file is part of the GNU opcodes library. - GAS, GDB, and GNU binutils is free software; you can redistribute it - and/or modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2, or (at your - option) any later version. + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. - GAS, GDB, and GNU binutils are distributed in the hope that they will be - useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, @@ -34,7 +34,7 @@ const inst cr16_instruction[] = /* opc8 r r */ \ {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} -/* for Logincal operations, allow unsinged imm16 also */ +/* For Logical operations, allow unsigned imm16 also. */ #define ARITH1_BYTE_INST(NAME, OPC, OP1) \ /* opc8 imm16 r */ \ {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}} @@ -160,11 +160,11 @@ const inst cr16_instruction[] = /* Create a conditional branch instruction. */ #define BRANCH_INST(NAME, OPC) \ /* opc4 c4 dispe9 */ \ - {NAME, 1, OPC, 28, BRANCH_INS, {{cc,20}, {dispe9,16}}}, \ + {NAME, 1, OPC, 28, BRANCH_INS | RELAXABLE, {{cc,20}, {dispe9,16}}},\ /* opc4 c4 disps17 */ \ - {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS, {{cc,20}, {disps17,0}}}, \ + {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS | RELAXABLE, {{cc,20}, {disps17,0}}},\ /* opc4 c4 disps25 */ \ - {NAME, 3, (OPC<<4), 16 , BRANCH_INS, {{cc,4}, {disps25,16}}} + {NAME, 3, (OPC<<4), 16 , BRANCH_INS | RELAXABLE, {{cc,4}, {disps25,16}}} BRANCH_INST ("b", 0x1), @@ -459,8 +459,11 @@ const unsigned int cr16_num_opcodes = ARRAY_SIZE (cr16_instruction); For example : REG(u4, 0x84, CR16_U_REGTYPE) is interpreted as : - {"u4", u4, 0x84, CR16_U_REGTYPE} */ -#define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} + {"u4", u4, 0x84, CR16_U_REGTYPE} + The union initializer (second member) always refers to the first + member of the union, so cast NAME to that type to avoid possible + compiler warnings when used for CR16_P_REGTYPE cases. */ +#define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} #define REGP(NAME, BNAME, N, TYPE) {STRINGX(NAME), {BNAME}, N, TYPE} @@ -593,6 +596,7 @@ const operand_entry cr16_optab[] = {4, arg_cc, OP_UNSIGNED} /* cc - code */ }; +const unsigned int cr16_num_optab = ARRAY_SIZE (cr16_optab); /* CR16 traps/interrupts. */ const trap_entry cr16_traps[] =