X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fd10v-dis.c;h=a3423bccc4215e4986c11929c00fca93e60a1495;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=31ce5265076c393b11fea691b103815d8355b930;hpb=2dcee5388a24b78dfaa9a0bbe9ae235b4181d5c4;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/d10v-dis.c b/opcodes/d10v-dis.c index 31ce526507..a3423bccc4 100644 --- a/opcodes/d10v-dis.c +++ b/opcodes/d10v-dis.c @@ -1,78 +1,38 @@ /* Disassemble D10V instructions. - Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 1996-2020 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This file is part of the GNU opcodes library. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -#include + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" +#include #include "opcode/d10v.h" -#include "dis-asm.h" +#include "disassemble.h" /* The PC wraps at 18 bits, except for the segment number, so use this mask to keep the parts we want. */ #define PC_MASK 0x0303FFFF -static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr, - struct disassemble_info *info, int order)); -static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr, - struct disassemble_info *info)); - -int -print_insn_d10v (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[4]; - unsigned long insn; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb32 (buffer); - - status = insn & FM11; - switch (status) - { - case 0: - dis_2_short (insn, memaddr, info, 2); - break; - case FM01: - dis_2_short (insn, memaddr, info, 0); - break; - case FM10: - dis_2_short (insn, memaddr, info, 1); - break; - case FM11: - dis_long (insn, memaddr, info); - break; - } - return 4; -} - static void -print_operand (oper, insn, op, memaddr, info) - struct d10v_operand *oper; - unsigned long insn; - struct d10v_opcode *op; - bfd_vma memaddr; - struct disassemble_info *info; +print_operand (struct d10v_operand *oper, + unsigned long insn, + struct d10v_opcode *op, + bfd_vma memaddr, + struct disassemble_info *info) { int num, shift; @@ -114,13 +74,14 @@ print_operand (oper, insn, op, memaddr, info) { int i; int match = 0; + num += (oper->flags & (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)); if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1)) num += num ? OPERAND_ACC1 : OPERAND_ACC0; for (i = 0; i < d10v_reg_name_cnt (); i++) { - if (num == d10v_predefined_registers[i].value) + if (num == (d10v_predefined_registers[i].value & ~ OPERAND_SP)) { if (d10v_predefined_registers[i].pname) (*info->fprintf_func) (info->stream, "%s", @@ -142,7 +103,7 @@ print_operand (oper, insn, op, memaddr, info) (*info->fprintf_func) (info->stream, "cr"); else if (oper->flags & OPERAND_REG) (*info->fprintf_func) (info->stream, "r"); - (*info->fprintf_func) (info->stream, "%d", num); + (*info->fprintf_func) (info->stream, "%d", num & REGISTER_MASK); } } else @@ -152,6 +113,7 @@ print_operand (oper, insn, op, memaddr, info) { long max; int neg = 0; + max = (1 << (oper->bits - 1)); if (num & max) { @@ -186,13 +148,11 @@ print_operand (oper, insn, op, memaddr, info) } static void -dis_long (insn, memaddr, info) - unsigned long insn; - bfd_vma memaddr; - struct disassemble_info *info; +dis_long (unsigned long insn, + bfd_vma memaddr, + struct disassemble_info *info) { int i; - char buf[32]; struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes; struct d10v_operand *oper; int need_paren = 0; @@ -200,10 +160,12 @@ dis_long (insn, memaddr, info) while (op->name) { - if ((op->format & LONG_OPCODE) && ((op->mask & insn) == op->opcode)) + if ((op->format & LONG_OPCODE) + && ((op->mask & insn) == (unsigned long) op->opcode)) { match = 1; (*info->fprintf_func) (info->stream, "%s\t", op->name); + for (i = 0; op->operands[i]; i++) { oper = (struct d10v_operand *) &d10v_operands[op->operands[i]]; @@ -221,24 +183,21 @@ dis_long (insn, memaddr, info) } if (!match) - (*info->fprintf_func) (info->stream, ".long\t0x%08x", insn); + (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn); if (need_paren) (*info->fprintf_func) (info->stream, ")"); } static void -dis_2_short (insn, memaddr, info, order) - unsigned long insn; - bfd_vma memaddr; - struct disassemble_info *info; - int order; +dis_2_short (unsigned long insn, + bfd_vma memaddr, + struct disassemble_info *info, + int order) { int i, j; - char astr[2][32]; unsigned int ins[2]; struct d10v_opcode *op; - char buf[32]; int match, num_match = 0; struct d10v_operand *oper; int need_paren = 0; @@ -253,7 +212,8 @@ dis_2_short (insn, memaddr, info, order) while (op->name) { if ((op->format & SHORT_OPCODE) - && ((op->mask & ins[j]) == op->opcode)) + && ((((unsigned int) op->mask) & ins[j]) + == (unsigned int) op->opcode)) { (*info->fprintf_func) (info->stream, "%s\t", op->name); for (i = 0; op->operands[i]; i++) @@ -296,8 +256,42 @@ dis_2_short (insn, memaddr, info, order) } if (num_match == 0) - (*info->fprintf_func) (info->stream, ".long\t0x%08x", insn); + (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn); if (need_paren) (*info->fprintf_func) (info->stream, ")"); } + +int +print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + + status = insn & FM11; + switch (status) + { + case 0: + dis_2_short (insn, memaddr, info, 2); + break; + case FM01: + dis_2_short (insn, memaddr, info, 0); + break; + case FM10: + dis_2_short (insn, memaddr, info, 1); + break; + case FM11: + dis_long (insn, memaddr, info); + break; + } + return 4; +}