X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fd10v-opc.c;h=b2ce10f6163852530433769e78d5c6f861b37c20;hb=c2274b2767dba3175e585bd17f9f4a93b56cdc63;hp=1e099b6cee398db64e8620cdc2658366d8edf5e1;hpb=060d22b0d0cbc7786f83c236ed9812343530dc80;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c
index 1e099b6cee..b2ce10f616 100644
--- a/opcodes/d10v-opc.c
+++ b/opcodes/d10v-opc.c
@@ -1,5 +1,5 @@
 /* d10v-opc.c -- D10V opcode list
-   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
    Written by Martin Hunt, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -69,7 +69,7 @@ const struct pd_reg d10v_predefined_registers[] =
   { "r13", NULL, OPERAND_GPR+13 },
   { "r14", NULL, OPERAND_GPR+14 },
   { "r14-r15", NULL, OPERAND_GPR+14 },
-  { "r15", "sp", OPERAND_GPR+15 },
+  { "r15", "sp", OPERAND_SP|(OPERAND_GPR+15) },
   { "r2", NULL, OPERAND_GPR+2 },
   { "r2-r3", NULL, OPERAND_GPR+2 },
   { "r3", NULL, OPERAND_GPR+3 },
@@ -85,7 +85,7 @@ const struct pd_reg d10v_predefined_registers[] =
   { "rpt_c", NULL, OPERAND_CONTROL+7 },
   { "rpt_e", NULL, OPERAND_CONTROL+9 },
   { "rpt_s", NULL, OPERAND_CONTROL+8 },
-  { "sp", NULL, OPERAND_GPR+15 },
+  { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
 };
 
 int 
@@ -100,7 +100,11 @@ const struct d10v_operand d10v_operands[] =
   { 0, 0, 0 },
 #define RSRC	(UNUSED + 1)
   { 4, 1, OPERAND_GPR|OPERAND_REG },
-#define RDST	(RSRC + 1)
+#define RSRC_SP (RSRC + 1)
+  { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG },
+#define RSRC_NOSP (RSRC_SP + 1)
+  { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG },
+#define RDST	(RSRC_NOSP + 1)
   { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
 #define ASRC	(RDST + 1)
   { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
@@ -311,15 +315,15 @@ const struct d10v_opcode d10v_opcodes[] = {
   { "srx", SHORT_2, 1, IU, PAR|RF0, 0x4609, 0x7e1f, { RDST } },
   { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
   { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
-  { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC } },
+  { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } },
   { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
-  { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } },
+  { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } },
   { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } },
   { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
   { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
-  { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC } },
+  { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } },
   { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
-  { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } },
+  { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } },
   { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } },
   { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
   { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },